void bsp_start( void )
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
uintptr_t intrStackStart;
uintptr_t intrStackSize;
/*
* Note we can not get CPU identification dynamically, so
* force current_ppc_cpu.
*/
current_ppc_cpu = PPC_PSIM;
/*
* initialize the device driver parameters
* assume we are running with 20MHz bus
* this should speed up some tests :-)
*/
BSP_bus_frequency = 20;
bsp_time_base_frequency = 20000000;
bsp_clicks_per_usec = BSP_bus_frequency;
rtems_counter_initialize_converter(bsp_time_base_frequency);
/*
* Initialize the interrupt related settings.
*/
intrStackStart = (uintptr_t) bsp_interrupt_stack_start;
intrStackSize = (uintptr_t) bsp_interrupt_stack_size;
BSP_mem_size = (uint32_t )RamSize;
/*
* Initialize default raw exception handlers.
*/
ppc_exc_initialize(intrStackStart, intrStackSize);
/* Install default handler for the decrementer exception */
sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler);
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot install decrementer exception handler");
}
/* Initalize interrupt support */
bsp_interrupt_initialize();
#if 0
/*
* Setup BATs and enable MMU
*/
/* Memory */
setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW);
setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0);
/* PCI */
setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE);
setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE);
_write_MSR(_read_MSR() | MSR_DR | MSR_IR);
__asm__ volatile("sync; isync");
#endif
}
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
/*
* Note we can not get CPU identification dynamically.
* PVR has to be set to PPC_PSIM (0xfffe) from the device
* file.
*/
get_ppc_cpu_type();
/*
* initialize the device driver parameters
*/
BSP_bus_frequency = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND;
bsp_clicks_per_usec = BSP_bus_frequency;
BSP_time_base_divisor = 1;
/*
* The simulator likes the exception table to be at 0xfff00000.
*/
bsp_exceptions_in_RAM = FALSE;
/*
* Initialize default raw exception handlers.
*/
ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size()
);
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
/*
* Setup BATs and enable MMU
*/
/* Memory */
setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW);
setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0);
/* PCI */
setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE);
setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE);
_write_MSR(_read_MSR() | MSR_DR | MSR_IR);
__asm__ volatile("sync; isync");
}
