static int msm_bus_qos_enable_clk(struct msm_bus_node_device_type *node) { struct msm_bus_node_device_type *bus_node = NULL; long rounded_rate; int ret = 0; int bus_qos_enabled = 0; if (!node) { ret = -ENXIO; goto exit_enable_qos_clk; } bus_node = node->node_info->bus_device->platform_data; if (!bus_node) { ret = -ENXIO; goto exit_enable_qos_clk; } if (!clk_get_rate(bus_node->clk[DUAL_CTX].clk)) { rounded_rate = clk_round_rate(bus_node->clk[DUAL_CTX].clk, 1); ret = setrate_nodeclk(&bus_node->clk[DUAL_CTX], rounded_rate); if (ret) { MSM_BUS_ERR("%s: Failed to set bus clk, node %d", __func__, node->node_info->id); goto exit_enable_qos_clk; } ret = enable_nodeclk(&bus_node->clk[DUAL_CTX]); if (ret) { MSM_BUS_ERR("%s: Failed to enable bus clk, node %d", __func__, node->node_info->id); goto exit_enable_qos_clk; } bus_qos_enabled = 1; } if (!IS_ERR_OR_NULL(node->qos_clk.clk)) { rounded_rate = clk_round_rate(node->qos_clk.clk, 1); ret = setrate_nodeclk(&node->qos_clk, rounded_rate); if (ret) { MSM_BUS_ERR("Failed to set bus clk, node %d", node->node_info->id); goto exit_enable_qos_clk; } ret = enable_nodeclk(&node->qos_clk); if (ret) { MSM_BUS_ERR("Err enable mas qos clk, node %d ret %d", node->node_info->id, ret); goto exit_enable_qos_clk; } } ret = bus_qos_enabled; exit_enable_qos_clk: return ret; }
static int flush_clk_data(struct device *node_device, int ctx) { struct msm_bus_node_device_type *node; struct nodeclk *nodeclk = NULL; int ret = 0; node = node_device->platform_data; if (!node) { MSM_BUS_ERR("%s: Unable to find bus device for device %d", __func__, node->node_info->id); ret = -ENODEV; goto exit_flush_clk_data; } nodeclk = &node->clk[ctx]; if (node->node_info->is_fab_dev) { if (nodeclk->rate != node->cur_clk_hz[ctx]) { nodeclk->rate = node->cur_clk_hz[ctx]; nodeclk->dirty = true; } } if (nodeclk && nodeclk->clk && nodeclk->dirty) { long rounded_rate; if (nodeclk->rate) { rounded_rate = clk_round_rate(nodeclk->clk, nodeclk->rate); ret = setrate_nodeclk(nodeclk, rounded_rate); if (ret) { MSM_BUS_ERR("%s: Failed to set_rate %lu for %d", __func__, rounded_rate, node->node_info->id); ret = -ENODEV; goto exit_flush_clk_data; } ret = enable_nodeclk(nodeclk); } else ret = disable_nodeclk(nodeclk); if (ret) { MSM_BUS_ERR("%s: Failed to enable for %d", __func__, node->node_info->id); ret = -ENODEV; goto exit_flush_clk_data; } MSM_BUS_DBG("%s: Updated %d clk to %llu", __func__, node->node_info->id, nodeclk->rate); } exit_flush_clk_data: /* Reset the aggregated clock rate for fab devices*/ if (node->node_info->is_fab_dev) node->cur_clk_hz[ctx] = 0; nodeclk->dirty = 0; return ret; }