/*
Trigger the SPI DMA transfer. The parameters passed is used to identify the
mode of operation.
tx_data: !NULL, rx_data: NULL --> Half duplex write
tx_data: NULL, rx_data: !NULL --> Half duplex read
tx_data: !NULL, rx_data: !NULL --> Full duplex write-read
*/
static void trigger_spi_dma_transfer(struct spi_rtos_driver *rtos_drv,
const i8 *tx_data,
i8 *rx_data,
i32 size)
{
i32 chipsel_enable = 1;
/* Setup the SPI for DMA mode of tranfer */
cc_spi_control(rtos_drv->hal_handle, SPI_CTL_SET_DMA_RW, NULL);
/* Setup the DMA module for the transfer */
setup_dma_transfer(rtos_drv, tx_data, rx_data, size);
/* Initiate the DMA transfer */
cc_spi_control(rtos_drv->hal_handle,
SPI_CTL_CS_CTRL,
&chipsel_enable);
}
/*
Trigger the UART DMA transfer. The parameters passed is used to identify the
mode of operation.
tx_data: !NULL, rx_data: NULL --> Half duplex write
tx_data: NULL, rx_data: !NULL --> Half duplex read
tx_data: !NULL, rx_data: !NULL --> Full duplex write-read
*/
static void trigger_uart_dma_transfer(struct uart_rtos_driver *rtos_drv,
const i8 *tx_data,
i8 *rx_data,
i32 size)
{
i32 enable = 1;
/* Setup the DMA module for the transfer */
setup_dma_transfer(rtos_drv, tx_data, rx_data, size);
/* Initiate the DMA transfer */
if(tx_data != NULL){
cc_uart_control(rtos_drv->hal_handle,
e_start_tx_dma_transfer,
&enable);
}
if(rx_data != NULL){
cc_uart_control(rtos_drv->hal_handle,
e_start_rx_dma_transfer,
&enable);
}
}
/*
* Function called when the module is initialized
*/
static int __init dma_module_init(void) {
int error;
int i = 0;
transfers[0].data_type = OMAP_DMA_DATA_TYPE_S8;
/*transfers[1].data_type = OMAP_DMA_DATA_TYPE_S16;
transfers[2].data_type = OMAP_DMA_DATA_TYPE_S32;*/
for(i = 0; i < TRANSFER_COUNT; i++){
/* Create the transfer for the test */
transfers[i].device_id = OMAP_DMA_NO_DEVICE;
transfers[i].sync_mode = OMAP_DMA_SYNC_ELEMENT;
transfers[i].data_burst = OMAP_DMA_DATA_BURST_DIS;
transfers[i].endian_type = DMA_TEST_LITTLE_ENDIAN;
transfers[i].addressing_mode = OMAP_DMA_AMODE_POST_INC;
transfers[i].dst_addressing_mode = OMAP_DMA_AMODE_POST_INC;
transfers[i].priority = DMA_CH_PRIO_HIGH;
transfers[i].buffers.buf_size = (1024 * 1024);
/* Request a dma transfer */
error = request_dma(&transfers[i]);
if( error ){
set_test_passed(0);
return 1;
}
/* Request 2 buffer for the transfer and fill them */
error = create_transfer_buffers(&(transfers[i].buffers));
if( error ){
set_test_passed(0);
return 1;
}
fill_source_buffer(&(transfers[i].buffers));
/* Setup the dma transfer parameters */
setup_dma_transfer(&transfers[i]);
}
for(i = 0; i < TRANSFER_COUNT; i++){
/* Start the transfers */
start_dma_transfer(&transfers[i]);
}
/* Poll if the all the transfers have finished */
for(i = 0; i < TRANSFER_POLL_COUNT; i++){
if(get_transfers_finished()){
mdelay(TRANSFER_POLL_TIME);
check_test_passed();
break;
}else{
mdelay(TRANSFER_POLL_TIME);
}
}
/* This will happen if the poll retries have been reached*/
if(i == TRANSFER_POLL_COUNT){
set_test_passed(0);
return 1;
}
return 0;
}
/*
* Function called when the module is initialized
*/
static int __init dma_module_init(void) {
int error;
int i = 0;
wait_oswr_trigger = -1;
for (i = 0; i < TRANSFER_COUNT; i++) {
/* Create the transfer for the test */
transfers[i].device_id = OMAP_DMA_NO_DEVICE;
transfers[i].sync_mode = OMAP_DMA_SYNC_ELEMENT;
transfers[i].data_burst = OMAP_DMA_DATA_BURST_DIS;
transfers[i].data_type = OMAP_DMA_DATA_TYPE_S8;
transfers[i].endian_type = DMA_TEST_LITTLE_ENDIAN;
transfers[i].addressing_mode = OMAP_DMA_AMODE_POST_INC;
transfers[i].dst_addressing_mode = OMAP_DMA_AMODE_POST_INC;
transfers[i].priority = DMA_CH_PRIO_HIGH;
transfers[i].buffers.buf_size = (128 * (i+1)*(i+1)) + i % 2;
transfers[i].src_ei = transfers[i].dest_ei = 0;
transfers[i].src_fi = transfers[i].dest_fi = 0;
/* Request a dma transfer */
error = request_dma(&transfers[i]);
if( error ){
set_test_passed(0);
return 1;
}
/* Request 2 buffer for the transfer and fill them */
error = create_transfer_buffers(&(transfers[i].buffers));
if( error ){
set_test_passed(0);
return 1;
}
fill_source_buffer(&(transfers[i].buffers));
/* Setup the dma transfer parameters */
setup_dma_transfer(&transfers[i]);
}
for(i = 0; i < TRANSFER_COUNT; i++){
/* Start the transfers */
start_dma_transfer(&transfers[i]);
printk("Register Dump After configuration:\n");
printk("DMA channel number : %d\n", transfers[i].transfer_id);
dma_channel_registers_dump(transfers[i].transfer_id, reg_dump_after_config);
}
/* Poll if the all the transfers have finished */
for(i = 0; i < TRANSFER_POLL_COUNT; i++){
if(get_transfers_finished()){
mdelay(TRANSFER_POLL_TIME);
check_test_passed();
break;
}else{
mdelay(TRANSFER_POLL_TIME);
}
}
/* This will happen if the poll retries have been reached*/
if(i == TRANSFER_POLL_COUNT){
set_test_passed(0);
return 1;
}
return 0;
}
