void setup_soc_gpios(struct soc_gpio_config *config)
{
if (config) {
setup_gpios(config->ncore, &gpncore_bank);
setup_gpios(config->score, &gpscore_bank);
setup_gpios(config->ssus, &gpssus_bank);
setup_gpio_route(config->ssus, config->score);
if (config->core_dirq)
setup_dirqs(*config->core_dirq, &gpscore_bank);
if (config->sus_dirq)
setup_dirqs(*config->sus_dirq, &gpssus_bank);
}
}
static int __devinit tft_panel_probe(struct platform_device *plt_dev)
{
int ret;
printk(KERN_INFO "Broadcom TFT Panel Control Driver");
if (plt_dev->dev.platform_data == NULL) {
printk(KERN_ERR "%s() platform data is not present\n",
__func__);
return -ENODATA;
}
/* store pointer to platform data */
g_plt_data =
(struct tft_panel_platform_data *)plt_dev->dev.platform_data;
/* set up GPIOs */
ret = setup_gpios(g_plt_data);
if (ret != 0) {
printk(KERN_ERR "%s() setup_gpios() returned %d\n",
__func__, ret);
return ret;
}
#ifdef CONFIG_HAS_EARLYSUSPEND
register_early_suspend(&tft_panel_early_suspend_desc);
printk(KERN_INFO "%s() register for early suspend\n", __func__);
#endif /* CONFIG_HAS_EARLYSUSPEND */
printk(KERN_INFO "%s() TFT Panel Control Driver probed\n",
__func__);
return 0;
}
int main(void)
{
static unsigned int led_state = 0;
RCC_ClocksTypeDef clockinfo;
RCC_GetClocksFreq(&clockinfo);
// regardless of clock speed this gives us 1000 ticks per second
SysTick_Config(clockinfo.SYSCLK_Frequency / 1000);
int blink_speed_ms = 400;
setup_gpios();
setup_adc();
setup_usart();
setup_button_irqs();
kkputs("hello karl...\n");
uint64_t lasttime = millis();
while (1) {
if (millis() - blink_speed_ms > lasttime) {
if (led_state & 1) {
switch_leds_on();
kkputs("O");
} else {
switch_leds_off();
kkputs("o");
}
led_state ^= 1;
GPIO_TOGGLE(GPIOC, GPIO_Pin_3);
lasttime = millis();
}
if (button_pressed) {
button_pressed = 0;
kkputs("button was pressed!\n");
blink_speed_ms >>= 1;
if (blink_speed_ms <= 50) {
blink_speed_ms = 1000;
}
}
// start and wait for adc to convert...
ADC_RegularChannelConfig(ADC1, ADC_Channel_5, 1, ADC_SampleTime_192Cycles);
ADC_SoftwareStartConv(ADC1);
while (ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == 0)
;
uint16_t pot_val = ADC_GetConversionValue(ADC1);
if (pot_val > 0x700) {
GPIO_HIGH(GPIOA, GPIO_Pin_4);
} else {
GPIO_LOW(GPIOA, GPIO_Pin_4);
}
}
}
void app_main(void)
{
nvs_flash_init();
g_pot_event_group = xEventGroupCreate();
g_wifi_event_group = xEventGroupCreate();
setup_variables();
setup_wifi();
setup_gpios();
printf("v3 size: %d\n", sizeof(struct uni_proto_v3));
xTaskCreate(main_loop, "main_loop", 2048, NULL, 10, NULL);
xTaskCreate(wifi_loop, "wifi_loop", 2048, NULL, 10, NULL);
// xTaskCreate(test_loop, "test_loop", 2048, NULL, 10, NULL);
// main_loop(NULL);
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
#endif
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
setup_gpios();
#ifdef CONFIG_CMD_NAND
setup_gpmi_nand();
#endif
return 0;
}
int board_early_init_f(void)
{
init_drive_strength();
/* Setup debug led */
gpio_direction_output(6, 0);
mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
/* wait a little while to give the pll time to settle */
sdelay(100000);
setup_weim();
setup_uart();
setup_fec();
setup_gpios();
spi_io_init();
return 0;
}
void board_init_f(ulong dummy)
{
unsigned int ramchip;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 512 MB */
/* single chip select */
#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
.ncs = 1,
#else
.ncs = 2,
#endif
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
#ifdef CONFIG_CMD_NAND
/* Enable NAND */
setup_gpmi_nand();
#endif
/* setup clock gating */
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* setup AXI */
gpr_init();
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
setup_spi();
setup_gpios();
/* DDR initialization */
spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
ramchip = pfla02_detect_chiptype();
debug("Detected chip %d\n", ramchip);
#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
switch (ramchip) {
case RAM_MT64K:
sysinfo.cs_density = 6;
break;
case RAM_MT128K:
sysinfo.cs_density = 10;
break;
case RAM_MT256K:
sysinfo.cs_density = 18;
break;
}
#endif
spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
phyflex_err006282_workaround();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
