void board_init_f(ulong dummy) { #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); #endif /* setup clock gating */ ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* setup AXI */ gpr_init(); board_early_init_f(); /* setup GP timer */ timer_init(); setup_spi(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* Reset peripherals */ imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); gpio_direction_output(IMX_GPIO_NR(1, 3) , 0); udelay(500); gpio_set_value(IMX_GPIO_NR(1, 3), 1); #ifdef CONFIG_SYS_USE_SPINOR setup_spinor(); #endif #ifdef CONFIG_SYS_USE_EIMNOR setup_eimnor(); #endif #ifdef CONFIG_SYS_USE_NAND setup_gpmi_nand(); #endif #ifdef CONFIG_FEC_MXC setup_fec(); #endif #ifdef CONFIG_QSPI board_qspi_init(); #endif return 0; }
int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); iox74lv_init(); #ifdef CONFIG_SYS_I2C_MXC setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif #ifdef CONFIG_FEC_MXC setup_fec(CONFIG_FEC_ENET_DEV); #endif #ifdef CONFIG_SYS_USE_NAND setup_gpmi_nand(); #endif #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif return 0; }
int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_SYS_I2C_MXC setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); #endif /* Reset CPU_PER_RST_B signal for enet phy and PCIE */ port_exp_direction_output(CPU_PER_RST_B, 0); udelay(500); port_exp_direction_output(CPU_PER_RST_B, 1); /* Set steering signal to L for selecting B0 */ port_exp_direction_output(STEER_ENET, 0); #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif return 0; }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); iox74lv_init(); #ifdef CONFIG_FEC_MXC setup_fec(); #endif #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif #ifdef CONFIG_VIDEO_MXS setup_lcd(); #endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif return 0; }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); iox74lv_init(); #ifdef CONFIG_FEC_MXC setup_fec(); #endif #ifdef CONFIG_SYS_USE_NAND setup_gpmi_nand(); #endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif #ifdef CONFIG_MXC_EPDC qn_output[5] = qn_disable; iox74lv_set(5); setup_epdc(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif #ifdef CONFIG_MTD_NOR_FLASH eim_clk_setup(); #endif return 0; }
int board_early_init_f(void) { setup_iomux_uart(); #ifdef CONFIG_SYS_USE_NAND setup_gpmi_nand(); #endif #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif return 0; }
int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif return 0; }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_SYS_I2C_MXC setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); #endif #ifdef CONFIG_MXC_SPI setup_spi(); #endif #ifdef CONFIG_CMD_NAND setup_gpmi_nand(); #endif return 0; }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC setup_fec(); #endif #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif #ifdef CONFIG_VIDEO_MXS setup_lcd(); #endif return 0; }
int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_SYS_I2C_MXC setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif #ifdef CONFIG_FEC_MXC setup_fec(CONFIG_FEC_ENET_DEV); #endif #ifdef CONFIG_SYS_USE_SPINOR setup_spinor(); #endif #ifdef CONFIG_SYS_USE_NAND setup_gpmi_nand(); #endif #ifdef CONFIG_SYS_USE_EIMNOR /* * This function should be invoked after setup_fec, * because ENET2_RX_ER conflicts. However, we rarely need * ENET2_RX_ER for enet, and when use eimnor, we do not * have sd1/sd2, enet is a must to boot kernel and nfsrootfs. */ setup_eimnor(); #endif #ifdef CONFIG_SYS_USE_QSPI board_qspi_init(); #endif return 0; }
int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_SYS_I2C_MXC setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); #endif #ifdef CONFIG_MAX7310_IOEXP setup_max7310(); /* Reset CPU_PER_RST_B signal for enet phy and PCIE */ gpio_exp_direction_output(CPU_PER_RST_B, 0); udelay(500); gpio_exp_direction_output(CPU_PER_RST_B, 1); /* Set steering signal to L for selecting B0 */ gpio_exp_direction_output(STEER_ENET, 0); #endif #ifdef CONFIG_FEC_MXC setup_fec(CONFIG_FEC_ENET_DEV); #endif #ifdef CONFIG_SYS_USE_NAND setup_gpmi_nand(); #endif #ifdef CONFIG_QSPI board_qspi_init(); #endif return 0; }
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC setup_fec(); #endif #ifdef CONFIG_NAND_MXS setup_gpmi_nand(); #endif #ifdef CONFIG_VIDEO_MXS setup_lcd(); #endif #ifdef CONFIG_USB_EHCI_MX6 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); #endif return 0; }
void board_init_f(ulong dummy) { unsigned int ramchip; struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ .dsize = 2, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 512 MB */ /* single chip select */ #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) .ncs = 1, #else .ncs = 2, #endif .cs1_mirror = 1, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, .refsel = 1, /* Refresh cycles at 32KHz */ .refr = 7, /* 8 refresh commands per refresh cycle */ }; #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); #endif /* setup clock gating */ ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* setup AXI */ gpr_init(); board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); setup_spi(); setup_gpios(); /* DDR initialization */ spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]); ramchip = pfla02_detect_chiptype(); debug("Detected chip %d\n", ramchip); #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) switch (ramchip) { case RAM_MT64K: sysinfo.cs_density = 6; break; case RAM_MT128K: sysinfo.cs_density = 10; break; case RAM_MT256K: sysinfo.cs_density = 18; break; } #endif spl_dram_init(&sysinfo, &mt41k_xx[ramchip]); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); phyflex_err006282_workaround(); /* load/boot image from boot device */ board_init_r(NULL, 0); }