/* Create a new resource object, using the given template info */ struct pipe_resource * etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, uint64_t modifier, const struct pipe_resource *templat) { struct etna_screen *screen = etna_screen(pscreen); struct etna_resource *rsc; unsigned size; DBG_F(ETNA_DBG_RESOURCE_MSGS, "target=%d, format=%s, %ux%ux%u, array_size=%u, " "last_level=%u, nr_samples=%u, usage=%u, bind=%x, flags=%x", templat->target, util_format_name(templat->format), templat->width0, templat->height0, templat->depth0, templat->array_size, templat->last_level, templat->nr_samples, templat->usage, templat->bind, templat->flags); /* Determine scaling for antialiasing, allow override using debug flag */ int nr_samples = templat->nr_samples; if ((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) && !(templat->bind & PIPE_BIND_SAMPLER_VIEW)) { if (DBG_ENABLED(ETNA_DBG_MSAA_2X)) nr_samples = 2; if (DBG_ENABLED(ETNA_DBG_MSAA_4X)) nr_samples = 4; } int msaa_xscale = 1, msaa_yscale = 1; if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) { /* Number of samples not supported */ return NULL; } /* Determine needed padding (alignment of height/width) */ unsigned paddingX = 0, paddingY = 0; unsigned halign = TEXTURE_HALIGN_FOUR; if (!util_format_is_compressed(templat->format)) { /* If we have the TEXTURE_HALIGN feature, we can always align to the * resolve engine's width. If not, we must not align resources used * only for textures. If this GPU uses the BLT engine, never do RS align. */ bool rs_align = screen->specs.use_blt ? false : ( VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) || !etna_resource_sampler_only(templat)); etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX, &paddingY, &halign); assert(paddingX && paddingY); } else { /* Compressed textures are padded to their block size, but we don't have * to do anything special for that. */ paddingX = 1; paddingY = 1; } if (!screen->specs.use_blt && templat->target != PIPE_BUFFER) etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, &paddingY); if (templat->bind & PIPE_BIND_SCANOUT) { struct pipe_resource scanout_templat = *templat; struct renderonly_scanout *scanout; struct winsys_handle handle; /* pad scanout buffer size to be compatible with the RS */ if (!screen->specs.use_blt && modifier == DRM_FORMAT_MOD_LINEAR) etna_adjust_rs_align(screen->specs.pixel_pipes, &paddingX, &paddingY); scanout_templat.width0 = align(scanout_templat.width0, paddingX); scanout_templat.height0 = align(scanout_templat.height0, paddingY); scanout = renderonly_scanout_for_resource(&scanout_templat, screen->ro, &handle); if (!scanout) return NULL; assert(handle.type == WINSYS_HANDLE_TYPE_FD); handle.modifier = modifier; rsc = etna_resource(pscreen->resource_from_handle(pscreen, templat, &handle, PIPE_HANDLE_USAGE_WRITE)); close(handle.handle); if (!rsc) return NULL; rsc->scanout = scanout; return &rsc->base; } rsc = CALLOC_STRUCT(etna_resource); if (!rsc) return NULL; rsc->base = *templat; rsc->base.screen = pscreen; rsc->base.nr_samples = nr_samples; rsc->layout = layout; rsc->halign = halign; pipe_reference_init(&rsc->base.reference, 1); list_inithead(&rsc->list); size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale); uint32_t flags = DRM_ETNA_GEM_CACHE_WC; if (templat->bind & PIPE_BIND_VERTEX_BUFFER) flags |= DRM_ETNA_GEM_FORCE_MMU; struct etna_bo *bo = etna_bo_new(screen->dev, size, flags); if (unlikely(bo == NULL)) { BUG("Problem allocating video memory for resource"); goto free_rsc; } rsc->bo = bo; rsc->ts_bo = 0; /* TS is only created when first bound to surface */ if (DBG_ENABLED(ETNA_DBG_ZERO)) { void *map = etna_bo_map(bo); memset(map, 0, size); } return &rsc->base; free_rsc: FREE(rsc); return NULL; }
/* Create a new resource object, using the given template info */ struct pipe_resource * etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout, const struct pipe_resource *templat) { struct etna_screen *screen = etna_screen(pscreen); unsigned size; DBG_F(ETNA_DBG_RESOURCE_MSGS, "target=%d, format=%s, %ux%ux%u, array_size=%u, " "last_level=%u, nr_samples=%u, usage=%u, bind=%x, flags=%x", templat->target, util_format_name(templat->format), templat->width0, templat->height0, templat->depth0, templat->array_size, templat->last_level, templat->nr_samples, templat->usage, templat->bind, templat->flags); /* Determine scaling for antialiasing, allow override using debug flag */ int nr_samples = templat->nr_samples; if ((templat->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) && !(templat->bind & PIPE_BIND_SAMPLER_VIEW)) { if (DBG_ENABLED(ETNA_DBG_MSAA_2X)) nr_samples = 2; if (DBG_ENABLED(ETNA_DBG_MSAA_4X)) nr_samples = 4; } int msaa_xscale = 1, msaa_yscale = 1; if (!translate_samples_to_xyscale(nr_samples, &msaa_xscale, &msaa_yscale, NULL)) { /* Number of samples not supported */ return NULL; } /* If we have the TEXTURE_HALIGN feature, we can always align to the * resolve engine's width. If not, we must not align resources used * only for textures. */ bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) || !etna_resource_sampler_only(templat); /* Determine needed padding (alignment of height/width) */ unsigned paddingX = 0, paddingY = 0; unsigned halign = TEXTURE_HALIGN_FOUR; etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX, &paddingY, &halign); assert(paddingX && paddingY); if (templat->bind != PIPE_BUFFER) { unsigned min_paddingY = 4 * screen->specs.pixel_pipes; if (paddingY < min_paddingY) paddingY = min_paddingY; } struct etna_resource *rsc = CALLOC_STRUCT(etna_resource); if (!rsc) return NULL; rsc->base = *templat; rsc->base.screen = pscreen; rsc->base.nr_samples = nr_samples; rsc->layout = layout; rsc->halign = halign; pipe_reference_init(&rsc->base.reference, 1); list_inithead(&rsc->list); size = setup_miptree(rsc, paddingX, paddingY, msaa_xscale, msaa_yscale); uint32_t flags = DRM_ETNA_GEM_CACHE_WC; if (templat->bind & PIPE_BIND_VERTEX_BUFFER) flags |= DRM_ETNA_GEM_FORCE_MMU; struct etna_bo *bo = etna_bo_new(screen->dev, size, flags); if (unlikely(bo == NULL)) { BUG("Problem allocating video memory for resource"); return NULL; } rsc->bo = bo; rsc->ts_bo = 0; /* TS is only created when first bound to surface */ if (templat->bind & PIPE_BIND_SCANOUT) rsc->scanout = renderonly_scanout_for_resource(&rsc->base, screen->ro); if (DBG_ENABLED(ETNA_DBG_ZERO)) { void *map = etna_bo_map(bo); memset(map, 0, size); } return &rsc->base; }