/* Set conn->state to READING when done; otherwise, call a cm_set_. */ static krb5_boolean service_https_write(krb5_context context, const krb5_data *realm, struct conn_state *conn, struct select_state *selstate) { k5_tls_status st; /* If this is our first time in here, set up the SSL context. */ if (conn->http.tls == NULL && !setup_tls(context, realm, conn, selstate)) { kill_conn(context, conn, selstate); return FALSE; } /* Try to transmit our request to the server. */ st = context->tls->write(context, conn->http.tls, SG_BUF(conn->out.sgp), SG_LEN(conn->out.sgbuf)); if (st == DONE) { TRACE_SENDTO_KDC_HTTPS_SEND(context, &conn->addr); cm_read(selstate, conn->fd); conn->state = READING; } else if (st == WANT_READ) { cm_read(selstate, conn->fd); } else if (st == WANT_WRITE) { cm_write(selstate, conn->fd); } else if (st == ERROR_TLS) { TRACE_SENDTO_KDC_HTTPS_ERROR_SEND(context, &conn->addr); kill_conn(context, conn, selstate); } return FALSE; }
/* * Setup L4 architecture requirements: * kip_area, utcb_area, physical memory, current, * Init user address space, ramdisk, console, early consle */ void __init setup_arch (char **command_line) { unsigned long base, area; #if defined(CONFIG_IGUANA) setup_tls(1); #endif /* Return the command line to the rest of the kernel */ boot_command_line[COMMAND_LINE_SIZE-1] = '\0'; *command_line = boot_command_line; if (L4_UtcbIsKernelManaged()) { utcb_area = L4_Nilpage; } else { /* Currently hardcoded to 1024 L4 threads per linux * user address space */ area = L4_GetUtcbSize() * 1024; /* * Find some area to put the utcb in outside user's * area. When the KIP was present, 16 pages were * reserved for it, so keep the same spacing here * because the equation is not fully understood. */ base = PAGE_ALIGN(TASK_SIZE) + 16 * PAGE_SIZE + area; /* Round address to the 'area' boundary. */ base = (base + (area-1)) & (~(area-1)); utcb_area = L4_Fpage(base, L4_GetUtcbSize() * 1024); } /* Initialise our machine name */ setup_machine_name(); /* FIXME: (why?) */ start_phys_mem = __pa(start_phys_mem); end_phys_mem = __pa(end_phys_mem); /* Initialise paging */ paging_init(); /* Thread info setup. */ /* FIXME: remember for SMP startup */ current_tinfo(smp_processor_id()) = (unsigned long)&init_thread_union.thread_info; task_thread_info(current)->user_tid = L4_nilthread; task_thread_info(current)->user_handle = L4_nilthread; #ifdef CONFIG_EARLY_PRINTK /* early console initialisation */ enable_early_printk(); #endif /* Ramdisk setup */ #ifdef CONFIG_BLK_DEV_INITRD /* Board specific code should have set up initrd_start and initrd_end */ ROOT_DEV = Root_RAM0; /* FIXME! */ initrd_start = 0; //naming_lookup("ramdisk"); initrd_end = 0; //naming_lookup("ramdisk_end"); printk("end: %lx\n", initrd_end); initrd_below_start_ok = 1; if (initrd_start) { unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start); printk("Initial ramdisk at: 0x%p (%lu bytes)\n", (void *)initrd_start, initrd_size); } #endif /* CONFIG_BLK_DEV_INITRD */ #ifdef CONFIG_VT #if defined(CONFIG_VGA_CONSOLE) __setup_vga(); conswitchp = &vga_con; #elif defined(CONFIG_DUMMY_CONSOLE) conswitchp = &dummy_con; #endif /* CONFIG_VGA_CONSOLE */ screen_info.lfb_base = 0xe000000; screen_info.lfb_size = 600*800; screen_info.lfb_height = 600; screen_info.lfb_width = 800; #endif /* CONFIG_VT */ panic_timeout = 1; #if defined(CONFIG_CELL) /* L4-specific -gl,cvs */ { extern unsigned long TIMER_BASE, SERIAL_BASE; okl4_env_lookup_address("MAIN_TIMER_MEM0", &TIMER_BASE); okl4_env_lookup_address("MAIN_SERIAL_MEM0", &SERIAL_BASE); } #if defined(CONFIG_VERSATILE) { extern unsigned long ETH_BASE, CLCD_BASE, VERSATILE_SYS_BASE, KMI0_BASE, KMI1_BASE; okl4_env_lookup_address("MAIN_ETH_MEM0", Ð_BASE); okl4_env_lookup_address("MAIN_VERSATILESYS_MEM0", &VERSATILE_SYS_BASE); okl4_env_lookup_address("MAIN_CLCD_MEM0", &CLCD_BASE); okl4_env_lookup_address("MAIN_KMI0_MEM0", &KMI0_BASE); okl4_env_lookup_address("MAIN_KMI1_MEM0", &KMI1_BASE); } #endif #if defined(CONFIG_ARCH_GUMSTIX) { extern unsigned long GPIO_BASE, DMAC_BASE; extern unsigned long PXA_CS1_PHYS, PXA_CS1_DMA; extern unsigned long PXA_CS2_PHYS, PXA_CS2_DMA; okl4_env_lookup_address("MAIN_GPIO_MEM0", &GPIO_BASE); okl4_env_lookup_address("MAIN_DMA_MEM0", &DMAC_BASE); okl4_env_lookup_address("MAIN_CS_MEM1", &PXA_CS1_PHYS); okl4_env_lookup_address("MAIN_CS_MEM2", &PXA_CS2_PHYS); PXA_CS1_DMA = *((unsigned long *)okl4_env_get("cs_mem1_physical")); PXA_CS2_DMA = *((unsigned long *)okl4_env_get("cs_mem2_physical")); } #endif #endif /*CELL*/ }