int main(int argc, char *argv[])
{
mrp_mainloop_t *ml;
mrp_clear(&cfg);
parse_cmdline(&cfg, argc, argv);
mrp_log_set_mask(cfg.log_mask);
mrp_log_set_target(cfg.log_target);
ml = mainloop_create(&cfg);
if (ml == NULL)
fatal("failed to create main loop.");
dbus_test.ml = ml;
setup_dbus_tests(ml);
ml = dbus_test.ml;
setup_timers(ml);
setup_io(ml);
setup_signals(ml);
MRP_UNUSED(setup_deferred); /* XXX TODO: add deferred tests... */
#ifdef GLIB_ENABLED
if (cfg.mainloop_type != MAINLOOP_GLIB && cfg.mainloop_type != MAINLOOP_QT) {
if (cfg.ngio > 0 || cfg.ngtimer > 0)
glib_pump_setup(ml);
}
setup_glib_io();
setup_glib_timers();
#endif
if (mrp_add_timer(ml, 1000, check_quit, NULL) == NULL)
fatal("failed to create quit-check timer");
setup_wakeup(ml);
mainloop_run(&cfg);
check_io();
check_timers();
check_signals();
#ifdef GLIB_ENABLED
check_glib_io();
check_glib_timers();
#endif
if (dbus_test.client != 0)
close(dbus_test.pipe[1]); /* let the client continue */
check_dbus();
#ifdef GLIB_ENABLED
if (cfg.mainloop_type != MAINLOOP_GLIB) {
if (cfg.ngio > 0 || cfg.ngtimer > 0)
glib_pump_cleanup();
}
#endif
cleanup_wakeup();
mainloop_cleanup(&cfg);
}
static void omap5evm_mux_init(void)
{
/* core padconf essential */
setup_core(CONTROL_PADCONF_EMMC_CLK, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_CMD, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA0, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA1, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA2, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA3, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA4, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA5, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA6, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_EMMC_DATA7, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_SDCARD_CLK, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_SDCARD_CMD, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_SDCARD_DATA0, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_SDCARD_DATA1, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_SDCARD_DATA2, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_SDCARD_DATA3, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_UART3_RX_IRRX, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_UART3_TX_IRTX, (M0));
/* wakeup padconf essential */
setup_wakeup(CONTROL_WAKEUP_SR_PMIC_SCL, (PTU | IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SR_PMIC_SDA, (PTU | IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_32K, (IEN | M0));
/* core padconf non-essential */
setup_core(CONTROL_PADCONF_C2C_DATAIN0, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATAIN1, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATAIN2, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATAIN3, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATAIN4, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATAIN5, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATAIN6, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATAIN7, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_CLKIN1, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_CLKIN0, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_CLKOUT0, (M0));
setup_core(CONTROL_PADCONF_C2C_CLKOUT1, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT0, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT1, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT2, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT3, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT4, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT5, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT6, (M0));
setup_core(CONTROL_PADCONF_C2C_DATAOUT7, (M0));
setup_core(CONTROL_PADCONF_C2C_DATA8, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATA9, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATA10, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATA11, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATA12, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATA13, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATA14, (IEN | M0));
setup_core(CONTROL_PADCONF_C2C_DATA15, (IEN | M0));
setup_core(CONTROL_PADCONF_LLIB_WAKEREQOUT, (PTU | IEN | M6));
setup_core(CONTROL_PADCONF_LLIA_WAKEREQOUT, (M1));
setup_core(CONTROL_PADCONF_HSI1_ACREADY, (PTD | M6));
setup_core(CONTROL_PADCONF_HSI1_CAREADY, (PTD | M6));
setup_core(CONTROL_PADCONF_HSI1_ACWAKE, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_HSI1_CAWAKE, (PTU | IEN | M6));
setup_core(CONTROL_PADCONF_HSI1_ACFLAG, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_HSI1_ACDATA, (PTD | M6));
setup_core(CONTROL_PADCONF_HSI1_CAFLAG, (M6));
setup_core(CONTROL_PADCONF_HSI1_CADATA, (M6));
setup_core(CONTROL_PADCONF_UART1_TX, (M0));
setup_core(CONTROL_PADCONF_UART1_CTS, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_UART1_RX, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_UART1_RTS, (M0));
setup_core(CONTROL_PADCONF_HSI2_CAREADY, (IEN | M0));
setup_core(CONTROL_PADCONF_HSI2_ACREADY, (OFF_EN | M0));
setup_core(CONTROL_PADCONF_HSI2_CAWAKE, (IEN | PTD | M0));
setup_core(CONTROL_PADCONF_HSI2_ACWAKE, (M0));
setup_core(CONTROL_PADCONF_HSI2_CAFLAG, (IEN | PTD | M0));
setup_core(CONTROL_PADCONF_HSI2_CADATA, (IEN | PTD | M0));
setup_core(CONTROL_PADCONF_HSI2_ACDATA, (M0));
setup_core(CONTROL_PADCONF_HSI2_ACFLAG, (M0));
setup_core(CONTROL_PADCONF_UART2_RTS, (IEN | M1));
setup_core(CONTROL_PADCONF_UART2_CTS, (IEN | M1));
setup_core(CONTROL_PADCONF_UART2_RX, (IEN | M1));
setup_core(CONTROL_PADCONF_UART2_TX, (IEN | M1));
setup_core(CONTROL_PADCONF_USBB1_HSIC_STROBE, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_USBB1_HSIC_DATA, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_USBB2_HSIC_STROBE, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_USBB2_HSIC_DATA, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_TIMER10_PWM_EVT, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_TE0, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE0X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE0Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE1X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE1Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE2X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE2Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE3X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE3Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE4X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTA_LANE4Y, (IEN | M0));
setup_core(CONTROL_PADCONF_TIMER9_PWM_EVT, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_TE0, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE0X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE0Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE1X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE1Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE2X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE2Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE3X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE3Y, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE4X, (IEN | M0));
setup_core(CONTROL_PADCONF_DSIPORTC_LANE4Y, (IEN | M0));
setup_core(CONTROL_PADCONF_RFBI_HSYNC0, (M4));
setup_core(CONTROL_PADCONF_RFBI_TE_VSYNC0, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_RE, (M4));
setup_core(CONTROL_PADCONF_RFBI_A0, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA8, (M4));
setup_core(CONTROL_PADCONF_RFBI_DATA9, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA10, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA11, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA12, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA13, (PTU | IEN | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA14, (M4));
setup_core(CONTROL_PADCONF_RFBI_DATA15, (M4));
setup_core(CONTROL_PADCONF_GPIO6_182, (M6));
setup_core(CONTROL_PADCONF_GPIO6_183, (PTD | M6));
setup_core(CONTROL_PADCONF_GPIO6_184, (M4));
setup_core(CONTROL_PADCONF_GPIO6_185, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_GPIO6_186, (PTD | M6));
setup_core(CONTROL_PADCONF_GPIO6_187, (PTU | IEN | M4));
setup_core(CONTROL_PADCONF_RFBI_DATA0, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA1, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA2, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA3, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA4, (IEN | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA5, (IEN | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA6, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_DATA7, (PTD | M6));
setup_core(CONTROL_PADCONF_RFBI_CS0, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_RFBI_WE, (PTD | M6));
setup_core(CONTROL_PADCONF_MCSPI2_CS0, (M0));
setup_core(CONTROL_PADCONF_MCSPI2_CLK, (IEN | M0));
setup_core(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | M0));
setup_core(CONTROL_PADCONF_MCSPI2_SOMI, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_I2C4_SCL, (IEN | M0));
setup_core(CONTROL_PADCONF_I2C4_SDA, (IEN | M0));
setup_core(CONTROL_PADCONF_HDMI_CEC, (IEN | M0));
setup_core(CONTROL_PADCONF_HDMI_HPD, (PTD | IEN | M0));
setup_core(CONTROL_PADCONF_HDMI_DDC_SCL, (IEN | M0));
setup_core(CONTROL_PADCONF_HDMI_DDC_SDA, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE0X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE0Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE1Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE1X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE2Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE2X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE3X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE3Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE4X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTA_LANE4Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTB_LANE0X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTB_LANE0Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTB_LANE1Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTB_LANE1X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTB_LANE2Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTB_LANE2X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTC_LANE0Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTC_LANE0X, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTC_LANE1Y, (IEN | M0));
setup_core(CONTROL_PADCONF_CSIPORTC_LANE1X, (IEN | M0));
setup_core(CONTROL_PADCONF_CAM_SHUTTER, (M0));
setup_core(CONTROL_PADCONF_CAM_STROBE, (M0));
setup_core(CONTROL_PADCONF_CAM_GLOBALRESET, (IEN | M0));
setup_core(CONTROL_PADCONF_TIMER11_PWM_EVT, (PTD | M6));
setup_core(CONTROL_PADCONF_TIMER5_PWM_EVT, (PTD | M6));
setup_core(CONTROL_PADCONF_TIMER6_PWM_EVT, (PTD | M6));
setup_core(CONTROL_PADCONF_TIMER8_PWM_EVT, (PTU | M6));
setup_core(CONTROL_PADCONF_I2C3_SCL, (IEN | M0));
setup_core(CONTROL_PADCONF_I2C3_SDA, (IEN | M0));
setup_core(CONTROL_PADCONF_GPIO8_233, (IEN | M2));
setup_core(CONTROL_PADCONF_ABE_CLKS, (IEN | M0));
setup_core(CONTROL_PADCONF_ABEDMIC_DIN1, (IEN | M0));
setup_core(CONTROL_PADCONF_ABEDMIC_DIN2, (IEN | M0));
setup_core(CONTROL_PADCONF_ABEDMIC_DIN3, (IEN | M0));
setup_core(CONTROL_PADCONF_ABEDMIC_CLK1, (M0));
setup_core(CONTROL_PADCONF_ABEDMIC_CLK2, (IEN | M1));
setup_core(CONTROL_PADCONF_ABEDMIC_CLK3, (M1));
setup_core(CONTROL_PADCONF_ABESLIMBUS1_CLOCK, (IEN | M1));
setup_core(CONTROL_PADCONF_ABESLIMBUS1_DATA, (IEN | M1));
setup_core(CONTROL_PADCONF_ABEMCBSP2_DR, (IEN | M0));
setup_core(CONTROL_PADCONF_ABEMCBSP2_DX, (M0));
setup_core(CONTROL_PADCONF_ABEMCBSP2_FSX, (IEN | M0));
setup_core(CONTROL_PADCONF_ABEMCBSP2_CLKX, (IEN | M0));
setup_core(CONTROL_PADCONF_ABEMCPDM_UL_DATA,
(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0));
setup_core(CONTROL_PADCONF_ABEMCPDM_DL_DATA,
(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0));
setup_core(CONTROL_PADCONF_ABEMCPDM_FRAME,
(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0));
setup_core(CONTROL_PADCONF_ABEMCPDM_LB_CLK,
(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0));
setup_core(CONTROL_PADCONF_WLSDIO_CLK, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_WLSDIO_CMD, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_WLSDIO_DATA0, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_WLSDIO_DATA1, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_WLSDIO_DATA2, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_WLSDIO_DATA3, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_UART5_RX, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_UART5_TX, (M0));
setup_core(CONTROL_PADCONF_UART5_CTS, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_UART5_RTS, (M0));
setup_core(CONTROL_PADCONF_I2C2_SCL, (IEN | M0));
setup_core(CONTROL_PADCONF_I2C2_SDA, (IEN | M0));
setup_core(CONTROL_PADCONF_MCSPI1_CLK, (M6));
setup_core(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | M6));
setup_core(CONTROL_PADCONF_MCSPI1_SIMO, (PTD | M6));
setup_core(CONTROL_PADCONF_MCSPI1_CS0, (PTD | M6));
setup_core(CONTROL_PADCONF_MCSPI1_CS1, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_I2C5_SCL, (IEN | M0));
setup_core(CONTROL_PADCONF_I2C5_SDA, (IEN | M0));
setup_core(CONTROL_PADCONF_PERSLIMBUS2_CLOCK, (PTD | M6));
setup_core(CONTROL_PADCONF_PERSLIMBUS2_DATA, (PTD | IEN | M6));
setup_core(CONTROL_PADCONF_UART6_TX, (PTU | IEN | M6));
setup_core(CONTROL_PADCONF_UART6_RX, (PTU | IEN | M6));
setup_core(CONTROL_PADCONF_UART6_CTS, (PTU | IEN | M6));
setup_core(CONTROL_PADCONF_UART6_RTS, (PTU | M0));
setup_core(CONTROL_PADCONF_UART3_CTS_RCTX, (PTU | IEN | M6));
setup_core(CONTROL_PADCONF_UART3_RTS_IRSD, (PTU | IEN | M1));
setup_core(CONTROL_PADCONF_USBB3_HSIC_STROBE, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_USBB3_HSIC_DATA, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_USBD0_HS_DP, (IEN | M0));
setup_core(CONTROL_PADCONF_USBD0_HS_DM, (IEN | M0));
setup_core(CONTROL_PADCONF_USBD0_SS_RX, (IEN | M0));
setup_core(CONTROL_PADCONF_I2C1_PMIC_SCL, (PTU | IEN | M0));
setup_core(CONTROL_PADCONF_I2C1_PMIC_SDA, (PTU | IEN | M0));
/* wakeup padconf non-essential */
setup_wakeup(CONTROL_WAKEUP_LLIA_WAKEREQIN, (M7));
setup_wakeup(CONTROL_WAKEUP_LLIB_WAKEREQIN, (M7));
setup_wakeup(CONTROL_WAKEUP_DRM_EMU0, (PTU | IEN | M0));
setup_wakeup(CONTROL_WAKEUP_DRM_EMU1, (PTU | IEN | M0));
setup_wakeup(CONTROL_WAKEUP_JTAG_NTRST, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_JTAG_TCK, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_JTAG_RTCK, (M0));
setup_wakeup(CONTROL_WAKEUP_JTAG_TMSC, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_JTAG_TDI, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_JTAG_TDO, (M0));
setup_wakeup(CONTROL_WAKEUP_FREF_CLK_IOREQ, (IEN | PTD | M0));
setup_wakeup(CONTROL_WAKEUP_FREF_CLK0_OUT, (M0));
setup_wakeup(CONTROL_WAKEUP_FREF_CLK1_OUT, (M0));
setup_wakeup(CONTROL_WAKEUP_FREF_CLK2_OUT, (M0));
setup_wakeup(CONTROL_WAKEUP_FREF_CLK2_REQ, (PTU | IEN | M6));
setup_wakeup(CONTROL_WAKEUP_FREF_CLK1_REQ, (PTD | IEN | M6));
setup_wakeup(CONTROL_WAKEUP_SYS_NRESPWRON, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_NRESWARM, (PTU | IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_PWR_REQ, (M0));
setup_wakeup(CONTROL_WAKEUP_SYS_NIRQ1, (PTU | IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_NIRQ2, (PTU | IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_BOOT0, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_BOOT1, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_BOOT2, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_BOOT3, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_BOOT4, (IEN | M0));
setup_wakeup(CONTROL_WAKEUP_SYS_BOOT5, (IEN | M0));
}
static void panda_mux_init(void)
{
setup_core(CONTROL_PADCONF_GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat0 */
setup_core(CONTROL_PADCONF_GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat1 */
setup_core(CONTROL_PADCONF_GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat2 */
setup_core(CONTROL_PADCONF_GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat3 */
setup_core(CONTROL_PADCONF_GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat4 */
setup_core(CONTROL_PADCONF_GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat5 */
setup_core(CONTROL_PADCONF_GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat6 */
setup_core(CONTROL_PADCONF_GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_dat7 */
setup_core(CONTROL_PADCONF_GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)); /* gpio_32 */
setup_core(CONTROL_PADCONF_GPMC_AD9, (PTU | IEN | M3)); /* gpio_33 */
setup_core(CONTROL_PADCONF_GPMC_AD10, (PTU | IEN | M3)); /* gpio_34 */
setup_core(CONTROL_PADCONF_GPMC_AD11, (PTU | IEN | M3)); /* gpio_35 */
setup_core(CONTROL_PADCONF_GPMC_AD12, (PTU | IEN | M3)); /* gpio_36 */
setup_core(CONTROL_PADCONF_GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_37 */
setup_core(CONTROL_PADCONF_GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_38 */
setup_core(CONTROL_PADCONF_GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_39 */
setup_core(CONTROL_PADCONF_GPMC_A16, (M3)); /* gpio_40 */
setup_core(CONTROL_PADCONF_GPMC_A17, (PTD | M3)); /* gpio_41 */
setup_core(CONTROL_PADCONF_GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row6 */
setup_core(CONTROL_PADCONF_GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row7 */
setup_core(CONTROL_PADCONF_GPMC_A20, (IEN | M3)); /* gpio_44 */
setup_core(CONTROL_PADCONF_GPMC_A21, (M3)); /* gpio_45 */
setup_core(CONTROL_PADCONF_GPMC_A22, (M3)); /* gpio_46 */
setup_core(CONTROL_PADCONF_GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col7 */
setup_core(CONTROL_PADCONF_GPMC_A24, (PTD | M3)); /* gpio_48 */
setup_core(CONTROL_PADCONF_GPMC_A25, (PTD | M3)); /* gpio_49 */
setup_core(CONTROL_PADCONF_GPMC_NCS0, (M3)); /* gpio_50 */
setup_core(CONTROL_PADCONF_GPMC_NCS1, (IEN | M3)); /* gpio_51 */
setup_core(CONTROL_PADCONF_GPMC_NCS2, (IEN | M3)); /* gpio_52 */
setup_core(CONTROL_PADCONF_GPMC_NCS3, (IEN | M3)); /* gpio_53 */
setup_core(CONTROL_PADCONF_GPMC_NWP, (M3)); /* gpio_54 */
setup_core(CONTROL_PADCONF_GPMC_CLK, (PTD | M3)); /* gpio_55 */
setup_core(CONTROL_PADCONF_GPMC_NADV_ALE, (M3)); /* gpio_56 */
setup_core(CONTROL_PADCONF_GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)); /* sdmmc2_clk */
setup_core(CONTROL_PADCONF_GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* sdmmc2_cmd */
setup_core(CONTROL_PADCONF_GPMC_NBE0_CLE, (M3)); /* gpio_59 */
setup_core(CONTROL_PADCONF_GPMC_NBE1, (PTD | M3)); /* gpio_60 */
setup_core(CONTROL_PADCONF_GPMC_WAIT0, (PTU | IEN | M3)); /* gpio_61 */
setup_core(CONTROL_PADCONF_GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_62 */
setup_core(CONTROL_PADCONF_C2C_DATA11, (PTD | M3)); /* gpio_100 */
setup_core(CONTROL_PADCONF_C2C_DATA12, (PTU | IEN | M3)); /* gpio_101 */
setup_core(CONTROL_PADCONF_C2C_DATA13, (PTD | M3)); /* gpio_102 */
setup_core(CONTROL_PADCONF_C2C_DATA14, ( M1)); /* dsi2_te0 */
setup_core(CONTROL_PADCONF_C2C_DATA15, (PTD | M3)); /* gpio_104 */
setup_core(CONTROL_PADCONF_HDMI_HPD, (M0)); /* hdmi_hpd */
setup_core(CONTROL_PADCONF_HDMI_CEC, (M0)); /* hdmi_cec */
setup_core(CONTROL_PADCONF_HDMI_DDC_SCL, (PTU | M0)); /* hdmi_ddc_scl */
setup_core(CONTROL_PADCONF_HDMI_DDC_SDA, (PTU | IEN | M0)); /* hdmi_ddc_sda */
setup_core(CONTROL_PADCONF_CSI21_DX0, (IEN | M0)); /* csi21_dx0 */
setup_core(CONTROL_PADCONF_CSI21_DY0, (IEN | M0)); /* csi21_dy0 */
setup_core(CONTROL_PADCONF_CSI21_DX1, (IEN | M0)); /* csi21_dx1 */
setup_core(CONTROL_PADCONF_CSI21_DY1, (IEN | M0)); /* csi21_dy1 */
setup_core(CONTROL_PADCONF_CSI21_DX2, (IEN | M0)); /* csi21_dx2 */
setup_core(CONTROL_PADCONF_CSI21_DY2, (IEN | M0)); /* csi21_dy2 */
setup_core(CONTROL_PADCONF_CSI21_DX3, (PTD | M7)); /* csi21_dx3 */
setup_core(CONTROL_PADCONF_CSI21_DY3, (PTD | M7)); /* csi21_dy3 */
setup_core(CONTROL_PADCONF_CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)); /* csi21_dx4 */
setup_core(CONTROL_PADCONF_CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)); /* csi21_dy4 */
setup_core(CONTROL_PADCONF_CSI22_DX0, (IEN | M0)); /* csi22_dx0 */
setup_core(CONTROL_PADCONF_CSI22_DY0, (IEN | M0)); /* csi22_dy0 */
setup_core(CONTROL_PADCONF_CSI22_DX1, (IEN | M0)); /* csi22_dx1 */
setup_core(CONTROL_PADCONF_CSI22_DY1, (IEN | M0)); /* csi22_dy1 */
setup_core(CONTROL_PADCONF_CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)); /* cam_shutter */
setup_core(CONTROL_PADCONF_CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)); /* cam_strobe */
setup_core(CONTROL_PADCONF_CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)); /* gpio_83 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_clk */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)); /* usbb1_ulpiphy_stp */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dir */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_nxt */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat0 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat1 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat2 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat3 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat4 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat5 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat6 */
setup_core(CONTROL_PADCONF_USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)); /* usbb1_ulpiphy_dat7 */
setup_core(CONTROL_PADCONF_USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usbb1_hsic_data */
setup_core(CONTROL_PADCONF_USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usbb1_hsic_strobe */
setup_core(CONTROL_PADCONF_USBC1_ICUSB_DP, (IEN | M0)); /* usbc1_icusb_dp */
setup_core(CONTROL_PADCONF_USBC1_ICUSB_DM, (IEN | M0)); /* usbc1_icusb_dm */
setup_core(CONTROL_PADCONF_SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)); /* sdmmc1_clk */
setup_core(CONTROL_PADCONF_SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_cmd */
setup_core(CONTROL_PADCONF_SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat0 */
setup_core(CONTROL_PADCONF_SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat1 */
setup_core(CONTROL_PADCONF_SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat2 */
setup_core(CONTROL_PADCONF_SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat3 */
setup_core(CONTROL_PADCONF_SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat4 */
setup_core(CONTROL_PADCONF_SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat5 */
setup_core(CONTROL_PADCONF_SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat6 */
setup_core(CONTROL_PADCONF_SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc1_dat7 */
setup_core(CONTROL_PADCONF_ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_mcbsp2_clkx */
setup_core(CONTROL_PADCONF_ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)); /* abe_mcbsp2_dr */
setup_core(CONTROL_PADCONF_ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)); /* abe_mcbsp2_dx */
setup_core(CONTROL_PADCONF_ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_mcbsp2_fsx */
setup_core(CONTROL_PADCONF_ABE_MCBSP1_CLKX, (IEN | M1)); /* abe_slimbus1_clock */
setup_core(CONTROL_PADCONF_ABE_MCBSP1_DR, (IEN | M1)); /* abe_slimbus1_data */
setup_core(CONTROL_PADCONF_ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)); /* abe_mcbsp1_dx */
setup_core(CONTROL_PADCONF_ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_mcbsp1_fsx */
setup_core(CONTROL_PADCONF_ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_ul_data */
setup_core(CONTROL_PADCONF_ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_dl_data */
setup_core(CONTROL_PADCONF_ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_frame */
setup_core(CONTROL_PADCONF_ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_pdm_lb_clk */
setup_core(CONTROL_PADCONF_ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* abe_clks */
setup_core(CONTROL_PADCONF_ABE_DMIC_CLK1, (M0)); /* abe_dmic_clk1 */
setup_core(CONTROL_PADCONF_ABE_DMIC_DIN1, (IEN | M0)); /* abe_dmic_din1 */
setup_core(CONTROL_PADCONF_ABE_DMIC_DIN2, (PTU | IEN | M3));
setup_core(CONTROL_PADCONF_ABE_DMIC_DIN3, (IEN | M0)); /* abe_dmic_din3 */
setup_core(CONTROL_PADCONF_UART2_CTS, (PTU | IEN | M0)); /* uart2_cts */
setup_core(CONTROL_PADCONF_UART2_RTS, (M0)); /* uart2_rts */
setup_core(CONTROL_PADCONF_UART2_RX, (PTU | IEN | M0)); /* uart2_rx */
setup_core(CONTROL_PADCONF_UART2_TX, (M0)); /* uart2_tx */
setup_core(CONTROL_PADCONF_HDQ_SIO, (M3)); /* gpio_127 */
setup_core(CONTROL_PADCONF_I2C1_SCL, (PTU | IEN | M0)); /* i2c1_scl */
setup_core(CONTROL_PADCONF_I2C1_SDA, (PTU | IEN | M0)); /* i2c1_sda */
setup_core(CONTROL_PADCONF_I2C2_SCL, (PTU | IEN | M0)); /* i2c2_scl */
setup_core(CONTROL_PADCONF_I2C2_SDA, (PTU | IEN | M0)); /* i2c2_sda */
setup_core(CONTROL_PADCONF_I2C3_SCL, (PTU | IEN | M0)); /* i2c3_scl */
setup_core(CONTROL_PADCONF_I2C3_SDA, (PTU | IEN | M0)); /* i2c3_sda */
setup_core(CONTROL_PADCONF_I2C4_SCL, (PTU | IEN | M0)); /* i2c4_scl */
setup_core(CONTROL_PADCONF_I2C4_SDA, (PTU | IEN | M0)); /* i2c4_sda */
setup_core(CONTROL_PADCONF_MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_clk */
setup_core(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_somi */
setup_core(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_simo */
setup_core(CONTROL_PADCONF_MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi1_cs0 */
setup_core(CONTROL_PADCONF_MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)); /* mcspi1_cs1 */
setup_core(CONTROL_PADCONF_MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)); /* gpio_139 */
setup_core(CONTROL_PADCONF_MCSPI1_CS3, (PTU | IEN | M3)); /* gpio_140 */
setup_core(CONTROL_PADCONF_UART3_CTS_RCTX, (PTU | IEN | M0)); /* uart3_tx */
setup_core(CONTROL_PADCONF_UART3_RTS_SD, (M0)); /* uart3_rts_sd */
setup_core(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | M0)); /* uart3_rx */
setup_core(CONTROL_PADCONF_UART3_TX_IRTX, (M0)); /* uart3_tx */
setup_core(CONTROL_PADCONF_SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)); /* sdmmc5_clk */
setup_core(CONTROL_PADCONF_SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_cmd */
setup_core(CONTROL_PADCONF_SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat0 */
setup_core(CONTROL_PADCONF_SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat1 */
setup_core(CONTROL_PADCONF_SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat2 */
setup_core(CONTROL_PADCONF_SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* sdmmc5_dat3 */
setup_core(CONTROL_PADCONF_MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_clk */
setup_core(CONTROL_PADCONF_MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_simo */
setup_core(CONTROL_PADCONF_MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_somi */
setup_core(CONTROL_PADCONF_MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* mcspi4_cs0 */
setup_core(CONTROL_PADCONF_UART4_RX, (IEN | M0)); /* uart4_rx */
setup_core(CONTROL_PADCONF_UART4_TX, (M0)); /* uart4_tx */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_CLK, (IEN | M3)); /* gpio_157 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_STP, (IEN | M5)); /* dispc2_data23 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DIR, (IEN | M5)); /* dispc2_data22 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_NXT, (IEN | M5)); /* dispc2_data21 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT0, (IEN | M5)); /* dispc2_data20 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT1, (IEN | M5)); /* dispc2_data19 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT2, (IEN | M5)); /* dispc2_data18 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT3, (IEN | M5)); /* dispc2_data15 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT4, (IEN | M5)); /* dispc2_data14 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT5, (IEN | M5)); /* dispc2_data13 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT6, (IEN | M5)); /* dispc2_data12 */
setup_core(CONTROL_PADCONF_USBB2_ULPITLL_DAT7, (IEN | M5)); /* dispc2_data11 */
setup_core(CONTROL_PADCONF_USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)); /* gpio_169 */
setup_core(CONTROL_PADCONF_USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)); /* gpio_170 */
setup_core(CONTROL_PADCONF_UNIPRO_TX0, (PTD | IEN | M3)); /* gpio_171 */
setup_core(CONTROL_PADCONF_UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col1 */
setup_core(CONTROL_PADCONF_UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col2 */
setup_core(CONTROL_PADCONF_UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_col3 */
setup_core(CONTROL_PADCONF_UNIPRO_TX2, (PTU | IEN | M3)); /* gpio_0 */
setup_core(CONTROL_PADCONF_UNIPRO_TY2, (PTU | IEN | M3)); /* gpio_1 */
setup_core(CONTROL_PADCONF_UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row0 */
setup_core(CONTROL_PADCONF_UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row1 */
setup_core(CONTROL_PADCONF_UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row2 */
setup_core(CONTROL_PADCONF_UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row3 */
setup_core(CONTROL_PADCONF_UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row4 */
setup_core(CONTROL_PADCONF_UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)); /* kpd_row5 */
setup_core(CONTROL_PADCONF_USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)); /* usba0_otg_ce */
setup_core(CONTROL_PADCONF_USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usba0_otg_dp */
setup_core(CONTROL_PADCONF_USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)); /* usba0_otg_dm */
setup_core(CONTROL_PADCONF_FREF_CLK1_OUT, (M0)); /* fref_clk1_out */
setup_core(CONTROL_PADCONF_FREF_CLK2_OUT, (PTU | IEN | M3)); /* gpio_182 */
setup_core(CONTROL_PADCONF_SYS_NIRQ1, (PTU | IEN | M0)); /* sys_nirq1 */
setup_core(CONTROL_PADCONF_SYS_NIRQ2, (PTU | IEN | M0)); /* sys_nirq2 */
setup_core(CONTROL_PADCONF_SYS_BOOT0, (PTU | IEN | M3)); /* gpio_184 */
setup_core(CONTROL_PADCONF_SYS_BOOT1, (M3)); /* gpio_185 */
setup_core(CONTROL_PADCONF_SYS_BOOT2, (PTD | IEN | M3)); /* gpio_186 */
setup_core(CONTROL_PADCONF_SYS_BOOT3, (M3)); /* gpio_187 */
setup_core(CONTROL_PADCONF_SYS_BOOT4, (M3)); /* gpio_188 */
setup_core(CONTROL_PADCONF_SYS_BOOT5, (PTD | IEN | M3)); /* gpio_189 */
setup_core(CONTROL_PADCONF_DPM_EMU0, (IEN | M0)); /* dpm_emu0 */
setup_core(CONTROL_PADCONF_DPM_EMU1, (IEN | M0)); /* dpm_emu1 */
setup_core(CONTROL_PADCONF_DPM_EMU2, (IEN | M0)); /* dpm_emu2 */
setup_core(CONTROL_PADCONF_DPM_EMU3, (IEN | M5)); /* dispc2_data10 */
setup_core(CONTROL_PADCONF_DPM_EMU4, (IEN | M5)); /* dispc2_data9 */
setup_core(CONTROL_PADCONF_DPM_EMU5, (IEN | M5)); /* dispc2_data16 */
setup_core(CONTROL_PADCONF_DPM_EMU6, (IEN | M5)); /* dispc2_data17 */
setup_core(CONTROL_PADCONF_DPM_EMU7, (IEN | M5)); /* dispc2_hsync */
setup_core(CONTROL_PADCONF_DPM_EMU8, (IEN | M5)); /* dispc2_pclk */
setup_core(CONTROL_PADCONF_DPM_EMU9, (IEN | M5)); /* dispc2_vsync */
setup_core(CONTROL_PADCONF_DPM_EMU10, (IEN | M5)); /* dispc2_de */
setup_core(CONTROL_PADCONF_DPM_EMU11, (IEN | M5)); /* dispc2_data8 */
setup_core(CONTROL_PADCONF_DPM_EMU12, (IEN | M5)); /* dispc2_data7 */
setup_core(CONTROL_PADCONF_DPM_EMU13, (IEN | M5)); /* dispc2_data6 */
setup_core(CONTROL_PADCONF_DPM_EMU14, (IEN | M5)); /* dispc2_data5 */
setup_core(CONTROL_PADCONF_DPM_EMU15, (IEN | M5)); /* dispc2_data4 */
setup_core(CONTROL_PADCONF_DPM_EMU16, (M3)); /* gpio_27 */
setup_core(CONTROL_PADCONF_DPM_EMU17, (IEN | M5)); /* dispc2_data2 */
setup_core(CONTROL_PADCONF_DPM_EMU18, (IEN | M5)); /* dispc2_data1 */
setup_core(CONTROL_PADCONF_DPM_EMU19, (IEN | M5)); /* dispc2_data0 */
setup_wakeup(CONTROL_WKUP_PAD0_SIM_IO, (IEN | M0)); /* sim_io */
setup_wakeup(CONTROL_WKUP_PAD1_SIM_CLK, (M0)); /* sim_clk */
setup_wakeup(CONTROL_WKUP_PAD0_SIM_RESET, (M0)); /* sim_reset */
setup_wakeup(CONTROL_WKUP_PAD1_SIM_CD, (PTU | IEN | M0)); /* sim_cd */
setup_wakeup(CONTROL_WKUP_PAD0_SIM_PWRCTRL, (M0)); /* sim_pwrctrl */
setup_wakeup(CONTROL_WKUP_PAD1_SR_SCL, (PTU | IEN | M0)); /* sr_scl */
setup_wakeup(CONTROL_WKUP_PAD0_SR_SDA, (PTU | IEN | M0)); /* sr_sda */
setup_wakeup(CONTROL_WKUP_PAD1_FREF_XTAL_IN, (M0)); /* # */
setup_wakeup(CONTROL_WKUP_PAD0_FREF_SLICER_IN, (M0)); /* fref_slicer_in */
setup_wakeup(CONTROL_WKUP_PAD1_FREF_CLK_IOREQ, (M0)); /* fref_clk_ioreq */
setup_wakeup(CONTROL_WKUP_PAD0_FREF_CLK0_OUT, (M2)); /* sys_drm_msecure */
setup_wakeup(CONTROL_WKUP_PAD1_FREF_CLK3_REQ, (M3)); /* gpio_wk30 */
setup_wakeup(CONTROL_WKUP_PAD0_FREF_CLK3_OUT, (M0)); /* fref_clk3_out */
setup_wakeup(CONTROL_WKUP_PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)); /* # */
setup_wakeup(CONTROL_WKUP_PAD0_FREF_CLK4_OUT, (M0)); /* # */
setup_wakeup(CONTROL_WKUP_PAD1_SYS_32K, (IEN | M0)); /* sys_32k */
setup_wakeup(CONTROL_WKUP_PAD0_SYS_NRESPWRON, (M0)); /* sys_nrespwron */
setup_wakeup(CONTROL_WKUP_PAD1_SYS_NRESWARM, (M0)); /* sys_nreswarm */
setup_wakeup(CONTROL_WKUP_PAD0_SYS_PWR_REQ, (PTU | M0)); /* sys_pwr_req */
setup_wakeup(CONTROL_WKUP_PAD1_SYS_PWRON_RESET, (M3)); /* gpio_wk29 */
setup_wakeup(CONTROL_WKUP_PAD0_SYS_BOOT6, (IEN | M3)); /* gpio_wk9 */
setup_wakeup(CONTROL_WKUP_PAD1_SYS_BOOT7, (IEN | M3)); /* gpio_wk10 */
setup_wakeup(CONTROL_WKUP_PAD1_FREF_CLK3_REQ, (M3)); /* gpio_wk30 */
setup_wakeup(CONTROL_WKUP_PAD1_FREF_CLK4_REQ, (M3)); /* gpio_wk7 */
setup_wakeup(CONTROL_WKUP_PAD0_FREF_CLK4_OUT, (M3)); /* gpio_wk8 */
}
