/*
* Initializes UART access. The callback function will be called once
* per found UART.
*/
void
BCMATTACHFN(si_serial_init)(si_t *sih, si_serial_init_fn add)
{
osl_t *osh;
void *regs;
chipcregs_t *cc;
uint32 rev, cap, pll, baud_base, div;
uint irq;
int i, n;
osh = si_osh(sih);
cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);
ASSERT(cc);
/* Determine core revision and capabilities */
rev = sih->ccrev;
cap = sih->cccaps;
pll = cap & CC_CAP_PLL_MASK;
/* Determine IRQ */
irq = si_irq(sih);
if (CCPLL_ENAB(sih) && pll == PLL_TYPE1) {
/* PLL clock */
baud_base = si_clock_rate(pll,
R_REG(osh, &cc->clockcontrol_n),
R_REG(osh, &cc->clockcontrol_m2));
div = 1;
} else {
/* Fixed ALP clock */
if (rev >= 11 && rev != 15) {
baud_base = si_alp_clock(sih);
div = 1;
/* Turn off UART clock before switching clock source */
if (rev >= 21)
AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
/* Set the override bit so we don't divide it */
OR_REG(osh, &cc->corecontrol, CC_UARTCLKO);
if (rev >= 21)
OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
} else if (rev >= 3) {
/* Internal backplane clock */
baud_base = si_clock(sih);
div = 2; /* Minimum divisor */
W_REG(osh, &cc->clkdiv,
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
} else {
/* Fixed internal backplane clock */
baud_base = 88000000;
div = 48;
}
/* Clock source depends on strapping if UartClkOverride is unset */
if ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0) {
if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) {
/* Internal divided backplane clock */
baud_base /= div;
} else {
/* Assume external clock of 1.8432 MHz */
baud_base = 1843200;
}
}
}
/* Add internal UARTs */
n = cap & CC_CAP_UARTS_MASK;
for (i = 0; i < n; i++) {
regs = (void *)((ulong) &cc->uart0data + (i * 256));
if (add)
add(regs, irq, baud_base, 0);
}
}
static void
chipreset(struct bcm4xxx *ch)
{
bcmenetregs_t *regs;
uint32 clk, mdc;
ET_TRACE(("et%d: chipreset\n", ch->etc->unit));
regs = ch->regs;
if (!si_iscoreup(ch->sih)) {
if (!ch->etc->nicmode)
si_pci_setup(ch->sih, (1 << si_coreidx(ch->sih)));
/* power on reset: reset the enet core */
si_core_reset(ch->sih, 0, 0);
goto chipinreset;
}
/* read counters before resetting the chip */
if (ch->mibgood)
chipstatsupd(ch);
/* reset the tx dma engine */
if (ch->di)
dma_txreset(ch->di);
/* set emac into loopback mode to ensure no rx traffic */
W_REG(ch->osh, ®s->rxconfig, ERC_LE);
OSL_DELAY(1);
/* reset the rx dma engine */
if (ch->di)
dma_rxreset(ch->di);
/* reset core */
si_core_reset(ch->sih, 0, 0);
chipinreset:
/* must clear mib registers by hand */
W_REG(ch->osh, ®s->mibcontrol, EMC_RZ);
(void) R_REG(ch->osh, ®s->mib.tx_broadcast_pkts);
(void) R_REG(ch->osh, ®s->mib.tx_multicast_pkts);
(void) R_REG(ch->osh, ®s->mib.tx_len_64);
(void) R_REG(ch->osh, ®s->mib.tx_len_65_to_127);
(void) R_REG(ch->osh, ®s->mib.tx_len_128_to_255);
(void) R_REG(ch->osh, ®s->mib.tx_len_256_to_511);
(void) R_REG(ch->osh, ®s->mib.tx_len_512_to_1023);
(void) R_REG(ch->osh, ®s->mib.tx_len_1024_to_max);
(void) R_REG(ch->osh, ®s->mib.tx_jabber_pkts);
(void) R_REG(ch->osh, ®s->mib.tx_oversize_pkts);
(void) R_REG(ch->osh, ®s->mib.tx_fragment_pkts);
(void) R_REG(ch->osh, ®s->mib.tx_underruns);
(void) R_REG(ch->osh, ®s->mib.tx_total_cols);
(void) R_REG(ch->osh, ®s->mib.tx_single_cols);
(void) R_REG(ch->osh, ®s->mib.tx_multiple_cols);
(void) R_REG(ch->osh, ®s->mib.tx_excessive_cols);
(void) R_REG(ch->osh, ®s->mib.tx_late_cols);
(void) R_REG(ch->osh, ®s->mib.tx_defered);
(void) R_REG(ch->osh, ®s->mib.tx_carrier_lost);
(void) R_REG(ch->osh, ®s->mib.tx_pause_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_broadcast_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_multicast_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_len_64);
(void) R_REG(ch->osh, ®s->mib.rx_len_65_to_127);
(void) R_REG(ch->osh, ®s->mib.rx_len_128_to_255);
(void) R_REG(ch->osh, ®s->mib.rx_len_256_to_511);
(void) R_REG(ch->osh, ®s->mib.rx_len_512_to_1023);
(void) R_REG(ch->osh, ®s->mib.rx_len_1024_to_max);
(void) R_REG(ch->osh, ®s->mib.rx_jabber_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_oversize_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_fragment_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_missed_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_crc_align_errs);
(void) R_REG(ch->osh, ®s->mib.rx_undersize);
(void) R_REG(ch->osh, ®s->mib.rx_crc_errs);
(void) R_REG(ch->osh, ®s->mib.rx_align_errs);
(void) R_REG(ch->osh, ®s->mib.rx_symbol_errs);
(void) R_REG(ch->osh, ®s->mib.rx_pause_pkts);
(void) R_REG(ch->osh, ®s->mib.rx_nonpause_pkts);
ch->mibgood = TRUE;
/*
* We want the phy registers to be accessible even when
* the driver is "downed" so initialize MDC preamble, frequency,
* and whether internal or external phy here.
*/
/* default: 100Mhz SI clock and external phy */
W_REG(ch->osh, ®s->mdiocontrol, 0x94);
if (ch->etc->deviceid == BCM47XX_ENET_ID) {
/* 47xx chips: find out the clock */
if ((clk = si_clock(ch->sih)) != 0) {
mdc = 0x80 | ((clk + (MDC_RATIO / 2)) / MDC_RATIO);
W_REG(ch->osh, ®s->mdiocontrol, mdc);
} else {
ET_ERROR(("et%d: chipreset: Could not figure out backplane clock, "
"using 100Mhz\n",
ch->etc->unit));
}
}
/* some chips have internal phy, some don't */
if (!(R_REG(ch->osh, ®s->devcontrol) & DC_IP)) {
W_REG(ch->osh, ®s->enetcontrol, EC_EP);
} else if (R_REG(ch->osh, ®s->devcontrol) & DC_ER) {
AND_REG(ch->osh, ®s->devcontrol, ~DC_ER);
OSL_DELAY(100);
chipphyinit(ch, ch->etc->phyaddr);
}
/* clear persistent sw intstatus */
ch->intstatus = 0;
}
/*
* Initializes UART access. The callback function will be called once
* per found UART.
*/
void
BCMINITFN(si_serial_init)(si_t *sih, si_serial_init_fn add, uint32 baudrate)
{
osl_t *osh;
void *regs;
chipcregs_t *cc;
uint32 rev, cap, pll, baud_base, div;
uint irq;
int i, n;
osh = si_osh(sih);
cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);
ASSERT(cc);
/* Determine core revision and capabilities */
rev = sih->ccrev;
cap = sih->cccaps;
pll = cap & CC_CAP_PLL_MASK;
/* Determine IRQ */
irq = si_irq(sih);
if (CCPLL_ENAB(sih) && pll == PLL_TYPE1) {
/* PLL clock */
baud_base = si_clock_rate(pll,
R_REG(osh, &cc->clockcontrol_n),
R_REG(osh, &cc->clockcontrol_m2));
div = 1;
} else {
/* Fixed ALP clock */
/* XXX rev. 15 in 4785 breaks the rule! */
if (rev >= 11 && rev != 15) {
baud_base = si_alp_clock(sih);
div = 1;
/*
* If baudrate parameter is given with a non-zero value,
* UART clock will be divided for the given baud rate before
* feeding into UART module.
* Note: UART driver could also adjust UART module's divider for
* clock fine tunning.
*/
if (baudrate) {
/* Turn off UART clock before switching clock source */
if (rev >= 21)
AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
/* Don't set the override bit so we divide it */
AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKO);
div = baud_base / (baudrate * 16);
div = (div + 1) & ~0x1;
AND_REG(osh, &cc->clkdiv, ~CLKD_UART);
OR_REG(osh, &cc->clkdiv, div);
/* Turn back UART clock on */
if (rev >= 21)
OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
} else {
/* Turn off UART clock before switching clock source */
if (rev >= 21)
AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
OR_REG(osh, &cc->corecontrol, CC_UARTCLKO);
/* Turn back UART clock on */
if (rev >= 21)
OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
}
if (CONSOLE_TTY == 1) {
/* Use UART1, enable "UART1 use GPIO" bit */
OR_REG(osh, &cc->corecontrol, 0x80);
}
} else if (rev >= 3) {
/* Internal backplane clock */
baud_base = si_clock(sih);
div = 2; /* Minimum divisor */
W_REG(osh, &cc->clkdiv,
((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
} else {
/* Fixed internal backplane clock */
baud_base = 88000000;
div = 48;
}
/* Clock source depends on strapping if UartClkOverride is unset */
if ((rev > 0) &&
((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) {
/* Internal divided backplane clock */
baud_base /= div;
} else {
/* Assume external clock of 1.8432 MHz */
baud_base = 1843200;
}
}
}
/* Add internal UARTs */
n = cap & CC_CAP_UARTS_MASK;
for (i = 0; i < n; i++) {
/* Register offset changed after revision 0 */
if (rev)
regs = (void *)((ulong) &cc->uart0data + (i * 256));
else
regs = (void *)((ulong) &cc->uart0data + (i * 8));
if (add)
add(regs, irq, baud_base, 0);
}
}
static void *
chipattach(etc_info_t *etc, void *osh, void *regsva)
{
struct bcm4xxx *ch;
bcmenetregs_t *regs;
char name[16];
char *var;
uint boardflags, boardtype;
ET_TRACE(("et%d: chipattach: regsva 0x%lx\n", etc->unit, (ulong)regsva));
if ((ch = (struct bcm4xxx *)MALLOC(osh, sizeof(struct bcm4xxx))) == NULL) {
ET_ERROR(("et%d: chipattach: out of memory, malloced %d bytes\n", etc->unit,
MALLOCED(osh)));
return (NULL);
}
bzero((char *)ch, sizeof(struct bcm4xxx));
ch->etc = etc;
ch->et = etc->et;
ch->osh = osh;
/* store the pointer to the sw mib */
etc->mib = (void *)&ch->mib;
/* get si handle */
if ((ch->sih = si_attach(etc->deviceid, ch->osh, regsva, PCI_BUS, NULL, &ch->vars,
&ch->vars_size)) == NULL) {
ET_ERROR(("et%d: chipattach: si_attach error\n", etc->unit));
goto fail;
}
/* We used to have an assert here like:
* si_coreid(ch->sih) == ENET_CORE_ID
* but srom-less systems and simulators don't have a way to
* provide a default bar0window so we were relying on nvram
* variables. At some point we decided that we could do away
* with that since the wireless driver was simply doing a
* setcore in attach. So we need to do the same here for
* the ethernet.
*/
if ((regs = (bcmenetregs_t *)si_setcore(ch->sih, ENET_CORE_ID, etc->unit)) == NULL) {
ET_ERROR(("et%d: chipattach: Could not setcore to the ENET core\n", etc->unit));
goto fail;
}
ch->regs = regs;
etc->chip = ch->sih->chip;
etc->chiprev = ch->sih->chiprev;
etc->coreid = si_coreid(ch->sih);
etc->corerev = si_corerev(ch->sih);
etc->nicmode = !(ch->sih->bustype == SI_BUS);
etc->coreunit = si_coreunit(ch->sih);
etc->boardflags = getintvar(ch->vars, "boardflags");
etc->hwrxoff = HWRXOFF;
boardflags = etc->boardflags;
boardtype = ch->sih->boardtype;
/* Backplane clock ticks per microsecs: used by gptimer, intrecvlazy */
etc->bp_ticks_usec = si_clock(ch->sih) / 1000000;
/* get our local ether addr */
sprintf(name, "et%dmacaddr", etc->coreunit);
var = getvar(ch->vars, name);
if (var == NULL) {
ET_ERROR(("et%d: chipattach: NVRAM_GET(%s) not found\n", etc->unit, name));
goto fail;
}
bcm_ether_atoe(var, &etc->perm_etheraddr);
if (ETHER_ISNULLADDR(&etc->perm_etheraddr)) {
ET_ERROR(("et%d: chipattach: invalid format: %s=%s\n", etc->unit, name, var));
goto fail;
}
bcopy((char *)&etc->perm_etheraddr, (char *)&etc->cur_etheraddr, ETHER_ADDR_LEN);
/*
* Too much can go wrong in scanning MDC/MDIO playing "whos my phy?" .
* Instead, explicitly require the environment var "et<coreunit>phyaddr=<val>".
*/
/* get our phyaddr value */
sprintf(name, "et%dphyaddr", etc->coreunit);
var = getvar(ch->vars, name);
if (var == NULL) {
ET_ERROR(("et%d: chipattach: NVRAM_GET(%s) not found\n", etc->unit, name));
goto fail;
}
etc->phyaddr = bcm_atoi(var) & EPHY_MASK;
/* nvram says no phy is present */
if (etc->phyaddr == EPHY_NONE) {
ET_ERROR(("et%d: chipattach: phy not present\n", etc->unit));
goto fail;
}
/* get our mdc/mdio port number */
sprintf(name, "et%dmdcport", etc->coreunit);
var = getvar(ch->vars, name);
if (var == NULL) {
ET_ERROR(("et%d: chipattach: NVRAM_GET(%s) not found\n", etc->unit, name));
goto fail;
}
etc->mdcport = bcm_atoi(var);
/* configure pci core */
si_pci_setup(ch->sih, (1 << si_coreidx(ch->sih)));
/* reset the enet core */
chipreset(ch);
/* dma attach */
sprintf(name, "et%d", etc->coreunit);
if ((ch->di = dma_attach(osh, name, ch->sih,
(void *)®s->dmaregs.xmt, (void *)®s->dmaregs.rcv,
NTXD, NRXD, RXBUFSZ, -1, NRXBUFPOST, HWRXOFF,
&et_msg_level)) == NULL) {
ET_ERROR(("et%d: chipattach: dma_attach failed\n", etc->unit));
goto fail;
}
etc->txavail[TX_Q0] = (uint *)&ch->di->txavail;
/* set default sofware intmask */
ch->intmask = DEF_INTMASK;
/*
* For the 5222 dual phy shared mdio contortion, our phy is
* on someone elses mdio pins. This other enet enet
* may not yet be attached so we must defer the et_phyfind().
*/
/* if local phy: reset it once now */
if (etc->mdcport == etc->coreunit)
chipphyreset(ch, etc->phyaddr);
#ifdef ETROBO
/*
* Broadcom Robo ethernet switch.
*/
if ((boardflags & BFL_ENETROBO) &&
(etc->phyaddr == EPHY_NOREG)) {
/* Attach to the switch */
if (!(etc->robo = bcm_robo_attach(ch->sih, ch, ch->vars,
(miird_f)bcm47xx_et_chops.phyrd,
(miiwr_f)bcm47xx_et_chops.phywr))) {
ET_ERROR(("et%d: chipattach: robo_attach failed\n", etc->unit));
goto fail;
}
/* Enable the switch and set it to a known good state */
if (bcm_robo_enable_device(etc->robo)) {
ET_ERROR(("et%d: chipattach: robo_enable_device failed\n", etc->unit));
goto fail;
}
/* Configure the switch to do VLAN */
if ((boardflags & BFL_ENETVLAN) &&
bcm_robo_config_vlan(etc->robo, etc->perm_etheraddr.octet)) {
ET_ERROR(("et%d: chipattach: robo_config_vlan failed\n", etc->unit));
goto fail;
}
/* Enable switching/forwarding */
if (bcm_robo_enable_switch(etc->robo)) {
ET_ERROR(("et%d: chipattach: robo_enable_switch failed\n", etc->unit));
goto fail;
}
}
#endif /* ETROBO */
#ifdef ETADM
/*
* ADMtek ethernet switch.
*/
if (boardflags & BFL_ENETADM) {
/* Attach to the device */
if (!(ch->adm = adm_attach(ch->sih, ch->vars))) {
ET_ERROR(("et%d: chipattach: adm_attach failed\n", etc->unit));
goto fail;
}
/* Enable the external switch and set it to a known good state */
if (adm_enable_device(ch->adm)) {
ET_ERROR(("et%d: chipattach: adm_enable_device failed\n", etc->unit));
goto fail;
}
/* Configure the switch */
if ((boardflags & BFL_ENETVLAN) && adm_config_vlan(ch->adm)) {
ET_ERROR(("et%d: chipattach: adm_config_vlan failed\n", etc->unit));
goto fail;
}
}
#endif /* ETADM */
return ((void *)ch);
fail:
chipdetach(ch);
return (NULL);
}
