void
memerr4_4c(unsigned int issync,
u_int ser, u_int sva, u_int aer, u_int ava,
struct trapframe *tf) /* XXX - unused/invalid */
{
char bits[64];
u_int pte;
snprintb(bits, sizeof(bits), SER_BITS, ser);
printf("%ssync mem arr: ser=%s sva=0x%x ",
issync ? "" : "a", bits, sva);
snprintb(bits, sizeof(bits), AER_BITS, aer & 0xff);
printf("aer=%s ava=0x%x\n", bits, ava);
pte = getpte4(sva);
if ((pte & PG_V) != 0 && (pte & PG_TYPE) == PG_OBMEM) {
u_int pa = (pte & PG_PFNUM) << PGSHIFT;
printf(" spa=0x%x, module location: %s\n", pa,
prom_pa_location(pa, 0));
}
pte = getpte4(ava);
if ((pte & PG_V) != 0 && (pte & PG_TYPE) == PG_OBMEM) {
u_int pa = (pte & PG_PFNUM) << PGSHIFT;
printf(" apa=0x%x, module location: %s\n", pa,
prom_pa_location(pa, 0));
}
if (par_err_reg) {
snprintb(bits, sizeof(bits), PER_BITS, *par_err_reg);
printf("parity error register = %s\n", bits);
}
panic("memory error"); /* XXX */
}
static void
sync_status(const char *what, int ostatus, int nstatus)
{
char obuf[256], nbuf[256], tbuf[1024];
#if defined(USE_SNPRINTB) && defined (STA_FMT)
snprintb(obuf, sizeof(obuf), STA_FMT, ostatus);
snprintb(nbuf, sizeof(nbuf), STA_FMT, nstatus);
#else
snprintf(obuf, sizeof(obuf), "%04x", ostatus);
snprintf(nbuf, sizeof(nbuf), "%04x", nstatus);
#endif
snprintf(tbuf, sizeof(tbuf), "%s status: %s -> %s", what, obuf, nbuf);
report_event(EVNT_KERN, NULL, tbuf);
}
/*
* hardmemerr4m: called upon fatal memory error. Print a message and panic.
*/
static void
hardmemerr4m(unsigned type, u_int sfsr, u_int sfva, u_int afsr, u_int afva)
{
char bits[64];
printf("memory fault: type %d", type);
snprintb(bits, sizeof(bits), SFSR_BITS, sfsr);
printf("sfsr=%s sfva=0x%x\n", bits, sfva);
if (afsr != 0) {
snprintb(bits, sizeof(bits), AFSR_BITS, afsr);
printf("; afsr=%s afva=0x%x%x\n", bits,
(afsr & AFSR_AFA) >> AFSR_AFA_RSHIFT, afva);
}
/*
* Setup interrupt vector if one is provided and interrupts are know to
* work on that particular chip.
*/
int
tpm_tis12_irqinit(struct tpm_softc *sc, int irq, int idx)
{
uint32_t r;
if ((irq == -1) || (tpm_devs[idx].flags & TPM_DEV_NOINTS)) {
sc->sc_vector = -1;
return 0;
}
/* Ack and disable all interrupts. */
r = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE);
bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE,
r & ~TPM_GLOBAL_INT_ENABLE);
bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS,
bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS));
#ifdef TPM_DEBUG
char buf[128];
snprintb(buf, sizeof(buf), TPM_INTERRUPT_ENABLE_BITS, r);
aprint_debug_dev(sc->sc_dev, "%s: before ien %s\n", __func__, buf);
#endif
/* Program interrupt vector. */
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_INT_VECTOR, irq);
sc->sc_vector = irq;
/* Program interrupt type. */
r &= ~(TPM_INT_EDGE_RISING|TPM_INT_EDGE_FALLING|TPM_INT_LEVEL_HIGH|
TPM_INT_LEVEL_LOW);
r |= TPM_GLOBAL_INT_ENABLE|TPM_CMD_READY_INT|TPM_LOCALITY_CHANGE_INT|
TPM_STS_VALID_INT|TPM_DATA_AVAIL_INT;
if (sc->sc_capabilities & TPM_INTF_INT_EDGE_RISING)
r |= TPM_INT_EDGE_RISING;
else if (sc->sc_capabilities & TPM_INTF_INT_EDGE_FALLING)
r |= TPM_INT_EDGE_FALLING;
else if (sc->sc_capabilities & TPM_INTF_INT_LEVEL_HIGH)
r |= TPM_INT_LEVEL_HIGH;
else
r |= TPM_INT_LEVEL_LOW;
bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INTERRUPT_ENABLE, r);
#ifdef TPM_DEBUG
snprintb(buf, sizeof(buf), TPM_INTERRUPT_ENABLE_BITS, r);
aprint_debug_dev(sc->sc_dev, "%s: after ien %s\n", __func__, buf);
#endif
return 0;
}
/* Finish transaction. */
int
tpm_tis12_end(struct tpm_softc *sc, int flag, int err)
{
int rv = 0;
if (flag == UIO_READ) {
if ((rv = tpm_waitfor(sc, TPM_STS_VALID, TPM_READ_TMO,
sc->sc_read)))
return rv;
/* Still more data? */
sc->sc_stat = tpm_status(sc);
if (!err && ((sc->sc_stat & TPM_STS_DATA_AVAIL)
== TPM_STS_DATA_AVAIL)) {
#ifdef TPM_DEBUG
char buf[128];
snprintb(buf, sizeof(buf), TPM_STS_BITS, sc->sc_stat);
aprint_debug_dev(sc->sc_dev,
"%s: read failed stat=%s\n", __func__, buf);
#endif
rv = EIO;
}
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,
TPM_STS_CMD_READY);
/* Release our (0th) locality. */
bus_space_write_1(sc->sc_bt, sc->sc_bh,TPM_ACCESS,
TPM_ACCESS_ACTIVE_LOCALITY);
} else {
/* Hungry for more? */
sc->sc_stat = tpm_status(sc);
if (!err && (sc->sc_stat & TPM_STS_DATA_EXPECT)) {
#ifdef TPM_DEBUG
char buf[128];
snprintb(buf, sizeof(buf), TPM_STS_BITS, sc->sc_stat);
aprint_debug_dev(sc->sc_dev,
"%s: write failed stat=%s\n", __func__, buf);
#endif
rv = EIO;
}
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,
err ? TPM_STS_CMD_READY : TPM_STS_GO);
}
return rv;
}
/* Start transaction. */
int
tpm_legacy_start(struct tpm_softc *sc, int flag)
{
struct timeval tv;
uint8_t bits, r;
int to, rv;
bits = flag == UIO_READ ? TPM_LEGACY_DA : 0;
tv.tv_sec = TPM_LEGACY_TMO;
tv.tv_usec = 0;
to = tvtohz(&tv) / TPM_LEGACY_SLEEP;
while (((r = bus_space_read_1(sc->sc_batm, sc->sc_bahm, 1)) &
(TPM_LEGACY_BUSY|bits)) != bits && to--) {
rv = tsleep(sc, PRIBIO | PCATCH, "legacy_tpm_start",
TPM_LEGACY_SLEEP);
if (rv && rv != EWOULDBLOCK)
return rv;
}
#if defined(TPM_DEBUG) && !defined(__FreeBSD__)
char buf[128];
snprintb(buf, sizeof(buf), TPM_LEGACY_BITS, r);
aprint_debug_dev(sc->sc_dev, "%s: bits %s\n", device_xname(sc->sc_dev),
buf);
#endif
if ((r & (TPM_LEGACY_BUSY|bits)) != bits)
return EIO;
return 0;
}
/*
* Stray interrupt handler. Clear it if possible.
* If not, and if we get 10 interrupts in 10 seconds, panic.
* XXXSMP: We are holding the kernel lock at entry & exit.
*/
void
strayintr(struct clockframe *fp)
{
static int straytime, nstray;
char bits[64];
int timesince;
#if defined(MULTIPROCESSOR)
/*
* XXX
*
* Don't whine about zs interrupts on MP. We sometimes get
* stray interrupts when polled kernel output on cpu>0 eats
* the interrupt and cpu0 sees it.
*/
#define ZS_INTR_IPL 12
if (fp->ipl == ZS_INTR_IPL)
return;
#endif
snprintb(bits, sizeof(bits), PSR_BITS, fp->psr);
printf("stray interrupt cpu%d ipl 0x%x pc=0x%x npc=0x%x psr=%s\n",
cpu_number(), fp->ipl, fp->pc, fp->npc, bits);
timesince = time_uptime - straytime;
if (timesince <= 10) {
if (++nstray > 10)
panic("crazy interrupts");
} else {
straytime = time_uptime;
nstray = 1;
}
}
/*
* intr handler
*/
int
wb_sdmmc_intr(struct wb_softc *wb)
{
uint8_t val;
val = wb_read(wb, WB_SD_INTSTS);
if (val == 0xff || val == 0x00)
return 0;
if (wb->wb_sdmmc_dev == NULL)
return 1;
wb->wb_sdmmc_intsts |= val;
if (wb_sdmmc_debug) {
char buf[64];
snprintb(buf, sizeof(buf),
"\20\1TC\2BUSYEND\3PROGEND\4TIMEOUT"
"\5CRC\6FIFO\7CARD\010PENDING",
val);
REPORT(wb, "WB_SD_INTSTS = %s\n", buf);
}
if (val & WB_INT_CARD)
callout_schedule(&wb->wb_sdmmc_callout, hz / 4);
return 1;
}
/* Probe TPM using TIS 1.2 interface. */
int
tpm_tis12_probe(bus_space_tag_t bt, bus_space_handle_t bh)
{
uint32_t r;
uint8_t save, reg;
r = bus_space_read_4(bt, bh, TPM_INTF_CAPABILITIES);
if (r == 0xffffffff)
return 0;
#ifdef TPM_DEBUG
char buf[128];
snprintb(buf, sizeof(buf), TPM_CAPBITS, r);
printf("%s: caps=%s\n", __func__, buf);
#endif
if ((r & TPM_CAPSREQ) != TPM_CAPSREQ ||
!(r & (TPM_INTF_INT_EDGE_RISING | TPM_INTF_INT_LEVEL_LOW))) {
#ifdef TPM_DEBUG
printf("%s: caps too low (caps=%s)\n", __func__, buf);
#endif
return 0;
}
save = bus_space_read_1(bt, bh, TPM_ACCESS);
bus_space_write_1(bt, bh, TPM_ACCESS, TPM_ACCESS_REQUEST_USE);
reg = bus_space_read_1(bt, bh, TPM_ACCESS);
if ((reg & TPM_ACCESS_VALID) && (reg & TPM_ACCESS_ACTIVE_LOCALITY) &&
bus_space_read_4(bt, bh, TPM_ID) != 0xffffffff)
return 1;
bus_space_write_1(bt, bh, TPM_ACCESS, save);
return 0;
}
/* Setup TPM using TIS 1.2 interface. */
int
tpm_tis12_init(struct tpm_softc *sc, int irq, const char *name)
{
uint32_t r;
int i;
r = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INTF_CAPABILITIES);
#ifdef TPM_DEBUG
char cbuf[128];
snprintb(cbuf, sizeof(cbuf), TPM_CAPBITS, r);
aprint_debug_dev(sc->sc_dev, "%s: caps=%s ", __func__, cbuf);
#endif
if ((r & TPM_CAPSREQ) != TPM_CAPSREQ ||
!(r & (TPM_INTF_INT_EDGE_RISING | TPM_INTF_INT_LEVEL_LOW))) {
char buf[128];
snprintb(buf, sizeof(buf), TPM_CAPBITS, r);
aprint_error_dev(sc->sc_dev, "capabilities too low (caps=%s)\n",
buf);
return 1;
}
sc->sc_capabilities = r;
sc->sc_devid = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_ID);
sc->sc_rev = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_REV);
for (i = 0; tpm_devs[i].devid; i++)
if (tpm_devs[i].devid == sc->sc_devid)
break;
if (tpm_devs[i].devid)
aprint_normal(": %s rev 0x%x\n",
tpm_devs[i].name, sc->sc_rev);
else
aprint_normal(": device 0x%08x rev 0x%x\n",
sc->sc_devid, sc->sc_rev);
if (tpm_tis12_irqinit(sc, irq, i))
return 1;
if (tpm_request_locality(sc, 0))
return 1;
/* Abort whatever it thought it was doing. */
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);
return 0;
}
static int
ext2fs_checksb(struct ext2fs *fs, int ronly)
{
uint32_t u32;
if (fs2h16(fs->e2fs_magic) != E2FS_MAGIC) {
return (EINVAL); /* XXX needs translation */
}
if (fs2h32(fs->e2fs_rev) > E2FS_REV1) {
#ifdef DIAGNOSTIC
printf("ext2fs: unsupported revision number: %x\n",
fs2h32(fs->e2fs_rev));
#endif
return (EINVAL); /* XXX needs translation */
}
if (fs2h32(fs->e2fs_log_bsize) > 2) { /* block size = 1024|2048|4096 */
#ifdef DIAGNOSTIC
printf("ext2fs: bad block size: %d "
"(expected <= 2 for ext2 fs)\n",
fs2h32(fs->e2fs_log_bsize));
#endif
return (EINVAL); /* XXX needs translation */
}
if (fs2h32(fs->e2fs_rev) > E2FS_REV0) {
char buf[256];
if (fs2h32(fs->e2fs_first_ino) != EXT2_FIRSTINO) {
printf("ext2fs: unsupported first inode position\n");
return (EINVAL); /* XXX needs translation */
}
u32 = fs2h32(fs->e2fs_features_incompat) & ~EXT2F_INCOMPAT_SUPP;
if (u32) {
snprintb(buf, sizeof(buf), EXT2F_INCOMPAT_BITS, u32);
printf("ext2fs: unsupported incompat features: %s\n",
buf);
return EINVAL; /* XXX needs translation */
}
u32 = fs2h32(fs->e2fs_features_rocompat) & ~EXT2F_ROCOMPAT_SUPP;
if (!ronly && u32) {
snprintb(buf, sizeof(buf), EXT2F_ROCOMPAT_BITS, u32);
printf("ext2fs: unsupported ro-incompat features: %s\n",
buf);
return EROFS; /* XXX needs translation */
}
}
return (0);
}
static void
lpt_attach(device_t parent, device_t self, void *aux)
{
struct lpt_softc * sc = device_private(self);
struct ppbus_device_softc * ppbdev = &(sc->ppbus_dev);
struct ppbus_attach_args * args = aux;
char buf[64];
int error;
ppbdev->sc_dev = self;
error = lpt_request_ppbus(sc, 0);
if(error) {
printf("%s(%s): error (%d) requesting bus(%s). Device not "
"properly attached.\n", __func__, device_xname(self),
error, device_xname(parent));
return;
}
/* Record capabilities */
ppbdev->capabilities = args->capabilities;
/* Allocate memory buffers */
if(ppbdev->capabilities & PPBUS_HAS_DMA) {
if(ppbus_dma_malloc(parent, &(sc->sc_inbuf),
&(sc->sc_in_baddr), BUFSIZE)) {
printf(" : cannot allocate input DMA buffer. Device "
"not properly attached!\n");
return;
}
if(ppbus_dma_malloc(parent, &(sc->sc_outbuf),
&(sc->sc_out_baddr), BUFSIZE)) {
ppbus_dma_free(parent, &(sc->sc_inbuf),
&(sc->sc_in_baddr), BUFSIZE);
printf(" : cannot allocate output DMA buffer. Device "
"not properly attached!\n");
return;
}
} else {
sc->sc_inbuf = malloc(BUFSIZE, M_DEVBUF, M_WAITOK);
sc->sc_outbuf = malloc(BUFSIZE, M_DEVBUF, M_WAITOK);
}
/* Print out mode */
ppbdev->ctx.mode = ppbus_get_mode(parent);
snprintb(buf, sizeof(buf),
"\20\1COMPATIBLE\2NIBBLE\3PS2\4EPP\5ECP\6FAST_CENTR",
ppbdev->ctx.mode);
printf(": port mode = %s\n", buf);
/* Initialize the device on open by default */
sc->sc_flags = LPT_PRIME;
lpt_release_ppbus(sc, 0);
}
void
apic_format_redir(const char *where1, const char *where2, int idx,
uint32_t redirhi, uint32_t redirlo)
{
char buf[256];
snprintb(buf, sizeof(buf), redirlofmt, redirlo);
printf("%s: %s%d %s",
where1, where2, idx, buf);
if ((redirlo & LAPIC_DEST_MASK) == 0) {
snprintb(buf, sizeof(buf), redirhifmt, redirhi);
printf(" %s", buf);
}
printf("\n");
}
/*
* Print general debugging info
*/
static void
print_debug (struct msgs *mp)
{
char buf[100];
printf ("invo_name = %s\n", invo_name);
printf ("mypath = %s\n", mypath);
printf ("defpath = %s\n", defpath);
printf ("ctxpath = %s\n", ctxpath);
printf ("context flags = %s\n", snprintb (buf, sizeof(buf),
(unsigned) ctxflags, DBITS));
printf ("foldpath = %s\n", mp->foldpath);
printf ("folder flags = %s\n\n", snprintb(buf, sizeof(buf),
(unsigned) mp->msgflags, FBITS));
printf ("lowmsg=%d hghmsg=%d nummsg=%d curmsg=%d\n",
mp->lowmsg, mp->hghmsg, mp->nummsg, mp->curmsg);
printf ("lowsel=%d hghsel=%d numsel=%d\n",
mp->lowsel, mp->hghsel, mp->numsel);
printf ("lowoff=%d hghoff=%d\n\n", mp->lowoff, mp->hghoff);
}
static int
ichsmb_intr(void *arg)
{
struct ichsmb_softc *sc = arg;
uint8_t st;
uint8_t *b;
size_t len;
#ifdef ICHIIC_DEBUG
char fbuf[64];
#endif
/* Read status */
st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS);
if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR |
LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED |
LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0)
/* Interrupt was not for us */
return (0);
#ifdef ICHIIC_DEBUG
snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st);
printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf);
#endif
/* Clear status bits */
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st);
/* Check for errors */
if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) {
sc->sc_i2c_xfer.error = 1;
goto done;
}
if (st & LPCIB_SMB_HS_INTR) {
if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op))
goto done;
/* Read data */
b = sc->sc_i2c_xfer.buf;
len = sc->sc_i2c_xfer.len;
if (len > 0)
b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
LPCIB_SMB_HD0);
if (len > 1)
b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
LPCIB_SMB_HD1);
}
done:
if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0)
wakeup(sc);
return (1);
}
static void
omap3_scm_attach(device_t parent, device_t self, void *opaque)
{
struct omap3_scm_softc *sc = device_private(self);
struct obio_attach_args *obio = opaque;
uint32_t rev;
char buf[256];
const char *cid;
aprint_naive("\n");
KASSERT(obio->obio_size == SCM_SIZE);
sc->sc_dev = self;
sc->sc_iot = obio->obio_iot;
if (bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size,
0, &sc->sc_ioh) != 0) {
aprint_error(": couldn't map address space\n");
return;
}
rev = SCM_READ_REG(sc, CONTROL_REVISION);
aprint_normal(": rev. 0x%x\n", rev & 0xff);
sc->sc_cid = SCM_READ_REG(sc, CONTROL_OMAP_STATUS & 0xffff);
switch (sc->sc_cid) {
case CHIPID_OMAP3503: cid = "OMAP3503"; break;
case CHIPID_OMAP3515: cid = "OMAP3515"; break;
case CHIPID_OMAP3525: cid = "OMAP3525"; break;
case CHIPID_OMAP3530: cid = "OMAP3530"; break;
default: cid = "unknwon"; break;
}
aprint_normal_dev(self, "%s: ", cid);
snprintb(buf, sizeof(buf), "\177\020"
"b\0TO_OUT\0"
"b\1four_bit_mmc\0"
"b\2CCP2_CSI1\0"
"b\3CMADS_FL3G\0"
"b\4NEON_VFPLite\0"
"b\5ISP_disable\0"
"f\6\2IVA2_MHz\0=\0 430\0=\2 266\0"
"f\10\2ARM_MHz\0=\0 600\0=\1 400\0=\2 266\0"
"f\12\2MPU_L2_cache_size\0=\0 0KB\0=\1 64KB\0=\2 128KB\0=\3 Full\0"
"b\14IVA_disable_acc\0"
"f\15\2SGX_scalable_control\0=\0Full\0=\1Half\0=\2not-present\0\0",
sc->sc_cid);
aprint_normal("%s\n", buf);
omap3_scm_sensor_attach(sc);
}
static int
sparc_vme_error(void)
{
struct sparcvme_softc *sc = sparcvme_sc;
uint32_t afsr, afpa;
char bits[64];
afsr = sc->sc_reg->vmebus_afsr;
afpa = sc->sc_reg->vmebus_afar;
snprintb(bits, sizeof(bits), VMEBUS_AFSR_BITS, afsr);
printf("VME error:\n\tAFSR %s\n", bits);
printf("\taddress: 0x%x%x\n", afsr, afpa);
return (0);
}
/* Start transaction. */
int
tpm_tis12_start(struct tpm_softc *sc, int flag)
{
int rv;
if (flag == UIO_READ) {
rv = tpm_waitfor(sc, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
TPM_READ_TMO, sc->sc_read);
return rv;
}
/* Own our (0th) locality. */
if ((rv = tpm_request_locality(sc, 0)) != 0)
return rv;
sc->sc_stat = tpm_status(sc);
if (sc->sc_stat & TPM_STS_CMD_READY) {
#ifdef TPM_DEBUG
char buf[128];
snprintb(buf, sizeof(buf), TPM_STS_BITS, sc->sc_stat);
aprint_debug_dev(sc->sc_dev, "%s: UIO_WRITE status %s\n",
__func__, buf);
#endif
return 0;
}
#ifdef TPM_DEBUG
aprint_debug_dev(sc->sc_dev,
"%s: UIO_WRITE readying chip\n", __func__);
#endif
/* Abort previous and restart. */
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);
if ((rv = tpm_waitfor(sc, TPM_STS_CMD_READY, TPM_READY_TMO,
sc->sc_write))) {
#ifdef TPM_DEBUG
aprint_debug_dev(sc->sc_dev,
"%s: UIO_WRITE readying failed %d\n", __func__, rv);
#endif
return rv;
}
#ifdef TPM_DEBUG
aprint_debug_dev(sc->sc_dev,
"%s: UIO_WRITE readying done\n", __func__);
#endif
return 0;
}
int
ilwait(struct il_softc *sc, char *op)
{
while ((IL_RCSR(IL_CSR)&IL_CDONE) == 0)
;
if (IL_RCSR(IL_CSR)&IL_STATUS) {
char bits[64];
snprintb(bits, sizeof(bits), IL_BITS, IL_RCSR(IL_CSR));
aprint_error_dev(sc->sc_dev, "%s failed, csr=%s\n", op, bits);
return (-1);
}
return (0);
}
/*
* Print debugging info about all the SELECTED
* messages and the sequences they are in.
* Due limitattions of snprintb(), only a limited
* number of sequences will be printed. See the
* comments in sbr/seq_bits.c.
*/
static void
seq_printdebug (struct msgs *mp)
{
int msgnum;
char buf[BUFSIZ];
printf ("\n");
for (msgnum = mp->lowsel; msgnum <= mp->hghsel; msgnum++) {
if (is_selected (mp, msgnum))
printf ("%*d: %s\n", DMAXFOLDER, msgnum,
snprintb (buf, sizeof buf,
(unsigned) *bvector_bits (msgstat (mp, msgnum)),
seq_bits (mp)));
}
}
int
mount_procfs(int argc, char *argv[])
{
int ch, mntflags, altflags;
struct procfs_args args;
char canon_dir[MAXPATHLEN];
mntoptparse_t mp;
mntflags = 0;
altflags = PROCFSMNT_LINUXCOMPAT;
while ((ch = getopt(argc, argv, "o:")) != -1)
switch (ch) {
case 'o':
mp = getmntopts(optarg, mopts, &mntflags, &altflags);
if (mp == NULL)
err(1, "getmntopts");
freemntopts(mp);
break;
case '?':
default:
usage();
}
argc -= optind;
argv += optind;
if (argc != 2)
usage();
if (realpath(argv[1], canon_dir) == NULL) /* Check mounton path */
err(1, "realpath %s", argv[1]);
if (strncmp(argv[1], canon_dir, MAXPATHLEN)) {
warnx("\"%s\" is a relative path.", argv[1]);
warnx("using \"%s\" instead.", canon_dir);
}
args.version = PROCFS_ARGSVERSION;
args.flags = altflags;
if (mount(MOUNT_PROCFS, canon_dir, mntflags, &args, sizeof args) == -1)
err(1, "procfs on %s", canon_dir);
if (mntflags & MNT_GETARGS) {
char buf[1024];
(void)snprintb(buf, sizeof(buf), PROCFSMNT_BITS, args.flags);
printf("version=%d, flags=%s\n", args.version, buf);
}
exit(0);
}
int
pciprint(void *aux, const char *pnp)
{
struct pci_attach_args *pa = aux;
char devinfo[256];
const struct pci_quirkdata *qd;
if (pnp) {
pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo));
aprint_normal("%s at %s", devinfo, pnp);
}
aprint_normal(" dev %d function %d", pa->pa_device, pa->pa_function);
if (pci_config_dump) {
printf(": ");
pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
if (!pnp)
pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo));
printf("%s at %s", devinfo, pnp ? pnp : "?");
printf(" dev %d function %d (", pa->pa_device, pa->pa_function);
#ifdef __i386__
printf("tag %#lx, intrtag %#lx, intrswiz %#lx, intrpin %#lx",
*(long *)&pa->pa_tag, *(long *)&pa->pa_intrtag,
(long)pa->pa_intrswiz, (long)pa->pa_intrpin);
#else
printf("intrswiz %#lx, intrpin %#lx",
(long)pa->pa_intrswiz, (long)pa->pa_intrpin);
#endif
printf(", i/o %s, mem %s,",
pa->pa_flags & PCI_FLAGS_IO_OKAY ? "on" : "off",
pa->pa_flags & PCI_FLAGS_MEM_OKAY ? "on" : "off");
qd = pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
PCI_PRODUCT(pa->pa_id));
if (qd == NULL) {
printf(" no quirks");
} else {
snprintb(devinfo, sizeof (devinfo),
"\002\001multifn\002singlefn\003skipfunc0"
"\004skipfunc1\005skipfunc2\006skipfunc3"
"\007skipfunc4\010skipfunc5\011skipfunc6"
"\012skipfunc7", qd->quirks);
printf(" quirks %s", devinfo);
}
printf(")");
}
return UNCONF;
}
/*
* Bogus interrupt for which neither hard nor soft interrupt bit in
* the IPR was set.
*/
void
bogusintr(struct clockframe *fp)
{
char bits[64];
#if defined(MULTIPROCESSOR)
/*
* XXX as above.
*/
if (fp->ipl == ZS_INTR_IPL)
return;
#endif
snprintb(bits, sizeof(bits), PSR_BITS, fp->psr);
printf("cpu%d: bogus interrupt ipl 0x%x pc=0x%x npc=0x%x psr=%s\n",
cpu_number(), fp->ipl, fp->pc, fp->npc, bits);
}
int
tpm_request_locality(struct tpm_softc *sc, int l)
{
uint32_t r;
int to, rv;
if (l != 0)
return EINVAL;
if ((bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS) &
(TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) ==
(TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY))
return 0;
bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS,
TPM_ACCESS_REQUEST_USE);
to = tpm_tmotohz(TPM_ACCESS_TMO);
while ((r = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_ACCESS) &
(TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) !=
(TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY) && to--) {
rv = tsleep(sc->sc_init, PRIBIO | PCATCH, "tpm_locality", 1);
if (rv && rv != EWOULDBLOCK) {
#ifdef TPM_DEBUG
aprint_debug_dev(sc->sc_dev, "%s: interrupted %d\n",
__func__, rv);
#endif
return rv;
}
}
if ((r & (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) !=
(TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) {
#ifdef TPM_DEBUG
char buf[128];
snprintb(buf, sizeof(buf), TPM_ACCESS_BITS, r);
aprint_debug_dev(sc->sc_dev, "%s: access %s\n", __func__, buf);
#endif
return EBUSY;
}
return 0;
}
int
tpm_intr(void *v)
{
struct tpm_softc *sc = v;
uint32_t r;
#ifdef TPM_DEBUG
static int cnt = 0;
#endif
r = bus_space_read_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS);
#ifdef TPM_DEBUG
if (r != 0) {
char buf[128];
snprintb(buf, sizeof(buf), TPM_INTERRUPT_ENABLE_BITS, r);
aprint_debug_dev(sc->sc_dev, "%s: int=%s (%d)\n", __func__,
buf, cnt);
} else
cnt++;
#endif
if (!(r & (TPM_CMD_READY_INT | TPM_LOCALITY_CHANGE_INT |
TPM_STS_VALID_INT | TPM_DATA_AVAIL_INT)))
#ifdef __FreeBSD__
return;
#else
return 0;
#endif
if (r & TPM_STS_VALID_INT)
wakeup(sc);
if (r & TPM_CMD_READY_INT)
wakeup(sc->sc_write);
if (r & TPM_DATA_AVAIL_INT)
wakeup(sc->sc_read);
if (r & TPM_LOCALITY_CHANGE_INT)
wakeup(sc->sc_init);
bus_space_write_4(sc->sc_bt, sc->sc_bh, TPM_INT_STATUS, r);
return 1;
}
void
db_dump_pcb(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
{
struct pcb *pcb;
char bits[64];
int i;
if (have_addr)
pcb = (struct pcb *) addr;
else
pcb = curcpu()->curpcb;
snprintb(bits, sizeof(bits), PSR_BITS, pcb->pcb_psr);
db_printf("pcb@%p sp:%p pc:%p psr:%s onfault:%p\nfull windows:\n",
pcb, (void *)(long)pcb->pcb_sp, (void *)(long)pcb->pcb_pc,
bits, (void *)pcb->pcb_onfault);
for (i=0; i<pcb->pcb_nsaved; i++) {
db_printf("win %d: at %llx local, in\n", i,
(unsigned long long)pcb->pcb_rw[i+1].rw_in[6]);
db_printf("%16llx %16llx %16llx %16llx\n",
(unsigned long long)pcb->pcb_rw[i].rw_local[0],
(unsigned long long)pcb->pcb_rw[i].rw_local[1],
(unsigned long long)pcb->pcb_rw[i].rw_local[2],
(unsigned long long)pcb->pcb_rw[i].rw_local[3]);
db_printf("%16llx %16llx %16llx %16llx\n",
(unsigned long long)pcb->pcb_rw[i].rw_local[4],
(unsigned long long)pcb->pcb_rw[i].rw_local[5],
(unsigned long long)pcb->pcb_rw[i].rw_local[6],
(unsigned long long)pcb->pcb_rw[i].rw_local[7]);
db_printf("%16llx %16llx %16llx %16llx\n",
(unsigned long long)pcb->pcb_rw[i].rw_in[0],
(unsigned long long)pcb->pcb_rw[i].rw_in[1],
(unsigned long long)pcb->pcb_rw[i].rw_in[2],
(unsigned long long)pcb->pcb_rw[i].rw_in[3]);
db_printf("%16llx %16llx %16llx %16llx\n",
(unsigned long long)pcb->pcb_rw[i].rw_in[4],
(unsigned long long)pcb->pcb_rw[i].rw_in[5],
(unsigned long long)pcb->pcb_rw[i].rw_in[6],
(unsigned long long)pcb->pcb_rw[i].rw_in[7]);
}
}
int
mount_cd9660(int argc, char **argv)
{
struct iso_args args;
char canon_dev[MAXPATHLEN], canon_dir[MAXPATHLEN];
int mntflags;
mount_cd9660_parseargs(argc, argv, &args, &mntflags,
canon_dev, canon_dir);
if (mount(MOUNT_CD9660, canon_dir, mntflags, &args, sizeof args) == -1)
err(1, "%s on %s", canon_dev, canon_dir);
if (mntflags & MNT_GETARGS) {
char buf[2048];
(void)snprintb(buf, sizeof(buf), ISOFSMNT_BITS, args.flags);
printf("%s\n", buf);
}
exit(0);
}
int
mount_ntfs(int argc, char *argv[])
{
struct ntfs_args args;
int mntflags;
char canon_dev[MAXPATHLEN], canon_dir[MAXPATHLEN];
mount_ntfs_parseargs(argc, argv, &args, &mntflags,
canon_dev, canon_dir);
if (mount(MOUNT_NTFS, canon_dir, mntflags, &args, sizeof args) == -1)
err(EX_OSERR, "%s on %s", canon_dev, canon_dir);
if (mntflags & MNT_GETARGS) {
char buf[1024];
(void)snprintb(buf, sizeof(buf), NTFS_MFLAG_BITS, args.flag);
printf("uid=%d, gid=%d, mode=0%o, flags=%s\n", args.uid,
args.gid, args.mode, buf);
}
exit (0);
}
void
nmi_hard(void)
{
/*
* A level 15 hard interrupt.
*/
int fatal = 0;
uint32_t si;
char bits[64];
u_int afsr, afva;
/* Tally */
cpuinfo.ci_intrcnt[15].ev_count++;
cpuinfo.ci_data.cpu_nintr++;
afsr = afva = 0;
if ((*cpuinfo.get_asyncflt)(&afsr, &afva) == 0) {
snprintb(bits, sizeof(bits), AFSR_BITS, afsr);
printf("Async registers (mid %d): afsr=%s; afva=0x%x%x\n",
cpuinfo.mid, bits,
(afsr & AFSR_AFA) >> AFSR_AFA_RSHIFT, afva);
}
void
pcic_power(int why, void *arg)
{
struct pcic_handle *h = arg;
struct pcic_softc *sc = device_private(h->ph_parent);
int reg;
DPRINTF(("%s: power: why %d\n", device_xname(h->ph_parent), why));
if (h->flags & PCIC_FLAG_SOCKETP) {
if ((why == PWR_RESUME) &&
(pcic_read(h, PCIC_CSC_INTR) == 0)) {
#ifdef PCICDEBUG
char bitbuf[64];
#endif
reg = PCIC_CSC_INTR_CD_ENABLE;
if (sc->irq != -1)
reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT;
pcic_write(h, PCIC_CSC_INTR, reg);
#ifdef PCICDEBUG
snprintb(bitbuf, sizeof(bitbuf), PCIC_CSC_INTR_FORMAT,
pcic_read(h, PCIC_CSC_INTR));
#endif
DPRINTF(("%s: CSC_INTR was zero; reset to %s\n",
device_xname(sc->dev), bitbuf));
}
/*
* check for card insertion or removal during suspend period.
* XXX: the code can't cope with card swap (remove then insert).
* how can we detect such situation?
*/
if (why == PWR_RESUME)
(void)pcic_intr_socket(h);
}
}