/**
* Flush the tile cache: write all dirty tiles back to the transfer.
* any tiles "flagged" as cleared will be "really" cleared.
*/
void
sp_flush_tile_cache(struct softpipe_tile_cache *tc)
{
struct pipe_transfer *pt = tc->transfer;
int inuse = 0, pos;
if (pt) {
/* caching a drawing transfer */
for (pos = 0; pos < NUM_ENTRIES; pos++) {
struct softpipe_cached_tile *tile = tc->entries[pos];
if (!tile)
{
assert(tc->tile_addrs[pos].bits.invalid);
continue;
}
sp_flush_tile(tc, pos);
++inuse;
}
sp_tile_cache_flush_clear(tc);
tc->last_tile_addr.bits.invalid = 1;
}
#if 0
debug_printf("flushed tiles in use: %d\n", inuse);
#endif
}
/**
* Flush the tile cache: write all dirty tiles back to the transfer.
* any tiles "flagged" as cleared will be "really" cleared.
*/
void
sp_flush_tile_cache(struct softpipe_tile_cache *tc)
{
struct pipe_transfer *pt = tc->transfer;
int inuse = 0, pos;
if (pt) {
/* caching a drawing transfer */
for (pos = 0; pos < NUM_ENTRIES; pos++) {
struct softpipe_cached_tile *tile = tc->entries + pos;
if (!tile->addr.bits.invalid) {
if (tc->depth_stencil) {
pipe_put_tile_raw(tc->pipe, pt,
tile->addr.bits.x * TILE_SIZE,
tile->addr.bits.y * TILE_SIZE,
TILE_SIZE, TILE_SIZE,
tile->data.depth32, 0/*STRIDE*/);
}
else {
pipe_put_tile_rgba(tc->pipe, pt,
tile->addr.bits.x * TILE_SIZE,
tile->addr.bits.y * TILE_SIZE,
TILE_SIZE, TILE_SIZE,
(float *) tile->data.color);
}
tile->addr.bits.invalid = 1; /* mark as empty */
inuse++;
}
}
sp_tile_cache_flush_clear(tc);
}
#if 0
debug_printf("flushed tiles in use: %d\n", inuse);
#endif
}
