static void prepare_for_transfer(struct device *dev)
{
struct spi_nrfx_data *dev_data = get_dev_data(dev);
const struct spi_nrfx_config *dev_config = get_dev_config(dev);
struct spi_context *ctx = &dev_data->ctx;
int status;
size_t buf_len = spi_context_longest_current_buf(ctx);
if (buf_len > 0) {
nrfx_err_t result;
if (buf_len > dev_config->max_buf_len) {
buf_len = dev_config->max_buf_len;
}
result = nrfx_spis_buffers_set(
&dev_config->spis,
ctx->tx_buf,
spi_context_tx_buf_on(ctx) ? buf_len : 0,
ctx->rx_buf,
spi_context_rx_buf_on(ctx) ? buf_len : 0);
if (result == NRFX_SUCCESS) {
return;
}
/* Cannot prepare for transfer. */
status = -EIO;
} else {
/* Zero-length buffer provided. */
status = 0;
}
spi_context_complete(ctx, status);
}
static void push_data(struct device *dev)
{
const struct spi_dw_config *info = dev->config->config_info;
struct spi_dw_data *spi = dev->driver_data;
u32_t data = 0U;
u32_t f_tx;
DBG_COUNTER_INIT();
if (spi_context_rx_on(&spi->ctx)) {
f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs) -
read_rxflr(info->regs);
if ((int)f_tx < 0) {
f_tx = 0U; /* if rx-fifo is full, hold off tx */
}
} else {
f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs);
}
while (f_tx) {
if (spi_context_tx_buf_on(&spi->ctx)) {
switch (spi->dfs) {
case 1:
data = UNALIGNED_GET((u8_t *)
(spi->ctx.tx_buf));
break;
case 2:
data = UNALIGNED_GET((u16_t *)
(spi->ctx.tx_buf));
break;
#ifndef CONFIG_ARC
case 4:
data = UNALIGNED_GET((u32_t *)
(spi->ctx.tx_buf));
break;
#endif
}
} else if (spi_context_rx_on(&spi->ctx)) {
/* No need to push more than necessary */
if ((int)(spi->ctx.rx_len - spi->fifo_diff) <= 0) {
break;
}
data = 0U;
} else if (spi_context_tx_on(&spi->ctx)) {
data = 0U;
} else {
/* Nothing to push anymore */
break;
}
write_dr(data, info->regs);
spi_context_update_tx(&spi->ctx, spi->dfs, 1);
spi->fifo_diff++;
f_tx--;
DBG_COUNTER_INC();
}
if (!spi_context_tx_on(&spi->ctx)) {
/* prevents any further interrupts demanding TX fifo fill */
write_txftlr(0, info->regs);
}
LOG_DBG("Pushed: %d", DBG_COUNTER_RESULT());
}
