/*--------------------------------------------------------------------------*/ static void spi_setup(void) { /* Configure GPIOs: SS=PB12, SCK=PB13, MISO=PB14 and MOSI=PB15 * For now ignore the SS pin so we can use it to time the ISRs */ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, /* GPIO4 | */ GPIO13 | GPIO15 ); gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); /* Reset SPI, SPI_CR1 register cleared, SPI is disabled */ spi_reset(SPI2); /* Explicitly disable I2S in favour of SPI operation */ SPI2_I2SCFGR = 0; /* Set up SPI in Master mode with: * Clock baud rate: 1/64 of peripheral clock frequency * Clock polarity: Idle High * Clock phase: Data valid on 2nd clock pulse * Data frame format: 8-bit or 16-bit * Frame format: MSB First */ #if USE_16BIT_TRANSFERS spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_16BIT, SPI_CR1_MSBFIRST); #else spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); #endif /* * Set NSS management to software. * * Note: * Setting nss high is very important, even if we are controlling the GPIO * ourselves this bit needs to be at least set to 1, otherwise the spi * peripheral will not send any data out. */ spi_enable_software_slave_management(SPI2); spi_set_nss_high(SPI2); /* Enable SPI2 periph. */ spi_enable(SPI2); }
/* * SPI1 remapped: * SCK - PB3 * MISO - PB4 * MOSI - PB5 */ void SPI1_init(){ // enable AFIO & other clocking rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN); // remap SPI1 (change pins from PA5..7 to PB3..5); also turn off JTAG gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF, AFIO_MAPR_SPI1_REMAP); // SCK, MOSI - push-pull output gpio_set_mode(GPIO_BANK_SPI1_RE_SCK, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_SCK); gpio_set_mode(GPIO_BANK_SPI1_RE_MOSI, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_MOSI); // MISO - opendrain in gpio_set_mode(GPIO_BANK_SPI1_RE_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI1_RE_MISO); spi_reset(SPI1); /* Set up SPI in Master mode with: * Clock baud rate: 1/128 of peripheral clock frequency (APB2, 72MHz) * Clock polarity: CPOL=0, CPHA=0 * Data frame format: 8-bit * Frame format: MSB First */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); nvic_enable_irq(NVIC_SPI1_IRQ); // enable SPI interrupt spi_enable(Current_SPI); }
// setup screen and pad void interface_setup() { // SPI gpio_mode_setup(INTERFACE_SPI_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, INTERFACE_SPI_CLK_PIN | INTERFACE_SPI_MISO_PIN | INTERFACE_SPI_MOSI_PIN ); gpio_set_af(INTERFACE_SPI_PORT, GPIO_AF5, INTERFACE_SPI_CLK_PIN | INTERFACE_SPI_MISO_PIN | INTERFACE_SPI_MOSI_PIN); gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1); gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4 | GPIO5); rcc_periph_clock_enable(RCC_SPI1); spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI1); spi_enable(SPI1); // OLED ssd1306_setup(); // PAD pad_setup(); nvic_set_priority(NVIC_EXTI0_IRQ,0x00); /* Enable EXTI0 interrupt. */ nvic_enable_irq(NVIC_EXTI0_IRQ); gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO0); /* Configure the EXTI subsystem. */ exti_select_source(EXTI0, GPIOA); exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); exti_enable_request(EXTI0); }
static int _init(netdev2_t *encdev) { encx24j600_t *dev = (encx24j600_t *) encdev; DEBUG("encx24j600: starting initialization...\n"); /* setup IO */ gpio_init(dev->cs, GPIO_OUT); gpio_set(dev->cs); gpio_init_int(dev->int_pin, GPIO_IN_PU, GPIO_FALLING, encx24j600_isr, (void*)dev); if (spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, ENCX24J600_SPI_SPEED) < 0) { return -1; } lock(dev); /* initialization procedure as described in data sheet (39935c.pdf) */ do { do { xtimer_usleep(ENCX24J600_INIT_DELAY); reg_set(dev, ENC_EUDAST, 0x1234); xtimer_usleep(ENCX24J600_INIT_DELAY); } while (reg_get(dev, ENC_EUDAST) != 0x1234); while (!(reg_get(dev, ENC_ESTAT) & ENC_CLKRDY)); /* issue System Reset */ cmd(dev, ENC_SETETHRST); /* make sure initialization finalizes */ xtimer_usleep(1000); } while (!(reg_get(dev, ENC_EUDAST) == 0x0000)); /* configure flow control */ phy_reg_set(dev, ENC_PHANA, 0x05E1); reg_set_bits(dev, ENC_ECON2, ENC_AUTOFC); /* setup receive buffer */ reg_set(dev, ENC_ERXST, RX_BUFFER_START); reg_set(dev, ENC_ERXTAIL, RX_BUFFER_END); dev->rx_next_ptr = RX_BUFFER_START; /* configure receive filter to receive multicast frames */ reg_set_bits(dev, ENC_ERXFCON, ENC_MCEN); /* setup interrupts */ reg_set_bits(dev, ENC_EIE, ENC_PKTIE | ENC_LINKIE); cmd(dev, ENC_ENABLERX); cmd(dev, ENC_SETEIE); DEBUG("encx24j600: initialization complete.\n"); unlock(dev); #ifdef MODULE_NETSTATS_L2 memset(&netdev->stats, 0, sizeof(netstats_t)); #endif return 0; }
/* * SPI2: * SCK - PB13 * MISO - PB14 * MOSI - PB15 */ void SPI2_init(){ // turn on clocking //rcc_periph_clock_enable(RCC_SPI2 | RCC_GPIOB); rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN); // SCK, MOSI - push-pull output gpio_set_mode(GPIO_BANK_SPI2_SCK, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI2_SCK); gpio_set_mode(GPIO_BANK_SPI2_MOSI, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI2_MOSI); // MISO - opendrain in gpio_set_mode(GPIO_BANK_SPI2_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI2_MISO); spi_reset(SPI2); /* Set up SPI in Master mode with: * Clock baud rate: 1/64 of peripheral clock frequency (APB1, 36MHz) * Clock polarity: Idle High * Clock phase: Data valid on 2nd clock pulse * Data frame format: 8-bit * Frame format: MSB First */ spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); // nvic_enable_irq(NVIC_SPI2_IRQ); // enable SPI interrupt spi_enable(Current_SPI); }
void radio_init() { rcc_periph_clock_enable(R_RCC_SPI); rcc_periph_clock_enable(R_RCC_GPIO); gpio_mode_setup(R_SPI_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, R_SPI_PINS); gpio_set_af(R_SPI_PORT, R_SPI_AFn, R_SPI_PINS); gpio_mode_setup(R_CS_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, R_CS_PIN); // Reset and enable the SPI periph spi_reset(R_SPI); spi_init_master(R_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_CRCL_8BIT, SPI_CR1_MSBFIRST); // Trigger an RXNE event when we have 8 bits (one byte) in the buffer spi_fifo_reception_threshold_8bit(R_SPI); // NSS must be set high for the peripheral to function spi_enable_software_slave_management(R_SPI); spi_set_nss_high(R_SPI); gpio_set(R_CS_PORT, R_CS_PIN); // Enable spi_enable(R_SPI); radio_sleep(); }
int cmd_init_master(int argc, char **argv) { int res; spi_master = -1; if (parse_spi_dev(argc, argv) < 0) { return 1; } spi_acquire(spi_dev); res = spi_init_master(spi_dev, spi_mode, spi_speed); spi_release(spi_dev); if (res < 0) { printf("spi_init_master: error initializing SPI_%i device (code %i)\n", spi_dev, res); return 1; } res = gpio_init(spi_cs, GPIO_OUT); if (res < 0){ printf("gpio_init: error initializing GPIO_%ld as CS line (code %i)\n", (long)spi_cs, res); return 1; } gpio_set(spi_cs); spi_master = 1; printf("SPI_%i successfully initialized as master, cs: GPIO_%ld, mode: %i, speed: %i\n", spi_dev, (long)spi_cs, spi_mode, spi_speed); return 0; }
int kw2xrf_spi_init(spi_t spi, spi_speed_t spi_speed, gpio_t cs_pin) { int res; kw2xrf_cs_pin = cs_pin; /**< for later reference */ kw2xrf_spi = spi; #if KW2XRF_SHARED_SPI spi_acquire(kw2xrf_spi); #endif res = spi_init_master(kw2xrf_spi, SPI_CONF_FIRST_RISING, spi_speed); #if KW2XRF_SHARED_SPI spi_release(kw2xrf_spi); gpio_init_out(kw2xrf_cs_pin, GPIO_NOPULL); gpio_set(kw2xrf_cs_pin); #endif if (res < 0) { DEBUG("kw2xrf_spi_init: error initializing SPI_%i device (code %i)\n", kw2xrf_spi, res); return -1; } return 0; }
void at86rf231_gpio_spi_interrupts_init(void) { /* set up GPIO pins */ /* SCLK and MOSI*/ GPIOA->CRL &= ~(0xf << (5 * 4)); GPIOA->CRL |= (0xb << (5 * 4)); GPIOA->CRL &= ~(0xf << (7 * 4)); GPIOA->CRL |= (0xb << (7 * 4)); /* MISO */ gpio_init_in(SPI_0_MISO_GPIO, GPIO_NOPULL); /* SPI init */ spi_init_master(SPI_0, SPI_CONF_FIRST_RISING, SPI_SPEED_5MHZ); spi_poweron(SPI_0); /* IRQ0 */ gpio_init_in(SPI_0_IRQ0_GPIO, GPIO_NOPULL); gpio_init_int(SPI_0_IRQ0_GPIO, GPIO_NOPULL, GPIO_RISING, (gpio_cb_t)at86rf231_rx_irq, NULL); /* Connect EXTI4 Line to PC4 pin */ at86rf231_enable_interrupts(); /* CS */ gpio_init_out(SPI_0_CS_GPIO, GPIO_NOPULL); /* SLEEP */ gpio_init_out(SPI_0_SLEEP_GPIO, GPIO_NOPULL); /* RESET */ gpio_init_out(SPI_0_RESET_GPIO, GPIO_NOPULL); }
int ng_at86rf2xx_init(ng_at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed, gpio_t cs_pin, gpio_t int_pin, gpio_t sleep_pin, gpio_t reset_pin) { dev->driver = &ng_at86rf2xx_driver; /* initialize device descriptor */ dev->spi = spi; dev->cs_pin = cs_pin; dev->int_pin = int_pin; dev->sleep_pin = sleep_pin; dev->reset_pin = reset_pin; /* initialise SPI */ spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, spi_speed); /* initialise GPIOs */ gpio_init(dev->cs_pin, GPIO_DIR_OUT, GPIO_NOPULL); gpio_set(dev->cs_pin); gpio_init(dev->sleep_pin, GPIO_DIR_OUT, GPIO_NOPULL); gpio_clear(dev->sleep_pin); gpio_init(dev->reset_pin, GPIO_DIR_OUT, GPIO_NOPULL); gpio_set(dev->reset_pin); gpio_init_int(dev->int_pin, GPIO_NOPULL, GPIO_RISING, _irq_handler, dev); /* test if the SPI is set up correctly and the device is responding */ if (ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__PART_NUM) != NG_AT86RF2XX_PARTNUM) { DEBUG("[ng_at86rf2xx] error: unable to read correct part number\n"); return -1; } /* reset device to default values and put it into RX state */ ng_at86rf2xx_reset(dev); return 0; }
int main(void) { spi_init_master(SPI_MODE0,SPI_CLOCK_DIVIDER128,false); while(1){ spi_transfer(0xff); _delay_ms(50); } return 1; }
/** Set up the SPI buses. * Set up the SPI peripheral, SPI clocks, SPI pins, and SPI pins' clocks. */ void spi_setup(void) { /* Enable SPI1 periperal clock */ RCC_APB2ENR |= RCC_APB2ENR_SPI1EN; /* Enable SPI2 periperal clock */ RCC_APB1ENR |= RCC_APB1ENR_SPI2EN; /* Enable GPIO clocks for CS lines */ RCC_AHB1ENR |= RCC_AHB1ENR_IOPAEN | RCC_AHB1ENR_IOPBEN; /* Setup CS line GPIOs */ /* Deselect FPGA CS */ gpio_set(GPIOA, GPIO4); /* Deselect configuration flash and front-end CS */ gpio_set(GPIOB, GPIO11 | GPIO12); /* FPGA CS */ gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO4); /* Configuration flash CS */ gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO12); /* Front-end CS */ gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO11); /* Setup SPI alternate function */ gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7); gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7); gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO13 | GPIO14 | GPIO15); gpio_set_af(GPIOB, GPIO_AF5, GPIO13 | GPIO14 | GPIO15); /* Setup SPI parameters. */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI1); /* Required, see 25.3.1 section about NSS */ spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI2); /* Required, see 25.3.1 section about NSS */ /* Finally enable the SPI. */ spi_enable(SPI1); spi_enable(SPI2); chMtxInit(&spi_mutex); }
/* *************** HAL API functions **************************************** */ void hal_init( void ) { int ret = 0; /* Reset variables used in file. */ hal_system_time = 0; // hal_reset_flags(); /* Enable GPIOA clock. Enable AFIO clock. */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_AFIOEN ); /* The following pins are output pins. */ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,RST); //reset gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SLP_TR); //sleep gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SEL); //cs gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, SCK | MOSI | MISO); //sck mosi miso spi_disable(RF_SPI); SPI2_I2SCFGR = 0; /* Setup SPI parameters. */ spi_init_master(RF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_16, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_set_unidirectional_mode(RF_SPI); spi_set_full_duplex_mode(RF_SPI); /* Not receive-only */ spi_enable_software_slave_management(RF_SPI); spi_set_nss_high(RF_SPI); spi_enable_ss_output(RF_SPI); /* Required, see NSS, 25.3.1 section. */ /* Finally enable the SPI. */ spi_enable(RF_SPI); /* Set GPIO4 (in GPIO port C) to 'input float'. */ gpio_set_mode(RF_IRQ_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, RF_IRQ_PIN); gpio_clear(RF_IRQ_PORT, RF_IRQ_PIN); /* Configure the EXTI subsystem. */ exti_select_source(EXTI4, RF_IRQ_PORT); exti_set_trigger(EXTI4, EXTI_TRIGGER_RISING); exti_enable_request(EXTI4); exti_reset_request(EXTI4); PRINTF("Enabling interrupts\r\n"); /* Enable EXTI0 interrupt. */ nvic_enable_irq(NVIC_EXTI4_IRQ); nvic_set_priority(NVIC_EXTI4_IRQ,4); //@@@!? timer_init(); // ret = trx_init(); // if(ret!=0) // { // PRINTF("rf231:hal init failed\r\n"); // }else // { // PRINTF("rf231:hal init success\r\n"); // } }
/* * Sets the GPIO pins to SPI mode for the MS5611. * */ static void ms5611_pin_setup() { rcc_periph_clock_enable(RCC_SPI1); //Probably required gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO3 | GPIO4 | GPIO5); //gpio_mode_setup (uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios) gpio_set_af(GPIOB, GPIOB_SPI_AF_NUM ,GPIO3 | GPIO4 | GPIO5); //gpio_set_af (uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios) spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); //SHOULD EQUAL: SPI_CR1_BR_1 | SPI_CR1_CPOL | SPI_CR1_CPHA in CHiBIOS // might require spi_enable_ss_output(SPI1); */ /* Required, see NSS, 25.3.1 section. */ }
void at86rf2xx_setup(at86rf2xx_t *dev, const at86rf2xx_params_t *params) { netdev2_t *netdev = (netdev2_t *)dev; netdev->driver = &at86rf2xx_driver; /* initialize device descriptor */ memcpy(&dev->params, params, sizeof(at86rf2xx_params_t)); dev->idle_state = AT86RF2XX_STATE_TRX_OFF; dev->state = AT86RF2XX_STATE_SLEEP; dev->pending_tx = 0; /* initialise SPI */ spi_init_master(dev->params.spi, SPI_CONF_FIRST_RISING, params->spi_speed); }
static void spi_setup(void) { gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO13 | GPIO14 | GPIO15); gpio_set_af(GPIOB, GPIO_AF5, GPIO13 | GPIO14 | GPIO15); /* Setup SPI parameters. */ spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI2); /* Required, see NSS, 25.3.1 section. */ /* Finally enable the SPI. */ spi_enable(SPI2); }
void TxSpiInit(void) { /* Enable SPI2 */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN); /* Enable GPIOA */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); /* Enable GPIOB */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); /* SCK, MOSI */ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15); /* MISO */ gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); /*CYRF cfg */ /* Reset and CS */ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO11 | GPIO12); gpio_set(GPIOB, GPIO12); gpio_clear(GPIOB, GPIO11); /* A7105 */ //Disable JTAG and SWD AFIO_MAPR = (AFIO_MAPR & ~AFIO_MAPR_SWJ_MASK) | AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF; gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO13); gpio_set(GPIOA, GPIO13); /* CC2500 */ //Disable JTAG and SWD AFIO_MAPR = (AFIO_MAPR & ~AFIO_MAPR_SWJ_MASK) | AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF; gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO14); gpio_set(GPIOA, GPIO14); /* Includes enable? */ spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_16, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_software_slave_management(SPI2); spi_set_nss_high(SPI2); spi_enable(SPI2); }
int ws2812_init(ws2812_t *dev, spi_t spi){ dev->spi = spi; log; /* Init SPI */ spi_poweron(dev->spi); log; spi_acquire(dev->spi); log; int status = spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, SPI_SPEED_4MHZ); log; spi_release(dev->spi); log; return status; }
void main() { spi_init_master(); spi_transive_master(0); while(1) { for(int i = 0; i<256; i++) { spi_transive_master(i); _delay_ms(50); } } }
void inits( void) { cli(); USART_init(MYUBRR, TRUE); can_init(); spi_init_master(); fm_init(); timer0_init(); timer1_init(); //TODO: RUN timer3_init(); timer3_init(); prepare_rx(1, ID_steeringWheel, MASK_FRONT_MODULE, fm_msg_handler); printf("\r\nFront module initialized"); sei(); set_bit(DDRB, DDB6); clear_bit(PORTB, PB6); }
static void acq_spi_init(uint32_t spi) { spi_reset(spi); spi_init_master(spi, SPI_CR1_BAUDRATE_FPCLK_DIV_2, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, 0, SPI_CR1_MSBFIRST); spi_set_data_size(spi, SPI_CR2_DS_14BIT); spi_set_receive_only_mode(spi); spi_fifo_reception_threshold_16bit(spi); SPI_CR2(spi) |= SPI_CR2_NSSP; spi_enable_rx_buffer_not_empty_interrupt(spi); }
static void spi_setup(void) { /* Radio RST */ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO0); /* Configure GPIOs: SS=PA4, SCK=PA5, MISO=PA6 and MOSI=PA7 */ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO4); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5 | GPIO7 ); gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); /* Reset SPI, SPI_CR1 register cleared, SPI is disabled */ spi_reset(SPI1); /* Set up SPI in Master mode with: * Clock baud rate: 1/64 of peripheral clock frequency * Clock polarity: Idle High * Clock phase: Data valid on 2nd clock pulse * Data frame format: 8-bit * Frame format: MSB First */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); /* * Set NSS management to software. * * Note: * Setting nss high is very important, even if we are controlling the GPIO * ourselves this bit needs to be at least set to 1, otherwise the spi * peripheral will not send any data out. */ spi_enable_software_slave_management(SPI1); spi_set_nss_high(SPI1); /* Enable SPI1 periph. */ spi_enable(SPI1); }
int main() { led_on(); usart_init(); debugln("\nUSART initialized"); spi_init_master(); debugln("SPI master"); for(int i=0; i<5; i++) { debugx(spi_tx(42)); debugln(" spi_tx"); } for (;;){} return 1; }
/* Function to setup the SPI1 */ static void spi_setup(void) { /* Enable SPI1 clock. */ rcc_periph_clock_enable(RCC_SPI1); /* reset SPI1 */ spi_reset(SPI1); /* init SPI1 master */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); /* enable SPI1 first */ spi_enable(SPI1); }
/** * initialize - Performs all initialization procedures * * Returns a CHARLIE_STAT_* constant that indicates the succes or * failure of the initialization. */ static uint8_t initialize(void) { charlie.shutdown = FALSE; init_atmega(); init_ports(); debug_init_ports(); rs232_init(); spi_init_master(); i2c_init(); if (rtc_init()) { return CHARLIE_STAT_RTC_ERROR; } time_init(); time_sync_to_realtime(); sched_init(); if (card_init()) { return CHARLIE_STAT_CARD_ERROR; } if (fsys_init()) { return CHARLIE_STAT_FSYS_ERROR; } if (fsys_check_read_only()) { return CHARLIE_STAT_FSYS_READONLY; } cfg_load(); if (enc28j60_init(&cfg.mac_addr)) { return CHARLIE_STAT_NET_ERROR; } net_init(); adc_init(); sensors_init(); pump_init(); plants_init(); sei(); return CHARLIE_STAT_OK; }
void SPITouch_Init() { if(! HAS_TOUCH) return; #if 0 /* Enable SPI1 */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN); /* Enable GPIOA */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); /* Enable GPIOB */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); #endif /* CS */ gpio_set_mode(_TOUCH_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, _TOUCH_PIN); /* PenIRQ is pull-up input*/ gpio_set_mode(_TOUCH_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, _TOUCH_IRQ_PIN); gpio_set(_TOUCH_PORT, _TOUCH_IRQ_PIN); CS_LO(); spi_xfer(SPI1, RESET); CS_HI(); //SPITouch_Calibrate(197312, 147271, -404, -20); /* Read from my Tx */ #if 0 /* SCK, MOSI */ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5 | GPIO7); /* MISO */ gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO6); /* Includes enable */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_software_slave_management(SPI1); spi_set_nss_high(SPI1); spi_enable(SPI1); #endif }
void at86rf2xx_setup(at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed, gpio_t cs_pin, gpio_t int_pin, gpio_t sleep_pin, gpio_t reset_pin) { netdev2_t *netdev = (netdev2_t *)dev; netdev->driver = &at86rf2xx_driver; /* initialize device descriptor */ dev->spi = spi; dev->cs_pin = cs_pin; dev->int_pin = int_pin; dev->sleep_pin = sleep_pin; dev->reset_pin = reset_pin; dev->idle_state = AT86RF2XX_STATE_TRX_OFF; dev->state = AT86RF2XX_STATE_SLEEP; /* initialise SPI */ spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, spi_speed); }
void setup(void) { // setup clock struct rcc_clock_scale clock = rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_120MHZ]; rcc_clock_setup_hse_3v3(&clock); // enable GPIO clock - A (oled), B(oled), C (buttons) rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); // enable SPI clock rcc_periph_clock_enable(RCC_SPI1); // enable OTG FS clock rcc_periph_clock_enable(RCC_OTGFS); // enable RNG rcc_periph_clock_enable(RCC_RNG); RNG_CR |= RNG_CR_IE | RNG_CR_RNGEN; // set GPIO for buttons gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO2 | GPIO5); // set GPIO for OLED display gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4); gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1); // enable SPI 1 for OLED display gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7); gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7); // spi_disable_crc(SPI1); spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI1); // spi_enable_software_slave_management(SPI1); // spi_set_nss_high(SPI1); // spi_clear_mode_fault(SPI1); spi_enable(SPI1); // enable OTG_FS gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12); gpio_set_af(GPIOA, GPIO_AF10, GPIO11 | GPIO12); }
void baro_init() { gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); deselect_slave(); spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI2); spi_enable(SPI2); dma_set_peripheral_address(DMA1, DMA_CHANNEL3, SPI2_DR); dma_set_read_from_memory(DMA1, DMA_CHANNEL3); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3); dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT); dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT); dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH); dma_set_peripheral_address(DMA1, DMA_CHANNEL4, SPI2_DR); dma_set_read_from_peripheral(DMA1, DMA_CHANNEL4); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL4); dma_set_peripheral_size(DMA1, DMA_CHANNEL4, DMA_CCR_PSIZE_8BIT); dma_set_memory_size(DMA1, DMA_CHANNEL4, DMA_CCR_MSIZE_8BIT); dma_set_priority(DMA1, DMA_CHANNEL4, DMA_CCR_PL_VERY_HIGH); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL4); timer_reset(TIM4); timer_enable_irq(TIM4, TIM_DIER_UIE); timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* 3200 / 16 = 200 Hz */ timer_set_prescaler(TIM4, 32); timer_set_period(TIM4, 5625); nvic_set_priority(NVIC_TIM4_IRQ, 16 * 2); nvic_set_priority(NVIC_DMA1_CHANNEL4_IRQ, 16 * 2); nvic_enable_irq(NVIC_TIM4_IRQ); nvic_enable_irq(NVIC_DMA1_CHANNEL4_IRQ); read_calibration_data(); }
void spi_setup(void) { // SPI1 SCK gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_SCK); // SPI1 MOSI gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_MOSI); // SPI ChipSelect gpio_set_mode(MRF_SELECT_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, MRF_SELECT_PIN); gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI1_MISO); /* Setup SPI parameters. */ spi_init_master(MRF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); /* Ignore the stupid NSS pin. */ spi_enable_software_slave_management(MRF_SPI); spi_enable_ss_output(MRF_SPI); spi_set_nss_high(MRF_SPI); /* Finally enable the SPI. */ spi_enable(MRF_SPI); }