void spi_init(spi_t bus)
{
/* make sure given bus device is valid */
assert(bus < SPI_NUMOF);
/* initialize the buses lock */
mutex_init(&locks[bus]);
/* trigger pin initialization */
spi_init_pins(bus);
/* power on the bus temporarily */
poweron(bus);
/* make the base configuration: configure as SPI master, set CS inactive
* state (for HWCS lines) and clear FIFO counters and disable FIFOs */
dev(bus)->MCR = (SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS_MASK |
SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK |
SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK |
SPI_MCR_DOZE_MASK | SPI_MCR_HALT_MASK);
/* disable all DMA and interrupt requests */
dev(bus)->RSER = 0;
/* Wait for the hardware to acknowledge the halt command */
while (dev(bus)->SR & SPI_SR_TXRXS_MASK) {}
/* and power off the bus until it is actually used */
poweroff(bus);
}
void spi_init(spi_t *obj_in, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
spi_obj_t *obj = OBJ_P(obj_in);
uint32_t spi = (uint32_t)NC;
en_clk_dst_t clock;
if (mosi != NC) {
spi = pinmap_merge(spi, pinmap_peripheral(mosi, PinMap_SPI_MOSI));
clock = CY_PIN_CLOCK(pinmap_function(mosi, PinMap_SPI_MOSI));
}
if (miso != NC) {
spi = pinmap_merge(spi, pinmap_peripheral(miso, PinMap_SPI_MISO));
clock = CY_PIN_CLOCK(pinmap_function(miso, PinMap_SPI_MISO));
}
if (sclk != NC) {
spi = pinmap_merge(spi, pinmap_peripheral(sclk, PinMap_SPI_SCLK));
clock = CY_PIN_CLOCK(pinmap_function(sclk, PinMap_SPI_SCLK));
}
if (ssel != NC) {
spi = pinmap_merge(spi, pinmap_peripheral(ssel, PinMap_SPI_SSEL));
clock = CY_PIN_CLOCK(pinmap_function(ssel, PinMap_SPI_SSEL));
}
if (spi != (uint32_t)NC) {
obj->base = (CySCB_Type*)spi;
obj->spi_id = ((SPIName)spi - SPI_0) / (SPI_1 - SPI_0);
obj->pin_mosi = mosi;
obj->pin_miso = miso;
obj->pin_sclk = sclk;
obj->pin_ssel = ssel;
obj->data_bits = 8;
obj->clock = clock;
obj->div_num = CY_INVALID_DIVIDER;
obj->ms_mode = CY_SCB_SPI_MASTER;
#if DEVICE_SPI_ASYNCH
obj->pending = PENDING_NONE;
obj->events = 0;
obj->tx_buffer = NULL;
obj->tx_buffer_size = 0;
obj->rx_buffer = NULL;
obj->rx_buffer_size = 0;
#endif // DEVICE_SPI_ASYNCH
spi_init_clock(obj, SPI_DEFAULT_SPEED);
spi_init_pins(obj);
spi_init_peripheral(obj);
#if DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
obj->pm_callback_handler.callback = spi_pm_callback;
obj->pm_callback_handler.type = CY_SYSPM_DEEPSLEEP;
obj->pm_callback_handler.skipMode = 0;
obj->pm_callback_handler.callbackParams = &obj->pm_callback_params;
obj->pm_callback_params.base = obj->base;
obj->pm_callback_params.context = obj;
if (!Cy_SysPm_RegisterCallback(&obj->pm_callback_handler)) {
error("PM callback registration failed!");
}
#endif // DEVICE_SLEEP && DEVICE_LOWPOWERTIMER
} else {
error("SPI pinout mismatch. Requested Rx and Tx pins can't be used for the same SPI communication.");
}
}
uint8_t u8x8_byte_riotos_hw_spi(u8x8_t *u8g2, uint8_t msg, uint8_t arg_int, void *arg_ptr)
{
spi_t dev = (spi_t) u8g2->dev;
switch (msg) {
case U8X8_MSG_BYTE_SEND:
spi_transfer_bytes(dev, GPIO_UNDEF, true,
arg_ptr, NULL, (size_t)arg_int);
break;
case U8X8_MSG_BYTE_INIT:
spi_init_pins(dev);
break;
case U8X8_MSG_BYTE_SET_DC:
u8x8_gpio_SetDC(u8g2, arg_int);
break;
case U8X8_MSG_BYTE_START_TRANSFER:
spi_acquire(dev, GPIO_UNDEF,
u8x8_spi_mode_to_spi_conf(u8g2->display_info->spi_mode),
u8x8_pulse_width_to_spi_speed(u8g2->display_info->sck_pulse_width_ns));
u8x8_gpio_SetCS(u8g2, u8g2->display_info->chip_enable_level);
u8g2->gpio_and_delay_cb(u8g2, U8X8_MSG_DELAY_NANO, u8g2->display_info->post_chip_enable_wait_ns, NULL);
break;
case U8X8_MSG_BYTE_END_TRANSFER:
u8g2->gpio_and_delay_cb(u8g2, U8X8_MSG_DELAY_NANO, u8g2->display_info->pre_chip_disable_wait_ns, NULL);
u8x8_gpio_SetCS(u8g2, u8g2->display_info->chip_disable_level);
spi_release(dev);
break;
default:
return 0;
}
return 1;
}
void spi_init(spi_t bus)
{
assert(bus < SPI_NUMOF);
/* initialize device lock */
mutex_init(&locks[bus]);
/* initialize pins */
spi_init_pins(bus);
}
struct rf24* radio_init(void)
{
spi_init_pins();
spi_init();
rf24_init(&nrf);
return &nrf;
}
void spi_format(spi_t *obj_in, int bits, int mode, int slave)
{
spi_obj_t *obj = OBJ_P(obj_in);
cy_en_scb_spi_mode_t new_mode = slave? CY_SCB_SPI_SLAVE : CY_SCB_SPI_MASTER;
if ((bits < 4) || (bits > 16)) return;
Cy_SCB_SPI_Disable(obj->base, &obj->context);
obj->data_bits = bits;
obj->clk_mode = (cy_en_scb_spi_sclk_mode_t)(mode & 0x3);
if (obj->ms_mode != new_mode) {
obj->ms_mode = new_mode;
spi_init_pins(obj);
}
spi_init_peripheral(obj);
}
void spi_init(spi_t bus)
{
assert(bus <= SPI_NUMOF);
/* temporarily power on the device */
poweron(bus);
/* configure device to be a master and disable SSI operation mode */
dev(bus)->CR1 = 0;
/* configure system clock as SSI clock source */
dev(bus)->CC = SSI_SS_IODIV;
/* and power off the bus again */
poweroff(bus);
/* trigger SPI pin configuration */
spi_init_pins(bus);
}
void spi_sensor_init(void)
{
uint8_t data_buffer[3] = {0x0, 0x0, 0x0};
spi_init_pins();
spi_master_init(&SPIC);
spi_master_setup_device(&SPIC, &SPI_ADC, SPI_MODE_3, 500000, 0);
spi_enable(&SPIC);
spi_select_device(&SPIC, &SPI_ADC);
spi_write_packet(&SPIC, resetdata, 5);
//clock reg
data_buffer[0] = 0x20;
spi_write_packet(&SPIC, data_buffer, 1);
//data_buffer[0] = 0x00;
data_buffer[0] = clockreg;
spi_write_packet(&SPIC, data_buffer, 1);
//setup reg
data_buffer[0] = 0x10;
spi_write_packet(&SPIC, data_buffer, 1);
//data_buffer[0] = 0x04;
data_buffer[0] = setupreg;
spi_write_packet(&SPIC, data_buffer, 1);
//offset reg
data_buffer[0] = 0x60;
spi_write_packet(&SPIC, data_buffer, 1);
data_buffer[0] = 0x18;
data_buffer[1] = 0x3A;
data_buffer[2] = 0x00;
spi_write_packet(&SPIC, data_buffer, 3);
//gain reg
data_buffer[0] = 0x70;
spi_write_packet(&SPIC, data_buffer, 1);
data_buffer[0] = 0x89;
data_buffer[1] = 0x78;
data_buffer[2] = 0xD7;
spi_write_packet(&SPIC, data_buffer, 3);
spi_deselect_device(&SPIC, &SPI_ADC);
}
void spi_init(spi_t bus)
{
assert(bus <= SPI_NUMOF);
/* we need to differentiate between the legacy SPI device and USCI */
#ifndef SPI_USE_USCI
/* put SPI device in reset state */
SPI_BASE->CTL = USART_CTL_SWRST;
SPI_BASE->CTL |= (USART_CTL_CHAR | USART_CTL_SYNC | USART_CTL_MM);
SPI_BASE->RCTL = 0;
SPI_BASE->MCTL = 0;
/* enable SPI mode */
SPI_ME |= SPI_ME_BIT;
#else
/* reset SPI device */
SPI_BASE->CTL1 = USCI_SPI_CTL1_SWRST;
SPI_BASE->CTL1 |= (USCI_SPI_CTL1_SSEL_SMCLK);
#endif
/* trigger the pin configuration */
spi_init_pins(bus);
}
void spi_init(spi_t bus)
{
/* make sure given bus is good */
assert(bus < SPI_NUMOF);
/* initialize the device lock */
mutex_init(&locks[bus]);
/* configure pins and their muxes */
spi_init_pins(bus);
/* wake up device */
poweron(bus);
/* reset all device configuration */
dev(bus)->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
while ((dev(bus)->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) ||
(dev(bus)->SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST));
/* configure base clock: using GLK GEN 0 */
#if defined(CPU_FAM_SAMD21)
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 |
(SERCOM0_GCLK_ID_CORE + sercom_id(dev(bus))));
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
#elif defined(CPU_FAM_SAML21)
GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + sercom_id(dev(bus))].reg =
(GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0);
#endif
/* enable receiver and configure character size to 8-bit
* no synchronization needed, as SERCOM device is not enabled */
dev(bus)->CTRLB.reg = (SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN);
/* put device back to sleep */
poweroff(bus);
}
