void can_rx_if_clear(void)
{
spi_chipselect(ENABLE);
spi_tx_rx(BIT_MODIFY_CMD);
spi_tx_rx(INT_FLAG_ADDR);
spi_tx_rx(RX_MASK);
spi_tx_rx(0x00); //send 0x00 to clear flags
spi_chipselect(DISABLE);
}
void can_reset(void)
{
//ENABLE SLAVE AND SEND TRANSMIT CODE
spi_chipselect(ENABLE);
spi_tx_rx(RESET);
spi_chipselect(DISABLE);
}
void can_config(int mode)
{
can_reset(); //reset mcp
spi_chipselect(ENABLE); //enable slave
spi_tx_rx(WRITE_CMD);
//Enter config mode
//Send address of CAN CONTROL registerxFF because 0xXFH is mentioned
//0b10000000 to enter config mode
//be aware of potential delay while setting config_mode
can_write_reg(0xFF,0x80); //check config mode is achieved or not
spi_chipselect(DISABLE);
if(can_read_status()>>5 !=0x04)
{
printf("\n\rERROR UNABLE TO ENTER CONFIG MODE\n\r");
}
else
{
static uint8_t
sendStrobe (uint8_t reg)
{
uint8_t rc = 0;
(void)spi_tx_rx(spi, ®, 1, 0, &rc);
return rc;
}
static int
writeRegister (uint8_t reg,
uint8_t val)
{
uint8_t txbuf[2];
uint8_t rxbuf[2];
txbuf[0] = reg;
txbuf[1] = val;
(void)spi_tx_rx(spi, txbuf, 2, 0, rxbuf);
return rxbuf[1];
}
static uint8_t
readRegister (uint8_t reg)
{
uint8_t rxbuf[2];
/* If this is a status register add the BURST bit */
if (0x30 <= reg) {
reg |= 0x40;
}
/* Add the READ bit */
reg |= 0x80;
(void)spi_tx_rx(spi, ®, 1, 1, rxbuf);
return rxbuf[1];
}
void can_transmit(uint8_t buff_num,uint8_t msg_id,uint8_t length, char *data) //ask that can we for address use 8_t!!!!!
{
unsigned char temp=0;
//always maximum priority is used, standard frames no remote request
spi_chipselect(ENABLE); //enable slave (mcp)
//check for pending transmissions
spi_tx_rx((unsigned char)READ_CMD);
spi_tx_rx((unsigned char)0x30+(buff_num*0x10)); //send address of Transmit Control Register (add 10 to base address to point to other buffers)
temp=spi_tx_rx((unsigned char)0); //send zero and get status of buffer (Transmit Control Register) in temp
while(temp & 0x08) //0x08 because TXREQ is position 3 in Transmit control buffer!!!!
{
spi_chipselect(ENABLE);
// temp=spi_tx_rx((unsigned char)0); //keep receiving status of control Transmit Control Register until TXREQ is 0 !!!!
spi_tx_rx((unsigned char)READ_CMD);
spi_tx_rx((unsigned char)0x30+(buff_num*0x10)); //send address of Transmit Control Register (add 10 to base address to point to other buffers)
temp=spi_tx_rx((unsigned char)0); //send zero and get status of buffer (Transmit Control Register) in temp
spi_chipselect(DISABLE);
}
spi_chipselect(DISABLE);
//preparing TX buffer to start transmission
//priority
spi_chipselect(ENABLE);
spi_tx_rx((unsigned char)WRITE_CMD); //send write command when flag is cleared
spi_tx_rx((unsigned char)0x30+(buff_num*0x10)); //send address of Transmit Control Register (add 10 to base address to point to other registers)
spi_tx_rx((unsigned char)0x03); //send message priority as highest (first 2 bits in control register)!!!!
spi_chipselect(DISABLE);
//higher byte of ID
spi_chipselect(ENABLE);
spi_tx_rx(WRITE_CMD);
spi_tx_rx(0x31+(buff_num*0x10)); //send address of Transmit Buffer Std. Identifier HIGH Register (add 10 to base address to point to other registers)
spi_tx_rx((unsigned char)msg_id>>3); //shift out lower 3 bits!!!!
spi_chipselect(DISABLE);
//lower byte of ID
spi_chipselect(ENABLE);
spi_tx_rx(WRITE_CMD);
spi_tx_rx((unsigned char)0x32+(buff_num*0x10)); //send address of Transmit Buffer Std. Identifier LOW Register (add 10 to base address to point to other registers)
spi_tx_rx((unsigned char)msg_id<<5); //shift lower 5 bits to higher position!!!!
spi_chipselect(DISABLE);
//length of data
spi_chipselect(ENABLE);
spi_tx_rx(WRITE_CMD);
spi_tx_rx((unsigned char)0x35+(buff_num*0x10)); //send address of Transmit Buffer Data Length Register, RTR is always 0!!!
spi_tx_rx((unsigned char)(length & 0x0F)); //only lower 4 bits of length are used, RTR=0
spi_chipselect(DISABLE);
//NOW DATA IS SENT
spi_chipselect(ENABLE);
spi_tx_rx(WRITE_CMD);
spi_tx_rx((unsigned char)((0x36+(buff_num*0x10))));
unsigned char loop_var;
for(loop_var=0;loop_var<length;loop_var++)
{
//spi_tx_rx((unsigned char)((0x36+(buff_num*0x10))+loop_var)); //transmit buffer data registers addresses
spi_tx_rx(data[loop_var]); //data to be sent!!!!
}
spi_chipselect(DISABLE);
//set TXREQ to initiate transmission
spi_chipselect(ENABLE);
spi_tx_rx(WRITE_CMD);
//TX initiation part
spi_tx_rx((unsigned char)0x30+(buff_num*0x10)); //send address of Transmit Control Register (add 10 to base address to point to other registers)
spi_tx_rx((unsigned char)0x08); //set TXREQ to start transmission, it is 4th bit!!!!
spi_chipselect(DISABLE); //disable slave
//clear flag!!! YULONG THE GREAT
can_rx_if_clear();
}
static int spi_transmit( comm_channel_t *channel, const char *tx_buf, int tx_items )
{
spi_connection_t *sc = spi_get_connection( channel );
int tx_index = 0;
int rx_items = 0;
if( !sc || tx_items < COMM_OVERHEAD || tx_items > COMM_BUF_SIZE )
{
return( -1 );
}
sc->rx_index = 0;
sc->new_data = 0;
while( 1 )
{
/* check for TX items to transmit */
if( tx_items )
{
sc->rx_buf[ sc->rx_index ] = spi_tx_rx( sc, tx_buf[ tx_index ] );
/* check for end of TX data stream */
if( ++tx_index == tx_items )
{
tx_items = 0;
}
}
else /* transmit null-byte */
{
sc->rx_buf[ sc->rx_index ] = spi_tx_rx( sc, 0 );
}
/* check RX data stream for packet marks and payload size */
if( sc->rx_index == 0 )
{
/* check for first packet mark */
if( sc->rx_buf[0] == COMM_PACKET_MARK )
{
rx_items = COMM_OVERHEAD;
}
}
else
if( sc->rx_index == 1 )
{
/* check for second packet mark */
if( sc->rx_buf[1] != COMM_PACKET_MARK )
{
rx_items = 0;
sc->rx_index = 0;
}
}
else
if( sc->rx_index == 3 )
{
/* second header byte contains payload size */
rx_items += sc->rx_buf[3];
/* check for valid packet size */
if( rx_items > COMM_BUF_SIZE )
{
rx_items = 0;
sc->rx_index = 0;
}
}
/* check for end of RX data stream */
if( rx_items && ++sc->rx_index == rx_items )
{
rx_items = 0;
}
/* check for end of transmission */
if( !tx_items && !rx_items )
{
sc->rx_index = 0;
sc->new_data = 1;
break;
}
}
return( 0 );
}
