/**
* Write data to SPI device
*
* @v nvs NVS device
* @v address Address from which to read
* @v data Data buffer
* @v len Length of data buffer
* @ret rc Return status code
*/
int spi_write ( struct nvs_device *nvs, unsigned int address,
const void *data, size_t len ) {
struct spi_device *device = nvs_to_spi ( nvs );
struct spi_bus *bus = device->bus;
unsigned int command = spi_command ( SPI_WRITE, address,
device->munge_address );
int rc;
DBG ( "SPI %p writing %zd bytes to %#04x\n", device, len, address );
if ( ( rc = bus->rw ( bus, device, SPI_WREN, -1,
NULL, NULL, 0 ) ) != 0 ) {
DBG ( "SPI %p failed to write-enable device\n", device );
return rc;
}
if ( ( rc = bus->rw ( bus, device, command, address,
data, NULL, len ) ) != 0 ) {
DBG ( "SPI %p failed to write data to device\n", device );
return rc;
}
if ( ( rc = spi_wait ( device ) ) != 0 ) {
DBG ( "SPI %p failed to complete write operation\n", device );
return rc;
}
return 0;
}
uint8_t spi_send(uint8_t b) {
uint8_t reply;
SPDR=b;
spi_wait();
reply = SPDR;
return reply;
}
int8 spi_get(TiSpiAdapter * spi, char * pc )
{
if(spi->id == 0)
{
SPI_SPDR = 0;
spi_wait(spi);
*pc = SPI_SPDR;
}
if(spi->id == 1)
{
SSPDR = 0;
spi_wait(spi);
*pc = SSPDR;
}
return 0;
}
void spi_send_byte(BYTE data)
{
#asm
ld hl, 2
add hl, sp
ld a, (hl)
out ($c1),a
#endasm
spi_wait();
}
uint32_t spi_transact(bool readback, int slave, uint32_t data, int length, uint32_t flags)
{
uint32_t control_word = 0;
control_word |= (slave << SPI_CORE_SLAVE_SELECT_SHIFT);
control_word |= (length << SPI_CORE_NUM_BITS_SHIFT);
if ((flags & SPI_PUSH_RISE) != 0) control_word |= (1 << SPI_CORE_DATA_OUT_EDGE_SHIFT);
if ((flags & SPI_PUSH_FALL) != 0) control_word |= (0 << SPI_CORE_DATA_OUT_EDGE_SHIFT);
if ((flags & SPI_LATCH_RISE) != 0) control_word |= (1 << SPI_CORE_DATA_IN_EDGE_SHIFT);
if ((flags & SPI_LATCH_FALL) != 0) control_word |= (0 << SPI_CORE_DATA_IN_EDGE_SHIFT);
const uint32_t data_out = data << (32 - length);
spi_wait();
spi_core->control = control_word;
spi_core->data = data_out;
if (!readback) return 0;
spi_wait();
return readback_mux->spi;
}
uint8_t mcp2515_read_id(uint32_t *id)
{
uint8_t first;
uint8_t tmp;
first = spi_putc(0xff);
tmp = spi_putc(0xff);
if (tmp & (1 << IDE)) {
spi_start(0xff);
*((uint16_t *) id + 1) = (uint16_t) first << 5;
*((uint8_t *) id + 1) = spi_wait();
spi_start(0xff);
*((uint8_t *) id + 2) |= (tmp >> 3) & 0x1C;
*((uint8_t *) id + 2) |= tmp & 0x03;
*((uint8_t *) id) = spi_wait();
return TRUE;
}
uint8 spi_put(TiSpiAdapter * spi, char ch )
{
uint8 ret = 0;
#ifdef GDEBUG
//uart_write( g_uart, "spi_put:\r\n", 10, 0x00 );
#endif
if (spi->id == 0)
{
// SPI_SPSR; // clear all the flags
SPI_SPDR = ch;
spi_wait(spi);
ret = SPI_SPDR;
}
else if (spi->id == 1)
{
SSPDR = ch;
spi_wait(spi);
ret = SSPDR;
}
return ret;
}
int
spi_send(struct spi_handle *sh, int cnt, const uint8_t *data)
{
struct spi_transfer trans;
struct spi_chunk chunk;
spi_transfer_init(&trans);
spi_chunk_init(&chunk, cnt, data, NULL);
spi_transfer_add(&trans, &chunk);
/* enqueue it and wait for it to complete */
spi_transfer(sh, &trans);
spi_wait(&trans);
if (trans.st_flags & SPI_F_ERROR)
return trans.st_errno;
return 0;
}
uint8_t spi_send(uint8_t b) {
uint8_t reply;
#ifdef ISP_LOW_SPEED
cli();
CLKPR = B10000000;
CLKPR = B00000011;
sei();
#endif
SPDR = b;
spi_wait();
reply = SPDR;
#ifdef ISP_LOW_SPEED
cli();
CLKPR = B10000000;
CLKPR = B00000000;
sei();
#endif
return reply;
}
void mcp2515_write_id(const uint32_t *id, uint8_t extended)
{
uint8_t tmp;
if (extended) {
spi_start(*((uint16_t *) id + 1) >> 5);
// naechsten Werte berechnen
tmp = (*((uint8_t *) id + 2) << 3) & 0xe0;
tmp |= (1 << IDE);
tmp |= (*((uint8_t *) id + 2)) & 0x03;
// warten bis der vorherige Werte geschrieben wurde
spi_wait();
// restliche Werte schreiben
spi_putc(tmp);
spi_putc(*((uint8_t *) id + 1));
spi_putc(*((uint8_t *) id));
}
else {
int
spi_send_recv(struct spi_handle *sh, int scnt, const uint8_t *snd,
int rcnt, uint8_t *rcv)
{
struct spi_transfer trans;
struct spi_chunk chunk1, chunk2;
spi_transfer_init(&trans);
spi_chunk_init(&chunk1, scnt, snd, NULL);
spi_chunk_init(&chunk2, rcnt, NULL, rcv);
spi_transfer_add(&trans, &chunk1);
spi_transfer_add(&trans, &chunk2);
/* enqueue it and wait for it to complete */
spi_transfer(sh, &trans);
spi_wait(&trans);
if (trans.st_flags & SPI_F_ERROR)
return trans.st_errno;
return 0;
}
void rtc_send(uint8_t b) {
PORTD &= ~_BV(6);
SPDR = b;
spi_wait();
}
void spi_send(uint8_t b)
{
SPDR = b;
spi_wait();
}
return_value_t loadcell_init()
{
unsigned i;
loadcell_state.init_return = RET_OK;
for (i = 0; i < 4; ++i) {
loadcell_state.values[i] = 0l;
loadcell_state.num_measurements[i] = 0;
}
SHD = 1;
IFS0bits.SPI1IF = 0; // Clear the Interrupt Flag
IEC0bits.SPI1IE = 0; // Disable the Interrupt
// SPI1CON1 Register Settings
SPI1CON1bits.DISSCK = 0; // Internal SPI clock is enabled
SPI1CON1bits.DISSDO = 0; // SDOx pin is controlled by the module
SPI1CON1bits.MODE16 = 0; // Communication is byte-wide (8 bits)
SPI1CON1bits.SMP = 0; // Input data is sampled at the middle of data output time
SPI1CON1bits.CKE = 0; // Serial output data changes on transition
// from Idle clock state to active clock state
SPI1CON1bits.CKP = 1; // Idle state for clock is a high level;
// active state is a low level
SPI1CON1bits.MSTEN = 1; // Master mode enabled
SPI1CON1bits.PPRE = 0b10; //0b01; // Primary prescale bit for SPI clock; 0b11 = 1:1; 0b10 = 4:1; 0b01 = 16:1; 0b00 = 64:1
SPI1CON1bits.SPRE = 0b101; //0b011; // Secondary prescale bit for SPI clock; 0b111 = 1:1; 0b110 = 1:2 ... 0b000 = 1:8
SPI1CON1bits.SSEN = 0; // Slave select pin disabled
SPI1CON2bits.FRMEN = 0; // Frame mode disabled
// SPISTAT Register Settings
SPI1STATbits.SPIEN = 1; // Enable SPI module
SPI1STATbits.SPISIDL = 0; // Continue module operation when device enters Idle mode
// Interrupt Controller Settings
SPI1STATbits.SPIROV = 0; // Clear SPI overflow bit
IFS0bits.SPI1EIF = 0; // Clear SPI1 Error Interrupt Flag Status bit
IPC2bits.SPI1IP = 0x06; // Set SPI1 Interrupt Priority Level to 1 = low priority
IFS0bits.SPI1IF = 0; // Clear the Interrupt Flag
IEC0bits.SPI1IE = 1; // Enable the Interrupt
SG_DESELECT;
loadcell_state.data_ready = 0;
loadcell_state.spi_state = SPI_IDLE;
// Configuration bits for ADC initialization
uint8_t mode_byte_1 = 0;
uint8_t mode_byte_2 = 0;
uint8_t mode_byte_3 = 0;
uint8_t config_byte_1;
uint8_t config_byte_2;
uint8_t config_byte_3;
uint8_t gpocon_byte;
loadcell_state.spi_state = SPI_VARIOUS;
SG_SELECT;
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
}
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
}
//reset chip
SPI1BUF = 0xFF;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = 0xFF;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = 0xFF;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = 0xFF;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = 0xFF;
spi_wait();
SG_DESELECT;
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
}
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
}
SG_SELECT;
//write the MODE register
SPI1BUF = SG_REG_MODE;
spi_wait();
mode_byte_1 = 0b00011100; //continuous mode, transmit status reg, MCLK2 is clock, average off (FS/2)
mode_byte_2 = 0b00001100; //sinc4 enabled | no parity | no clock divide | single ("zero" latency) | 60hz rejection | Last two bits are top two bits of FS
// These bits control the filtering and output freqeuency
// It works in conjuction with the sinc, chopping, 50/60 rejection, and averaging modes
mode_byte_3 = 4;
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = mode_byte_1;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = mode_byte_2;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = mode_byte_3;
spi_wait();
SG_DESELECT;
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
}
SG_SELECT;
loadcell_state.spi_state = SPI_VARIOUS;
// Configuration Register
SPI1BUF = SG_REG_CONFIG;
spi_wait();
//write the CONFIGURATION register
config_byte_1 = 0b00000100; // Chop disabled / REFIN1 ref. / Pseudo enabled
config_byte_2 = 0b00001111; // Enabled AIN1-4 / Disabled AIN5-8
config_byte_3 = 0b01010111; // no burn / Ref. Detect enabled / Buffer enabled / bipolar / GAIN 128
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = config_byte_1;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = config_byte_2;
spi_wait();
loadcell_state.spi_state = SPI_VARIOUS;
SPI1BUF = config_byte_3;
spi_wait();
SG_DESELECT;
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
}
SG_SELECT;
// GPOCON Register
SPI1BUF = SG_REG_GPOCON;
spi_wait();
//write the GPOCON Register
for (i = 0; i < 65; ++i) {
Nop();
}
loadcell_state.spi_state = SPI_VARIOUS;
gpocon_byte = 0b00100100; // no Dridge Power-Down / P3&P2 enabled / P1&P0 disabled / P3 low / P2 High / P1&P0 low
SPI1BUF = gpocon_byte;
spi_wait();
SG_DESELECT;
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
}
IC4CON1bits.ICM = 0b010; //interrupt on falling edge
IC4CON2bits.TRIGSTAT = 0;
for (i = 0; i < 65000; ++i) {
Nop();
Nop();
}
return loadcell_state.init_return;
}
