/* Hard coded nvalues for testing purposes, may cause device to hang! */
static void sr_set_testing_nvalues(struct omap_sr *sr)
{
if (sr->srid == SR1) {
if (cpu_is_omap3630()) {
sr->senp_mod = 0x1;
sr->senn_mod = 0x1;
/* calculate nvalues for each opp */
sr->opp1_nvalue = cal_test_nvalue(581, 489);
sr->opp2_nvalue = cal_test_nvalue(1072, 910);
sr->opp3_nvalue = cal_test_nvalue(1405, 1200);
sr->opp4_nvalue = cal_test_nvalue(1842, 1580);
sr->opp5_nvalue = cal_test_nvalue(1842, 1580);
if (sr_margin_steps || sr_margin_steps_1g)
sr_add_margin_steps(sr);
} else {
sr->senp_mod = 0x03; /* SenN-M5 enabled */
sr->senn_mod = 0x03;
/* calculate nvalues for each opp */
sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100,
0x28c + 0x100);
sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0,
0x3be + 0x1a0);
sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200,
0x655 + 0x200);
sr->opp4_nvalue = cal_test_nvalue(0x964 + 0x2a0,
0x727 + 0x2a0);
sr->opp5_nvalue = cal_test_nvalue(0xacd + 0x330,
0x848 + 0x330);
}
if (sr->opp5_nvalue) {
sr->opp6_nvalue = calculate_opp_nvalue(sr->opp5_nvalue,
227, 379);
}
} else if (sr->srid == SR2) {
if (cpu_is_omap3630()) {
sr->senp_mod = 0x1;
sr->senn_mod = 0x1;
sr->opp1_nvalue = cal_test_nvalue(556, 468);
sr->opp2_nvalue = cal_test_nvalue(1099, 933);
} else {
sr->senp_mod = 0x03;
sr->senn_mod = 0x03;
sr->opp1_nvalue = cal_test_nvalue(0x359, 0x25d);
sr->opp2_nvalue = cal_test_nvalue(0x4f5 + 0x1c0,
0x390 + 0x1c0);
sr->opp3_nvalue = cal_test_nvalue(0x76f + 0x200,
0x579 + 0x200);
}
}
}
static void sr_set_efuse_nvalues(struct omap_sr *sr)
{
if (sr->srid == SR1) {
if (cpu_is_omap3630()) {
sr->senn_mod = sr->senp_mod = 0x1;
sr->opp5_nvalue = sr1_opp[5] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP5_VDD1);
if (sr->opp5_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP5 %x\n",
sr->opp5_nvalue);
} else {
pr_info(KERN_INFO "SR: Nvalues not fused for"
"1.2G, disabled\n");
}
sr->opp4_nvalue = sr1_opp[4] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP4_VDD1);
if (sr->opp4_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP4 %x\n",
sr->opp4_nvalue);
} else {
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp3_nvalue = sr1_opp[3] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP3_VDD1);
if (sr->opp3_nvalue != 0) {
pr_info("SR2:Fused Nvalues for VDD2OPP3 %d\n",
sr->opp3_nvalue);
} else {
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp2_nvalue = sr1_opp[2] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP2_VDD1);
if (sr->opp2_nvalue != 0) {
pr_info("SR2:Fused Nvalues for VDD2OPP2 %d\n",
sr->opp2_nvalue);
} else {
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp1_nvalue = sr1_opp[1] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP1_VDD1);
if (sr->opp1_nvalue != 0) {
pr_info("SR2:Fused Nvalues for VDD2OPP1 %d\n",
sr->opp1_nvalue);
} else {
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
if (sr_margin_steps || sr_margin_steps_1g)
sr_add_margin_steps(sr);
} else {
sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
OMAP343X_SR1_SENNENABLE_MASK) >>
OMAP343X_SR1_SENNENABLE_SHIFT;
sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
OMAP343X_SR1_SENPENABLE_MASK) >>
OMAP343X_SR1_SENPENABLE_SHIFT;
sr->opp5_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP5_VDD1);
if (sr->opp5_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP5 %x\n",
sr->opp5_nvalue);
} else {
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp4_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP4_VDD1);
sr->opp3_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP3_VDD1);
sr->opp2_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP2_VDD1);
sr->opp1_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP1_VDD1);
if (sr->opp5_nvalue) {
sr->opp6_nvalue = calculate_opp_nvalue(sr->opp5_nvalue,
227, 379);
}
}
} else if (sr->srid == SR2) {
static void sr_set_efuse_nvalues(struct omap_sr *sr)
{
u32 senn_adj = 3.0*12.5;
u32 senp_adj = 2.6*12.5;
if (sr->srid == SR1) {
if (cpu_is_omap3630()) {
sr->senn_mod = sr->senp_mod = 0x1;
#if !(defined(CONFIG_MACH_OMAP3621_BOXER) ||\
defined(CONFIG_MACH_OMAP3621_EVT1A) ||\
defined(CONFIG_MACH_OMAP3621_EDP) ||\
defined(CONFIG_MACH_OMAP3621_GOSSAMER))
sr->opp5_nvalue = sr1_opp[5] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP5_VDD1);
if (sr->opp5_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP5 %x\n",
sr->opp5_nvalue);
} else {
pr_info(KERN_INFO "SR: Nvalues not fused for"
"1.2G, disabled\n");
}
sr->opp4_nvalue = sr1_opp[4] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP4_VDD1);
if (sr->opp4_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP4 %x\n",
sr->opp4_nvalue);
} else {
pr_info(KERN_INFO "SR: using test nvalues\n");
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp5_nvalue = sr->opp4_nvalue;
#endif
sr->opp3_nvalue = sr1_opp[3] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP3_VDD1);
if (sr->opp3_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP3 %x\n",
sr->opp3_nvalue);
} else {
pr_info(KERN_INFO "SR: using test nvalues\n");
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp2_nvalue = sr1_opp[2] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP2_VDD1);
if (sr->opp2_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP2 %x\n",
sr->opp2_nvalue);
} else {
pr_info(KERN_INFO "SR: using test nvalues\n");
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp1_nvalue = sr1_opp[1] =
omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP1_VDD1);
if (sr->opp1_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP1 %x\n",
sr->opp1_nvalue);
} else {
pr_info(KERN_INFO "SR: using test nvalues\n");
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
if (sr_margin_steps || sr_margin_steps_1g)
sr_add_margin_steps(sr);
} else {
sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
OMAP343X_SR1_SENNENABLE_MASK) >>
OMAP343X_SR1_SENNENABLE_SHIFT;
sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
OMAP343X_SR1_SENPENABLE_MASK) >>
OMAP343X_SR1_SENPENABLE_SHIFT;
#if !(defined(CONFIG_MACH_OMAP3621_BOXER) ||\
defined(CONFIG_MACH_OMAP3621_EVT1A) ||\
defined(CONFIG_MACH_OMAP3621_EDP) ||\
defined(CONFIG_MACH_OMAP3621_GOSSAMER))
sr->opp5_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP5_VDD1);
if (sr->opp5_nvalue != 0x0) {
pr_info("SR1:Fused Nvalues for VDD1OPP5 %x\n",
sr->opp5_nvalue);
} else {
/* use test nvalues */
sr_set_testing_nvalues(sr);
return;
}
sr->opp4_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP4_VDD1);
#endif
sr->opp3_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP3_VDD1);
sr->opp2_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP2_VDD1);
sr->opp1_nvalue = omap_ctrl_readl(
OMAP343X_CONTROL_FUSE_OPP1_VDD1);
#if !(defined(CONFIG_MACH_OMAP3621_BOXER) ||\
defined(CONFIG_MACH_OMAP3621_EVT1A) ||\
defined(CONFIG_MACH_OMAP3621_EDP) ||\
defined(CONFIG_MACH_OMAP3621_GOSSAMER))
if (sr->opp5_nvalue) {
sr->opp6_nvalue = calculate_opp_nvalue(sr->opp5_nvalue,
227, 379);
}
#endif
}
} else if (sr->srid == SR2) {
