/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
#if LPC_EXT_SDRAM
rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize system timer*/
rt_system_timer_init();
/* initialize application */
rt_application_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
/* initialization for system heap */
int rt_hw_board_heap_init(void)
{
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#if LPC_EXT_SDRAM
sram_init();
#endif
#endif
return 0;
}
void main(void) {
HardwareInit();
UartInit(STDIO,115200,DEFAULT_LINE_CTRL);
heap_size=free_heap();
#if defined DEBUG
test_pattern();
#endif
UartPrint(STDOUT,"video initialization\r");
VideoInit();
delay_ms(500);
UartPrint(STDOUT,"keyboard initialization: ");
if (KeyboardInit()){
UartPrint(STDOUT,"OK\r");
comm_channel=LOCAL_CON;
}else{
UartPrint(STDOUT,"keyboard error\r");
UartPrint(STDOUT,"Using uart2 channel.\r");
comm_channel=SERIAL_CON;
}
text_coord_t cpos;
UartPrint(STDOUT,"SD initialization: ");
if (!mount(0)){
UartPrint(STDOUT,"Failed\r");
SDCardReady=FALSE;
}else{
UartPrint(STDOUT,"succeeded\r");
SDCardReady=TRUE;
}
UartPrint(STDOUT,"SRAM initialization\r");
sram_init();
UartPrint(STDOUT,"sound initialization.\r");
tune((unsigned int*)&e3k[0]);
UartPrint(STDOUT,"initialization completed.\r");
set_cursor(CR_BLOCK); // sauvegare video_buffer dans SRAM
clear_screen();
#if defined _DEBUG_
graphics_test();
set_curpos(0,LINE_PER_SCREEN-1);
print(comm_channel,"test");
sram_write_block(100000,video_bmp,BMP_SIZE);
delay_ms(1000);
clear_screen();
delay_ms(1000);
sram_read_block(100000,video_bmp,BMP_SIZE);
delay_ms(1000);
clear_screen();
// print(comm_channel,"heap_size: ");
// print_int(comm_channel,heap_size,0);
// crlf();
#endif
shell();
} // main()
/* initialization for system heap */
int rt_hw_board_heap_init(void)
{
#ifdef RT_USING_HEAP
#if LPC_EXT_SDRAM
#include "drv_sram.h"
rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#endif
return 0;
}
int main(void)
{
int ret;
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//设置系统中断优先级分组2
delay_init(162);//延时初始化
tim3_init(162);//时钟初始化
sram_init();//SRAM初始化
ads1271_init(0);//ad初始化 参数为0 高速模式
led_init();//LED初始化
read_device_config();//读取flash中设备配置
current_source_init();//恒流源初始化
ethernet_init();//网络初始化
tcp_sever();//建立tcp服务器
while(!is_con());//等待连接
led_link(1);//开启连接灯
while(1)
{
//INT处理部分
ret = deal_int();
if((ret == NET_ERR) || (ret == NET_DISCONNECT))
sys_restart();//重启
//PRE处理部分
ret = deal_pre();
if((ret == NET_ERR) || (ret == NET_DISCONNECT))
sys_restart();//重启
//DIV处理
ret = deal_div();
if((ret == NET_ERR) || (ret == NET_DISCONNECT))
sys_restart();//重启
//STA处理
ret = deal_sta();
if((ret == NET_ERR) || (ret == NET_DISCONNECT))
sys_restart();//重启
//数据传输
while(1)
{
ret = deal_data();
if((ret == NET_ERR) || (ret == NET_DISCONNECT))
sys_restart();//重启
}
}
}
static void system_init(void) {
delay_init();
led_init();
beep_init();
key_init();
uart_init();
lcd_init();
sram_init();
time_init();
flash_inside_init();
flash_outside_init();
led_power_on();
lcd_on();
}
void memories_initialization(void)
{
#ifdef CONF_BOARD_SMC_PSRAM
psram_init();
#endif
#ifdef CONF_BOARD_SRAM
sram_init();
#endif
#ifdef CONF_BOARD_SDRAMC
/* Enable SMC peripheral clock */
pmc_enable_periph_clk(ID_SMC);
/* Complete SDRAM configuration */
sdramc_init((sdramc_memory_dev_t *)&SDRAM_MICRON_MT48LC16M16A2,
sysclk_get_cpu_hz());
#endif
#ifdef CONF_BOARD_AT45DBX
at45dbx_init();
if (at45dbx_mem_check() != true) {
while (1) {
}
}
#endif
#ifdef CONF_BOARD_SD_MMC_HSMCI
uint8_t slot = 0;
sd_mmc_err_t err;
sd_mmc_init();
if (slot == sd_mmc_nb_slot()) {
slot = 0;
}
// Wait for a card and ready
do {
err = sd_mmc_check(slot);
if ((SD_MMC_ERR_NO_CARD != err)
&& (SD_MMC_INIT_ONGOING != err)
&& (SD_MMC_OK != err)) {
while (SD_MMC_ERR_NO_CARD != sd_mmc_check(slot)) {
}
}
} while (SD_MMC_OK != err);
#endif
}
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_EXT_SDRAM
sdram_hw_init();
rt_system_heap_init((void*)EXT_SDRAM_BEGIN, (void*)EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
/* init application */
rt_application_init();
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
/**
* This function will initial STM32 board.
*/
void rt_hw_board_init()
{
/* Configure the MPU attributes as Write Through */
//mpu_init();
/* Enable the CPU Cache */
CPU_CACHE_Enable();
/* STM32F7xx HAL library initialization:
- Configure the Flash ART accelerator on ITCM interface
- Configure the Systick to generate an interrupt each 1 msec
- Set NVIC Group Priority to 4
- Global MSP (MCU Support Package) initialization
*/
HAL_Init();
/* Configure the system clock @ 200 Mhz */
SystemClock_Config();
/* init systick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_EXT_SDRAM
rt_system_heap_init((void*)EXT_SDRAM_BEGIN, (void*)EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
/**
* Run the application code (display messages from the radio and send responses)
*/
int main(void)
{
char pFlagData[32];
/* Porting code -- Don't need to do this
WDTCTL = WDTPW | WDTHOLD; // Disable watchdog timer
P1OUT = 0x00; // Port data output
P2OUT = 0x00;
P1DIR = 0x00; // Port direction register
P2DIR = 0xff;
P1IES = 0x00; // Port interrupt enable (0=dis 1=enabled)
P2IES = 0x00;
P1IE = 0x0F; // Port interrupt Edge Select (0=pos 1=neg)
P2IE = 0x00;
*/
// Setup no buffering for XINETD service
setvbuf( stdout, NULL, _IONBF, 0 );
FILE *pFlagFile = fopen( FLAG_FILE_NAME, "r" );
if ( !pFlagFile )
{
printf( "Failed to read flag data!\n" );
exit(1);
}
memset( pFlagData, 0, 32 );
fgets( pFlagData, 32, pFlagFile );
fclose( pFlagFile );
// Setup sig alarm handler
signal( SIGALRM, sig_alarm_handler );
alarm( MAX_IDLE_SECS );
sram_init();
cli_init_uart();
radio_init_uart();
//init_gui();
// PORT: OLD: g_myTeamID = TEAM_ID_ADDR;
g_myTeamID = 0; // PPP now
puts( "This is an infamous challenge from DEF CON CTF Finals in 2014, in which a custom hardware badge was made by the LegitBS team, I've ported it to work here, enjoy.\n" );
puts( "The buttons are mapped to the arrow keys.\n" );
puts( ".........................................\n" );
puts( "Application Core v1.0" );
puts( "openMSP430 core by Oliver Girard" );
puts( "p.s. I modded the core to make data executable -sirgoon" );
// Enable interrupts
eint();
// Run process loop
/*
while ( 1 )
{
LPM0;
cli_run();
radio_uart_run();
}
*/
interrupt_handler();
}
/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
struct pci_dev *p_smbus;
u8 rev;
u32 temp;
int retval;
int force_otg_hc_mode = 0;
switch (pdev->vendor) {
case PCI_VENDOR_ID_TOSHIBA_2:
/* celleb's companion chip */
if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
ehci->big_endian_mmio = 1;
#else
ehci_warn(ehci,
"unsupported big endian Toshiba quirk\n");
#endif
}
break;
case PCI_VENDOR_ID_INTEL:
if (pdev->device == 0x0811 || pdev->device == 0x0829 ||
pdev->device == 0xE006) {
ehci_info(ehci, "Detected Intel MID OTG HC\n");
hcd->has_tt = 1;
ehci->has_hostpc = 1;
#ifdef CONFIG_USB_OTG
ehci->has_otg = 1;
#endif
force_otg_hc_mode = 1;
hcd->has_sram = 1;
/*
* Disable SRAM for CLVP A0 due to the silicon issue.
*/
if (pdev->device == 0xE006 && pdev->revision < 0xC) {
ehci_info(ehci, "Disable SRAM for CLVP A0\n");
hcd->has_sram = 0;
}
hcd->sram_no_payload = 1;
sram_init(hcd);
} else if (pdev->device == 0x0806) {
ehci_info(ehci, "Detected Langwell MPH\n");
hcd->has_tt = 1;
ehci->has_hostpc = 1;
hcd->has_sram = 1;
hcd->sram_no_payload = 1;
sram_init(hcd);
} else if (pdev->device == 0x0829) {
ehci_info(ehci, "Detected Penwell OTG HC\n");
hcd->has_tt = 1;
ehci->has_hostpc = 1;
} else if (pdev->device == 0x08F2) {
#ifdef CONFIG_USB_EHCI_HCD_SPH
struct ehci_sph_pdata *sph_pdata;
sph_pdata = pdev->dev.platform_data;
if (!sph_pdata) {
ehci_err(ehci, "get SPH platform data failed\n");
retval = -ENODEV;
return retval;
}
/* All need to bypass tll mode */
temp = ehci_readl(ehci, hcd->regs + CLV_SPHCFG);
temp &= ~CLV_SPHCFG_ULPI1TYPE;
ehci_writel(ehci, temp, hcd->regs + CLV_SPHCFG);
sph_pdata->enabled = sph_enabled();
/* Check SPH enabled or not */
if (sph_pdata->enabled == 0) {
/* ULPI 1 ref-clock switch off */
temp = ehci_readl(ehci, hcd->regs + CLV_SPHCFG);
temp |= CLV_SPHCFG_REFCKDIS;
ehci_writel(ehci, temp, hcd->regs + CLV_SPHCFG);
/* Set Power state */
retval = pci_set_power_state(pdev, PCI_D1);
if (retval < 0)
ehci_err(ehci,
"Set SPH to D1 failed, retval = %d\n",
retval);
ehci_info(ehci, "USB SPH is disabled\n");
return -ENODEV;
}
ehci_info(ehci, "Detected SPH HC\n");
hcd->has_tt = 1;
ehci->has_hostpc = 1;
temp = ehci_readl(ehci, hcd->regs + CLV_SPH_HOSTPC);
temp |= CLV_SPH_HOSTPC_PTS;
ehci_writel(ehci, temp, hcd->regs + CLV_SPH_HOSTPC);
device_set_wakeup_enable(&pdev->dev, true);
/* Set Runtime-PM flags for SPH */
hcd->rpm_control = 1;
hcd->rpm_resume = 0;
pm_runtime_set_active(&pdev->dev);
#endif
} else if (pdev->device == 0x119C) {
ehci_info(ehci, "Detected Merr USB2 HC\n");
hcd->has_tt = 1;
ehci->has_hostpc = 1;
} else if (pdev->device == 0x119D) {
ehci_info(ehci, "Detected HSIC HC\n");
hcd->has_tt = 1;
ehci->has_hostpc = 1;
ehci->has_lpm = 0;
hcd->has_sram = 1;
hcd->sram_no_payload = 1;
sram_init(hcd);
device_set_wakeup_enable(&pdev->dev, true);
/* Set Runtime-PM flags for SPH */
hcd->rpm_control = 1;
hcd->rpm_resume = 0;
pm_runtime_set_active(&pdev->dev);
}
}
ehci->caps = hcd->regs;
ehci->regs = hcd->regs +
HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
/* ehci_init() causes memory for DMA transfers to be
* allocated. Thus, any vendor-specific workarounds based on
* limiting the type of memory used for DMA transfers must
* happen before ehci_init() is called. */
switch (pdev->vendor) {
case PCI_VENDOR_ID_NVIDIA:
/* NVidia reports that certain chips don't handle
* QH, ITD, or SITD addresses above 2GB. (But TD,
* data buffer, and periodic schedule are normal.)
*/
switch (pdev->device) {
case 0x003c: /* MCP04 */
case 0x005b: /* CK804 */
case 0x00d8: /* CK8 */
case 0x00e8: /* CK8S */
if (pci_set_consistent_dma_mask(pdev,
DMA_BIT_MASK(31)) < 0)
ehci_warn(ehci, "can't enable NVidia "
"workaround for >2GB RAM\n");
break;
}
break;
}
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
if (force_otg_hc_mode)
ehci_reset(ehci);
retval = ehci_halt(ehci);
if (retval)
return retval;
if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
(pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
/* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
* read/write memory space which does not belong to it when
* there is NULL pointer with T-bit set to 1 in the frame list
* table. To avoid the issue, the frame list link pointer
* should always contain a valid pointer to a inactive qh.
*/
ehci->use_dummy_qh = 1;
ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
"dummy qh workaround\n");
}
/* data structure init */
retval = ehci_init(hcd);
if (retval)
return retval;
switch (pdev->vendor) {
case PCI_VENDOR_ID_NEC:
ehci->need_io_watchdog = 0;
break;
case PCI_VENDOR_ID_INTEL:
ehci->need_io_watchdog = 0;
ehci->fs_i_thresh = 1;
if (pdev->device == 0x27cc) {
ehci->broken_periodic = 1;
ehci_info(ehci, "using broken periodic workaround\n");
}
if (pdev->device == 0x0806 || pdev->device == 0x0811
|| pdev->device == 0x0829 || pdev->device == 0xE006) {
ehci_info(ehci, "disable lpm for langwell/penwell\n");
ehci->has_lpm = 0;
}
if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
hcd->has_tt = 1;
tdi_reset(ehci);
}
break;
case PCI_VENDOR_ID_TDI:
if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
hcd->has_tt = 1;
tdi_reset(ehci);
}
break;
case PCI_VENDOR_ID_AMD:
/* AMD PLL quirk */
if (usb_amd_find_chipset_info())
ehci->amd_pll_fix = 1;
/* AMD8111 EHCI doesn't work, according to AMD errata */
if (pdev->device == 0x7463) {
ehci_info(ehci, "ignoring AMD8111 (errata)\n");
retval = -EIO;
goto done;
}
break;
case PCI_VENDOR_ID_NVIDIA:
switch (pdev->device) {
/* Some NForce2 chips have problems with selective suspend;
* fixed in newer silicon.
*/
case 0x0068:
if (pdev->revision < 0xa4)
ehci->no_selective_suspend = 1;
break;
/* MCP89 chips on the MacBookAir3,1 give EPROTO when
* fetching device descriptors unless LPM is disabled.
* There are also intermittent problems enumerating
* devices with PPCD enabled.
*/
case 0x0d9d:
ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
ehci->has_lpm = 0;
ehci->has_ppcd = 0;
ehci->command &= ~CMD_PPCEE;
break;
}
break;
case PCI_VENDOR_ID_VIA:
if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
u8 tmp;
/* The VT6212 defaults to a 1 usec EHCI sleep time which
* hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
* that sleep time use the conventional 10 usec.
*/
pci_read_config_byte(pdev, 0x4b, &tmp);
if (tmp & 0x20)
break;
pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
}
break;
case PCI_VENDOR_ID_ATI:
/* AMD PLL quirk */
if (usb_amd_find_chipset_info())
ehci->amd_pll_fix = 1;
/* SB600 and old version of SB700 have a bug in EHCI controller,
* which causes usb devices lose response in some cases.
*/
if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SBX00_SMBUS,
NULL);
if (!p_smbus)
break;
rev = p_smbus->revision;
if ((pdev->device == 0x4386) || (rev == 0x3a)
|| (rev == 0x3b)) {
u8 tmp;
ehci_info(ehci, "applying AMD SB600/SB700 USB "
"freeze workaround\n");
pci_read_config_byte(pdev, 0x53, &tmp);
pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
}
pci_dev_put(p_smbus);
}
break;
case PCI_VENDOR_ID_NETMOS:
/* MosChip frame-index-register bug */
ehci_info(ehci, "applying MosChip frame-index workaround\n");
ehci->frame_index_bug = 1;
break;
}
/* optional debug port, normally in the first BAR */
temp = pci_find_capability(pdev, 0x0a);
if (temp) {
pci_read_config_dword(pdev, temp, &temp);
temp >>= 16;
if ((temp & (3 << 13)) == (1 << 13)) {
temp &= 0x1fff;
ehci->debug = ehci_to_hcd(ehci)->regs + temp;
temp = ehci_readl(ehci, &ehci->debug->control);
ehci_info(ehci, "debug port %d%s\n",
HCS_DEBUG_PORT(ehci->hcs_params),
(temp & DBGP_ENABLED)
? " IN USE"
: "");
if (!(temp & DBGP_ENABLED))
ehci->debug = NULL;
}
}
ehci_reset(ehci);
/* at least the Genesys GL880S needs fixup here */
temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
temp &= 0x0f;
if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
ehci_dbg(ehci, "bogus port configuration: "
"cc=%d x pcc=%d < ports=%d\n",
HCS_N_CC(ehci->hcs_params),
HCS_N_PCC(ehci->hcs_params),
HCS_N_PORTS(ehci->hcs_params));
switch (pdev->vendor) {
case 0x17a0: /* GENESYS */
/* GL880S: should be PORTS=2 */
temp |= (ehci->hcs_params & ~0xf);
ehci->hcs_params = temp;
break;
case PCI_VENDOR_ID_NVIDIA:
/* NF4: should be PCC=10 */
break;
}
}
/* Serial Bus Release Number is at PCI 0x60 offset */
pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
if (pdev->vendor == PCI_VENDOR_ID_STMICRO
&& pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
ehci->sbrn = 0x20; /* ConneXT has no sbrn register */
/* Keep this around for a while just in case some EHCI
* implementation uses legacy PCI PM support. This test
* can be removed on 17 Dec 2009 if the dev_warn() hasn't
* been triggered by then.
*/
if (!device_can_wakeup(&pdev->dev)) {
u16 port_wake;
pci_read_config_word(pdev, 0x62, &port_wake);
if (port_wake & 0x0001) {
dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
device_set_wakeup_capable(&pdev->dev, 1);
}
}
#ifdef CONFIG_USB_SUSPEND
/* REVISIT: the controller works fine for wakeup iff the root hub
* itself is "globally" suspended, but usbcore currently doesn't
* understand such things.
*
* System suspend currently expects to be able to suspend the entire
* device tree, device-at-a-time. If we failed selective suspend
* reports, system suspend would fail; so the root hub code must claim
* success. That's lying to usbcore, and it matters for runtime
* PM scenarios with selective suspend and remote wakeup...
*/
if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif
ehci_port_power(ehci, 1);
retval = ehci_pci_reinit(ehci, pdev);
done:
return retval;
}
/* cart hardware detection */
void cart_hw_init()
{
int i;
/***************************************************************************************************************
CARTRIDGE ROM MIRRORING
***************************************************************************************************************
Cartridge area is mapped to $000000-$3fffff:
-> when accessing ROM, 68k address lines A1 to A21 are used by the internal cartridge hardware to decode the
full 4MB address range.
-> depending on the ROM total size, some address lines might be ignored, resulting in ROM mirroring.
Cartridges can use either 8-bits (x2) or 16-bits (x1, x2) Mask ROM chips, each chip size is a factor of 2 bytes:
-> two 8-bits chips are equivalent to one 16-bits chip, no specific address decoding is required, needed
address lines are simply connected to each chip, upper address lines are ignored and data lines are
connected appropriately to each chip (D0-D7 to one chip, D8-D15 to the other one).
ROM is mirrored each N bytes where N=2^(k+1) is the total ROM size (ROM1+ROM2,ROM1+ROM2,...).
-> one single 16-bits chip do not need specific address decoding, address lines are simply connected
depending on the ROM size, upper address lines being ignored.
ROM is mirrored each N bytes where N=2^k is the size of the ROM chip (ROM1,ROM1,ROM1,...).
-> two 16-bits chips of the same size are equivalent to one chip of double size, address decoding generally
is the same except that specific hardware is used (one address line is generally used for chip selection,
lower ones being used to address the chips and upper ones being ignored).
ROM is mirrored continuously each N bytes where N=2^(k+1) is the total ROM size (ROM1,ROM2,ROM1,ROM2,...).
-> two 16-bits chips with different size are mapped differently. Address decoding is done the same way as
above (one address line used for chip selection) but the ignored & required address lines differ from
one chip to another, which makes ROM mirroring different.
ROM2 size is generally half of ROM1 size and ROM are mirrored like that : ROM1,ROM2,ROM2,ROM1,ROM2,ROM2,...
From the emulator point of view, we only need to distinguish 3 cases:
1/ total ROM size is a factor of 2: ROM is mirrored each 2^k bytes.
2/ total ROM size is not a factor of 2 and cartridge uses one or two chips of the same size (Type A):
ROM is padded up to 2^k and mirrored each 2^k bytes.
3/ total ROM size is not a factor of 2 and cartridge uses two chips of different sizes (Type B):
ROM is not padded and the first 2^(k-1) bytes are mirrored each 2^k bytes while the next 2^(k-2) bytes are
mirrored in the last 2^(k-2) bytes.
******************************************************************************************************************/
/* calculate nearest size with factor of 2 */
unsigned int size = 0x10000;
while (cart.romsize > size)
size <<= 1;
/* total ROM size is not a factor of 2 */
/* TODO: handle more possible ROM configurations (using cartridge database ???) */
if ((size < MAXROMSIZE) && (cart.romsize < size))
{
/* two chips with different size */
if (config.romtype)
{
/* third ROM section is mirrored in the last section */
memcpy(cart.rom + cart.romsize, cart.rom + 2*cart.romsize - size, size - cart.romsize);
}
else
{
/* ROM is padded up to 2^k bytes */
memset(cart.rom + cart.romsize, 0xff, size - cart.romsize);
}
}
/* special case: Sonic & Knuckles */
/* $200000-$3fffff is mapped to external cartridge */
if (strstr(rominfo.international,"SONIC & KNUCKLES") != NULL)
{
/* disable ROM mirroring */
size = 0x400000;
}
/* ROM is mirrored each 2^k bytes */
cart.mask = size - 1;
/**********************************************
DEFAULT CARTRIDGE MAPPING
***********************************************/
for (i=0; i<0x40; i++)
{
/* cartridge ROM */
m68k_memory_map[i].base = cart.rom + ((i<<16) & cart.mask);
m68k_memory_map[i].read8 = NULL;
m68k_memory_map[i].read16 = NULL;
m68k_memory_map[i].write8 = m68k_unused_8_w;
m68k_memory_map[i].write16 = m68k_unused_16_w;
zbank_memory_map[i].read = NULL;
zbank_memory_map[i].write = zbank_unused_w;
}
for (i=0x40; i<0x80; i++)
{
/* unused area */
m68k_memory_map[i].base = cart.rom + (i<<16);
m68k_memory_map[i].read8 = m68k_read_bus_8;
m68k_memory_map[i].read16 = m68k_read_bus_16;
m68k_memory_map[i].write8 = m68k_unused_8_w;
m68k_memory_map[i].write16 = m68k_unused_16_w;
zbank_memory_map[i].read = zbank_unused_r;
zbank_memory_map[i].write = zbank_unused_w;
}
/**********************************************
BACKUP MEMORY
***********************************************/
sram_init();
eeprom_init();
if (sram.on)
{
if (sram.custom)
{
/* Serial EEPROM */
m68k_memory_map[eeprom.type.sda_out_adr >> 16].read8 = eeprom_read_byte;
m68k_memory_map[eeprom.type.sda_out_adr >> 16].read16 = eeprom_read_word;
m68k_memory_map[eeprom.type.sda_in_adr >> 16].read8 = eeprom_read_byte;
m68k_memory_map[eeprom.type.sda_in_adr >> 16].read16 = eeprom_read_word;
m68k_memory_map[eeprom.type.scl_adr >> 16].write8 = eeprom_write_byte;
m68k_memory_map[eeprom.type.scl_adr >> 16].write16 = eeprom_write_word;
zbank_memory_map[eeprom.type.sda_out_adr >> 16].read = eeprom_read_byte;
zbank_memory_map[eeprom.type.sda_in_adr >> 16].read = eeprom_read_byte;
zbank_memory_map[eeprom.type.scl_adr >> 16].write = eeprom_write_byte;
}
else
{
int main()
{
CLEAR_WRITE();
SET_STOPMOTOR();
CLEAR_SCANMEDIA();
CLEAR_MEDIASET();
CLEAR_READY();
//setup led and button gpio
GPIO_SetMode(LED_G_PORT, LED_G_PIN, GPIO_PMD_OUTPUT);
GPIO_SetMode(LED_R_PORT, LED_R_PIN, GPIO_PMD_OUTPUT);
GPIO_SetMode(SWITCH_PORT, SWITCH_PIN, GPIO_PMD_INPUT);
GPIO_SetMode(IRDATA_PORT, IRDATA_PIN, GPIO_PMD_INPUT);
LED_GREEN(0);
LED_RED(1);
detect_board_version();
/* Unlock protected registers */
SYS_UnlockReg();
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
UART0_Init();
SPI_Init();
TIMER_Open(TIMER0, TIMER_CONTINUOUS_MODE, 6000000);
TIMER_Open(TIMER1, TIMER_PERIODIC_MODE, TRANSFER_RATE * 2);
TIMER_Open(TIMER3, TIMER_PERIODIC_MODE, TRANSFER_RATE * 2);
TIMER_EnableInt(TIMER1);
TIMER_EnableInt(TIMER3);
/* Open USB controller */
USBD_Open(&gsInfo, HID_ClassRequest, NULL);
/* Init Endpoint configuration for HID */
HID_Init();
/* Start USB device */
USBD_Start();
/* Enable USB device interrupt */
NVIC_EnableIRQ(USBD_IRQn);
LED_GREEN(1);
LED_RED(0);
printf("\n\nnuc123-fdsemu v%d.%02d build %d started. Compiled on "__DATE__" at "__TIME__"\n",version / 100,version % 100,BUILDNUM);
printf("--CPU @ %0.3f MHz\n", (double)SystemCoreClock / 1000000.0f);
printf("--SPI0 @ %0.3f MHz\n", (double)SPI_GetBusClock(SPI0) / 1000000.0f);
printf("--SPI1 @ %0.3f MHz\n", (double)SPI_GetBusClock(SPI1) / 1000000.0f);
printf("--Detected board version: %d (config = %d %d %d)\n", boardver,PA12,PA13,PA14);
NVIC_SetPriority(USBD_IRQn,2);
NVIC_SetPriority(TMR1_IRQn,1);
NVIC_SetPriority(TMR2_IRQn,0);
NVIC_SetPriority(TMR3_IRQn,0);
NVIC_SetPriority(GPAB_IRQn,0);
NVIC_SetPriority(EINT0_IRQn,0);
flash_init();
sram_init();
fds_init();
print_block_info(0);
while(1) {
if(havepacket) {
havepacket = 0;
// process_send_feature(epdata,64);
}
console_tick();
fds_tick();
}
}
void console_tick(void)
{
int ch = 0;
if(read_char(&ch) == 0) {
int n;
char help[] =
"help:\r\n"
" 0-F : select block to read disk data from\r\n"
" i : insert disk\r\n"
" r : remove disk\r\n"
" f : flip disk to next side/disk\r\n"
" p : print disks stored in flash\r\n"
" d : disk read mode\r\n"
" t : transfer mode\r\n"
"\r\n";
switch((char)ch) {
case '?':
printf("%s",help);
printf("currently selected disk in block is %d.\r\n\r\n",diskblock);
break;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
case 'A':
case 'B':
case 'C':
case 'D':
case 'E':
case 'F':
if(ch >= 'A' && ch <= 'F') {
diskblock = 10 + (ch - 'A');
}
else {
diskblock = ch - '0';
}
printf("selected disk in block %X.\r\n",diskblock);
break;
case 'i':
fds_insert_disk(diskblock);
break;
case 'r':
fds_remove_disk();
break;
case 'p':
for(n=0;n<0x10;n++) {
print_block_info(n);
}
break;
case 's':
flash_init();
sram_init();
break;
case 'd':
fds_setup_diskread();
break;
case 't':
fds_setup_transfer();
if(IS_READY()) printf("drive is ready\n");
else printf("drive is not ready\n");
if(IS_MEDIASET()) printf("media is set\n");
else printf("media is not set\n");
if(IS_WRITABLE()) printf("media is writable\n");
else printf("media is not writable\n");
if(IS_MOTORON()) printf("motor is on\n");
else printf("motor is not on\n");
break;
case 'c':
sram_read(3537,crap,256);
hexdump("crap",crap,256);
break;
case 'v':
printf("stopping read\n");
CLEAR_WRITE();
CLEAR_SCANMEDIA();
SET_STOPMOTOR();
break;
case 'I':
printf("ident: '%s'\n",ident.ident);
break;
}
}
}
int main()
{
//uint8_t test_result=0;
//************************( 1 )*******************************************************
DDRD|=(1<<6)|(1<<7);//set LED pins as output
//PORTD&=~(1<<3);//vibration off
uart_init();//Keep this as first init so that text can be sent out in others
uart_puts("Starting up....");
_delay_ms(500);
PORTD|=1<<6;
_delay_ms(500);
PORTD&=~(1<<6);
spi_init(); //initialize SPI bus as master
init_tcnt2();//set up timer (RTC)
init_twi(); //initialize TWI interface
sei();
uart_puts("Pre Init...");
PORTB&=~(1<<sensor1_cs);//select sensor
SPIinit_MPU(MPU9250_FULL_SCALE_4G,MPU9250_GYRO_FULL_SCALE_500DPS);//init sensor
PORTB|=(1<<sensor1_cs);//deselect sensor
//init_MPU(MPU9250_FULL_SCALE_4G,MPU9250_GYRO_FULL_SCALE_500DPS, MPU9250_DEFAULT_ADDRESS); //initialize the 9axis sensor
//init_MPU(0,0, 0xD1); //initialize the 9axis sensor
//init_MPU(MPU9250_FULL_SCALE_4G,MPU9250_GYRO_FULL_SCALE_500DPS, MPU9250_DEFAULT_ADDRESS); //initialize the 9axis sensor
sram_init();//initialize sram
uart_puts("Post Init...");
//vibrate(100); //Send feedback showing complete setup
PORTD |=(1<<6)|(1<<7);
PORTD &=~(1<<7);
_delay_ms(200);
PORTD |=(1<<7);
PORTD &=~(1<<6);// blinks both lights to show the program is starting
_delay_ms(200);
PORTD |=(1<<6);
_delay_ms(1000);
record_shot();
while(1){} //*****************STOP POINT**********************
/*
test_result = test_com(0, MPU9250_DEFAULT_ADDRESS);
if(test_result)
{
uart_puts("MPU Status: OK\n");
}
else
uart_puts("MPU Status: FAILURE... You suck!\n");
*/
char rx_char;
uint16_t i=0;//used for for loops
//*****Fix me*******
//should set to int 0 not char '0' but the ascii zero prints better for now
for(i=0;i<512;i++){sd_buf[i]='0';}//sets inital buffer to zero values
uint16_t shot_count=0;
while(1)
{
//************************( 2 )*******************************************************
PORTD &=~(1<<7);
_delay_ms(2000);//Show red light for 2 sec, then turn green and start shot
PORTD |=(1<<7);
PORTD &=~(1<<6);
//************************( 3 )*******************************************************
//vibrate(100);
record_shot();//record a shot
char shots_s[10];
itoa(num_records,shots_s,10);
uart_puts("In 20 seconds The number of records was: ");
uart_puts(shots_s);
uart_putc('\n');
print_shot();
shot_count++;
itoa(shot_count,shots_s,10);
uart_puts("Shot Number: ");
uart_puts(shots_s);
uart_putc('\n');
//print_shot();
PORTD |=(1<<6);//turn off light
//vibrate(100);_delay_ms(100);vibrate(100); //Double vibration showing end of shot
//check_voltage();//Check system voltage
_delay_ms(5000);//wait 60 seconds
//************************( 6 )*******************************************************
continue; //start over and take another shot
uart_puts("Starting Testing\n\n");
uart_putc('\r');
rx_char=uart_getc();
if(rx_char=='c')
{
uart_puts("Command line:\n\n");
rx_char=uart_getc();
while(rx_char!='c')
{
if(rx_char=='s'){}
if(rx_char=='w'){}
if(rx_char=='r'){}//buffer gets set to sector!!
if(rx_char=='i'){}
rx_char=uart_getc();
}
}
// uint8_t i=0;
//Load values into 10 memory locations
//Zero is only skipped to avoid loading zero into the byte
//since when the byte is read back, zero could also mean communication failed
for(i=48;i<=57;i++)
{
sram_write(i,add_m,add_h,i);//only lower address byte is incremented
//uart_putc(i);
}//end loading for loop
//change value in one spot in array as build in "error"
sram_write(50,add_m,add_h,100);
//check values in first 10 memory locations, one should be "wrong"
for(i=48;i<57;i++)
{
_delay_ms(100);
PORTB |=(1<<1)|(1<<2);
_delay_ms(100);
if (sram_read(i,add_m,add_h)==i)
{
PORTB &=~(1<<1);
uart_puts("passed\n");
}//Byte read back correct GREEN light
else{PORTB &=~(1<<2);uart_puts("FAILED!!\n");}//Byte Read back was incorrect RED light
}//end for loop for checking values
PORTB |=(1<<1)|(1<<2);//both lights off
uart_puts("****Tesst finished*****\r\r");
_delay_ms(1500);//wait 1.5 seconds before starting again
} //end while
} //end main
int main(void)
{
#ifndef NO_DEBUG
uart_init();
stdout = &uart_stdout;
banner();
#endif
shared_memory_init();
system_init();
sram_init();
pwm_init();
irq_init();
boot_startup_rom(50);
globals_init();
pwm_stop();
usbInit();
usb_connect();
sei();
while (1) {
system_set_bus_avr();
system_set_wr_disable();
while (usb_trans.req_state != REQ_STATUS_SNES) {
usbPoll();
#if DO_SHELL
#ifndef NO_DEBUG
shell_run();
#endif
#endif
}
#if DO_SHM
shared_memory_write(SHARED_MEM_TX_CMD_TERMINATE, 0);
#endif
#if DO_SHM_SCRATCHPAD
shared_memory_scratchpad_region_tx_restore();
shared_memory_scratchpad_region_rx_restore();
#endif
#if DO_CRC_CHECK
info_P(PSTR("-->CRC Check\n"));
crc_check_bulk_memory(0x000000,
usb_trans.req_bank_size * usb_trans.req_bank_cnt,
usb_trans.req_bank_size);
#endif
system_set_rom_mode(&usb_trans);
system_set_wr_disable();
system_set_bus_snes();
system_send_snes_reset();
irq_stop();
while ((usb_trans.req_state != REQ_STATUS_AVR)) {
usbPoll();
#if DO_SHELL
#ifndef NO_DEBUG
shell_run();
#endif
#endif
}
info_P(PSTR("-->Switch TO AVR\n"));
shared_memory_init();
irq_init();
if (usb_trans.loader_enabled) {
boot_startup_rom(50);
} else {
system_set_bus_avr();
system_send_snes_reset();
}
globals_init();
}
return 0;
}
