/* write_7366(): Writes bytes in array "bytearray" to register "reg".
The number of bytes written depends on the reister and mode.
Config registers will write 1 byte. Other registers will
write the number of bytes specified by COUNTER_BYTES */
void write_7366(int module, int reg,unsigned char *bytearray) {
unsigned char ir = (0x2 << 6 ) | (reg << 3); //Instruction
unsigned char ReadData;
if ( (reg == MDR0) || (reg == MDR1) || (reg == STR) ) {
//One byte to write
ss_low(module);
delay(); //Setup time
SpiChnPutC(SPICHN, ir); //Write instruction after TX buffer empty
while(SpiChnRxBuffFull(SPICHN)==0); //Wait for RX buffer full
ReadData = SpiChnGetC(SPICHN); //Read what was clocked in during last write (nothing)
SpiChnPutC(SPICHN, bytearray[0]); //Clock out write byte after TX buffer empty
while(SpiChnRxBuffFull(SPICHN)==0); //Wait for RX buffer full
ReadData = SpiChnGetC(SPICHN); //Read what was clocked in during last write (garbage /dont care)
ss_high(module); //End comm
return;
}
if ( (reg == DTR) || (reg == CNTR) || (reg == OTR) ) {
//1-4 bytes to read
ss_low(module);
delay(); //Setup time
SpiChnPutC(SPICHN, ir); //Write instruction after TX buffer empty
while(SpiChnRxBuffFull(SPICHN)==0); //Wait for RX buffer full
ReadData = SpiChnGetC(SPICHN); //Read what was clocked in during last write (nothing)
//Do reads
int i;
for (i=0;i<COUNTER_BYTES;i++) {
SpiChnPutC(SPICHN, bytearray[i]); //Clock out byte after TX buffer empty
while(SpiChnRxBuffFull(SPICHN)==0); //Wait for RX buffer full
ReadData = SpiChnGetC(SPICHN); //Read what was clocked in during last write (don't care)
}
ss_high(module); //End comm
return;
}
}
/**************************************************
* Function name :
* Created by :
* Date created :
* Description :
* Notes :
***************************************************/
void read_callback(U8 *Rx_buffer, U8 length)
{
ss_high();
__delay_cycles(1000);
ss_low();
SPI_transfer (0, read_packet.read_frame, 7, control_callback);
}
/* clear_reg_7366(): Clears the given register */
void clear_reg_7366(int module, int reg) {
char ReadData;
char ir = (reg << 3); //Instruction
ss_low(module);
delay(); //Setup time
SpiChnPutC(SPICHN, ir); //Write instruction after TX buffer empty
while(SpiChnRxBuffFull(SPICHN)==0); //Wait for RX buffer full
ReadData = SpiChnGetC(SPICHN); //Read what was clocked in during last write (nothing)
ss_high(module);
}
/**************************************************
* Function name :
* Created by :
* Date created :
* Description :
* Notes :
***************************************************/
void timer_cb(void)
{
if(configuration_flag == 0x01)
{
SPI_break();
configuration_flag = 0x00;
ss_high();
__delay_cycles(5000000);
flag = 1;
}
}
uint8_t spi_send_receive(uint8_t send_data, uint8_t* received_data, uint8_t chipselect){
switch(state.send_receive){
case IDLE:
ss_high(chipselect);
ss_low(chipselect);
SPDR = send_data;
state.send_receive = SENDING;
break;
case SENDING:
if(!(SPSR & (1<<SPIF))){
state.send_receive = RECEIVING;
}
break;
case RECEIVING:
*received_data = SPDR;
ss_high(chipselect);
state.send_receive = IDLE;
break;
}
return state.send_receive;
}
void start_conversion()
{
uint16_t REG = 0;
//Steg 2 conversion
ss_low();
send_spi(START_CONVERSION);
REG = get_spi(0xFF);
ss_high();
if (REG & (1 << 15)) start_conversion();
REG = 0;
}
void deactivate_adc()
{
uint16_t REG = 0;
//Avaktivera adc omvandlingen
ss_low();
send_spi(DEACTIVATE_ADC);
REG = get_spi(0xFF);
ss_high();
if (REG & (1 << 15)) deactivate_adc();
REG = 0;
}
void activate_adc()
{
uint16_t REG = 0;
//Steg 1 sätt ADC till aktiv mode
ss_low();
send_spi(ACTIVATE_ADC);
REG = get_spi(0xFF);
ss_high();
if (REG & (1 << 15)) activate_adc();
REG = 0;
_delay_us(200);
}
void setup_counters() {
//Init I/O
//D1 has been set to slave select in 7366.h
TRISDbits.TRISD1 = 0; //Output for SS3
TRISEbits.TRISE9 = 0; //Output for SS2
TRISEbits.TRISE6 = 0; //Output for SS1
ss_high(MOT); ss_high(MAG1); ss_high(MAG2); // start all slave selects on high
//SPI setup
int rData = SPI1BUF; //Clears receive buffer
IFS0CLR = 0x03800000; //Clears any existing event (rx / tx/ fault interrupt)
SPI1STATCLR = 0x40; //Clears overflow
//Enables the SPI channel (channel, master mode enable | use 8 bit mode | turn on, clock divider)
SpiChnOpen(SPICHN, SPI_CON_MSTEN | SPI_CON_MODE8 | SPI_CON_ON|SPI_CKE_ON, 128); // divide fpb by 128, configure the I/O ports.
//Init 7366R
enable_7366(MAG1,QUADRATURE_X4 | MODULO_N | DISABLE_INDX,NO_FLAGS);
enable_7366(MAG2,QUADRATURE_X4 | MODULO_N | DISABLE_INDX,NO_FLAGS);
enable_7366(MOT,QUADRATURE_X4 | MODULO_N | DISABLE_INDX,NO_FLAGS);
unsigned char writebuf[COUNTER_BYTES];
//Note that MSB should be in slot 0
writebuf[1] = 0x58;
writebuf[0] = 0x98;
//Sets up DTR to contain 0x9858 = 39,000 (ticks/rev)
write_7366(MAG1,DTR, writebuf);
write_7366(MAG2,DTR, writebuf);
write_7366(MOT,DTR, writebuf);
clear_reg_7366(MAG1,STR);
clear_reg_7366(MAG2,STR);
clear_reg_7366(MOT,STR);
clear_reg_7366(MAG1,CNTR);
clear_reg_7366(MAG2,CNTR);
clear_reg_7366(MOT,CNTR);
}
uint16_t get_angular_rate()
{
uint16_t REG = 0;
uint16_t DATA = 0;
//Steg 3 poll
ss_low();
send_spi(POLL);
_delay_us(200);
//if (REG & (1 << 15)) get_angular_rate();
REG = get_spi(0xFF);
ss_high();
REG = REG >> 1;
DATA = REG & 0x07FF;
return DATA;
}
/**************************************************
* Function name :
* Created by :
* Date created :
* Description :
* Notes :
***************************************************/
void control_callback(U8 *Rx_buffer, U8 length)
{
ss_high();
configuration_flag = 0x01;
if(read_packet.read_pos.control_byte != 0xA5)
{
ss_high();
__delay_cycles(1000);
ss_low();
SPI_transfer (0, read_packet.read_frame, 7, control_callback);
}
// if(read_packet.read_pos.control_byte == 0x00)
// {
// error_cnt++;
// if(error_cnt < ERROR_CNT)
// {
// SPI_transfer (0, read_packet.read_frame, 7, control_callback);
// }
// else
// {
// error_cnt = 0x00;
// ss_high();
// sensor_union[DIS_number].sensor_data.status = ERROR_CONTROL_BYTE;
// sensor_cb();
// }
// }
// else
// {
// if(read_packet.read_pos.control_byte == 0xA5)
// {
// error_cnt = 0x00;
// ss_high();
// sensor_union[DIS_number].sensor_data.status = OK;
// sensor_cb();
// }
// else
// {
// if(read_packet.read_pos.status_byte == 0xA5)
// {
// error_cnt = 0x00;
// ss_high();
// for(U8 i=0; i <7; i++)
// {
// read_packet.read_frame[i] = read_packet.read_frame[i + 1];
// }
// sensor_union[DIS_number].sensor_data.status = OK;
// sensor_cb();
// }
// else
// {
// error_cnt++;
// if(error_cnt < ERROR_CNT)
// {
// ss_high();
// ss_low();
// SPI_transfer (write_packet.write_frame, read_packet.read_frame, 7, read_callback);
// }
// else
// {
// error_cnt = 0x00;
// ss_high();
// sensor_union[DIS_number].sensor_data.status = ERROR_CONTROL_BYTE;
// sensor_cb();
// }
// }
// }
// }
}
