static u32 ssb_pci_setup(struct b44_private *bp, u32 cores) { u32 bar_orig, pci_rev, val; pci_read_config_dword(bp->pci, SSB_BAR0_WIN, &bar_orig); pci_write_config_dword(bp->pci, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR); pci_rev = ssb_get_core_rev(bp); val = br32(bp, B44_SBINTVEC); val |= cores; bw32(bp, B44_SBINTVEC, val); val = br32(bp, SSB_PCI_TRANS_2); val |= SSB_PCI_PREF | SSB_PCI_BURST; bw32(bp, SSB_PCI_TRANS_2, val); pci_write_config_dword(bp->pci, SSB_BAR0_WIN, bar_orig); return pci_rev; }
static u32 ssb_pci_setup(struct b44 *bp, u32 cores) { u32 bar_orig, pci_rev, val; pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig); pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, ssb_get_addr(bp, SBID_REG_PCI, 0)); pci_rev = ssb_get_core_rev(bp); val = br32(bp, B44_SBINTVEC); val |= cores; bw32(bp, B44_SBINTVEC, val); val = br32(bp, SSB_PCI_TRANS_2); val |= SSB_PCI_PREF | SSB_PCI_BURST; bw32(bp, SSB_PCI_TRANS_2, val); pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig); return pci_rev; }