static int xilinx_spi_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
XilinxSPI *s = XILINX_SPI(dev);
int i;
DB_PRINT("\n");
s->spi = ssi_create_bus(dev, "spi");
sysbus_init_irq(sbd, &s->irq);
s->cs_lines = g_new0(qemu_irq, s->num_cs);
ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
for (i = 0; i < s->num_cs; ++i) {
sysbus_init_irq(sbd, &s->cs_lines[i]);
}
memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
"xilinx-spi", R_MAX * 4);
sysbus_init_mmio(sbd, &s->mmio);
s->irqline = -1;
fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
return 0;
}
static int xilinx_spi_init(SysBusDevice *dev)
{
int i;
XilinxSPI *s = FROM_SYSBUS(typeof(*s), dev);
DB_PRINT("\n");
s->spi = ssi_create_bus(&dev->qdev, "spi");
sysbus_init_irq(dev, &s->irq);
s->cs_lines = g_new(qemu_irq, s->num_cs);
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi);
for (i = 0; i < s->num_cs; ++i) {
sysbus_init_irq(dev, &s->cs_lines[i]);
}
memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
"xilinx-spi", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
s->irqline = -1;
fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
return 0;
}
static int pl022_init(SysBusDevice *dev)
{
pl022_state *s = FROM_SYSBUS(pl022_state, dev);
memory_region_init_io(&s->iomem, &pl022_ops, s, "pl022", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->ssi = ssi_create_bus(&dev->qdev, "ssi");
pl022_reset(s);
vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);
return 0;
}
static int pl022_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
PL022State *s = PL022(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
s->ssi = ssi_create_bus(dev, "ssi");
pl022_reset(s);
vmstate_register(dev, -1, &vmstate_pl022, s);
return 0;
}
static int pl022_init(SysBusDevice *dev)
{
pl022_state *s = FROM_SYSBUS(pl022_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(pl022_readfn,
pl022_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->ssi = ssi_create_bus(&dev->qdev, "ssi");
pl022_reset(s);
vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);
return 0;
}
static void imx_spi_realize(DeviceState *dev, Error **errp)
{
IMXSPIState *s = IMX_SPI(dev);
int i;
s->bus = ssi_create_bus(dev, "spi");
memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
TYPE_IMX_SPI, 0x1000);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);
for (i = 0; i < 4; ++i) {
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
}
s->burst_length = 0;
fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
}
