void core_fetch_STM_t::pre_fetch(void)
{
struct core_knobs_t * knobs = core->knobs;
int asid = core->current_thread->asid;
int i;
ZESTO_STAT(stat_add_sample(core->stat.fetch_stall, (int)stall_reason);)
/* In-order instruction commit. Individual uops cannot commit
until it is guaranteed that the entire Mop's worth of uops will
commit. */
void core_commit_atom_t::step(void)
{
struct core_knobs_t * knobs = core->knobs;
int commit_count = 0;
enum commit_stall_t stall_reason = CSTALL_NONE;
int branches_committed = 0;
/* This is just a deadlock watchdog. If something got messed up
in the pipeline and no forward progress is being made, this
code will eventually detect it and flush the pipeline in an
attempt to un-wedge the processor. If the processor then
deadlocks again without having first made any more forward
progress, we give up and kill the simulator. */
if((core->sim_cycle - core->exec->last_completed) > deadlock_threshold)
{
if(core->exec->last_completed_count == core->stat.eio_commit_insn)
{
char buf[256];
fflush(stdout);
snprintf(buf,sizeof(buf),"At cycle %lld, core[%d] has not completed a uop in %d cycles... definite deadlock",(long long)core->sim_cycle,core->current_thread->id,deadlock_threshold);
#ifdef ZTRACE
ztrace_print("DEADLOCK DETECTED: TERMINATING SIMULATION");
#endif
zesto_fatal(buf,(void)0);
}
else
{
struct Mop_t * Mop = ROB[ROB_head]->Mop;
#ifdef ZDEBUG
fprintf(stdout,"\n[%d][Core%d]COMMIT deadlock ",core->sim_cycle,core->current_thread->id,core->sim_cycle);
md_print_insn(Mop,stdout);
fprintf(stdout," MOP=%d last_Mop_seq= %d \n",Mop->oracle.seq,core->exec->last_Mop_seq);
#endif
fflush(stdout);
warn("At cycle %lld, core[%d] has not completed a uop in %d cycles... possible deadlock, flushing pipeline",(long long)core->sim_cycle,core->current_thread->id,deadlock_threshold);
#ifdef ZTRACE
ztrace_print("DEADLOCK DETECTED: FLUSHING PIPELINE");
#endif
/* flush the entire pipeline, correct path or not... */
core->oracle->complete_flush();
/*core->commit->*/recover();
core->exec->recover();
core->alloc->recover();
core->decode->recover();
core->fetch->recover(core->current_thread->regs.regs_NPC);
ZESTO_STAT(stat_add_sample(core->stat.commit_stall, (int)CSTALL_EMPTY);)
ZESTO_STAT(core->stat.commit_deadlock_flushes++;)
core->exec->last_completed = core->sim_cycle; /* so we don't do this again next cycle */
core->exec->last_completed_count = core->stat.eio_commit_insn;
}
void core_alloc_STM_t::step(void)
{
struct core_knobs_t * knobs = core->knobs;
enum alloc_stall_t stall_reason = ASTALL_NONE;
/*========================================================================*/
/*== Dispatch insts if ROB, RS, and LQ/SQ entries available (as needed) ==*/
if(core->decode->uop_available()) /* are there uops in the decode stage? */
{
/* if using drain flush: */
/* is the back-end still draining from a misprediction recovery? */
if(knobs->alloc.drain_flush && drain_in_progress)
{
if(!core->commit->ROB_empty())
{
stall_reason = ASTALL_DRAIN;
ZESTO_STAT(stat_add_sample(core->stat.alloc_stall, (int)stall_reason);)
return;
}
else
/* start simulation, program loaded, processor precise state initialized */
void
sim_main(void)
{
int i;
md_inst_t inst;
register md_addr_t addr;
register int is_write;
enum md_opcode op;
unsigned int flags;
enum md_fault_type fault;
fprintf(stderr, "sim: ** starting functional simulation **\n");
/* set up initial default next PC */
regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
/* check for DLite debugger entry condition */
if (dlite_check_break(regs.regs_PC, /* no access */0, /* addr */0, 0, 0))
dlite_main(regs.regs_PC - sizeof(md_inst_t), regs.regs_PC,
sim_num_insn, ®s, mem);
while (TRUE)
{
/* maintain $r0 semantics */
regs.regs_R[MD_REG_ZERO] = 0;
#ifdef TARGET_ALPHA
regs.regs_F.d[MD_REG_ZERO] = 0.0;
#endif /* TARGET_ALPHA */
/* get the next instruction to execute */
mem_access(mem, Read, regs.regs_PC, &inst, sizeof(md_inst_t));
if (verbose)
{
myfprintf(stderr, "%10n @ 0x%08p: ", sim_num_insn, regs.regs_PC);
md_print_insn(inst, regs.regs_PC, stderr);
fprintf(stderr, "\n");
/* fflush(stderr); */
}
/* keep an instruction count */
sim_num_insn++;
/* set default reference address and access mode */
addr = 0; is_write = FALSE;
/* set default fault - none */
fault = md_fault_none;
/* decode the instruction */
MD_SET_OPCODE(op, inst);
/* execute the instruction */
switch (op)
{
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
case OP: \
SYMCAT(OP,_IMPL); \
break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
case OP: \
panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT) \
{ fault = (FAULT); break; }
#include "machine.def"
default:
panic("attempted to execute a bogus opcode");
}
if (MD_OP_FLAGS(op) & F_MEM)
{
sim_num_refs++;
if (MD_OP_FLAGS(op) & F_STORE)
is_write = TRUE;
}
/*
* profile this instruction
*/
flags = MD_OP_FLAGS(op);
if (prof_ic)
{
enum inst_class_t ic;
/* compute instruction class */
if (flags & F_LOAD)
ic = ic_load;
else if (flags & F_STORE)
ic = ic_store;
else if (flags & F_UNCOND)
ic = ic_uncond;
else if (flags & F_COND)
ic = ic_cond;
else if (flags & F_ICOMP)
ic = ic_icomp;
else if (flags & F_FCOMP)
ic = ic_fcomp;
else if (flags & F_TRAP)
ic = ic_trap;
else
panic("instruction has no class");
/* update instruction class profile */
stat_add_sample(ic_prof, (int)ic);
}
if (prof_inst)
{
/* update instruction profile */
stat_add_sample(inst_prof, (int)op - /* skip NA */1);
}
if (prof_bc)
{
enum branch_class_t bc;
/* compute instruction class */
if (flags & F_CTRL)
{
if ((flags & (F_CALL|F_DIRJMP)) == (F_CALL|F_DIRJMP))
bc = bc_call_dir;
else if ((flags & (F_CALL|F_INDIRJMP)) == (F_CALL|F_INDIRJMP))
bc = bc_call_indir;
else if ((flags & (F_UNCOND|F_DIRJMP)) == (F_UNCOND|F_DIRJMP))
bc = bc_uncond_dir;
else if ((flags & (F_UNCOND|F_INDIRJMP))== (F_UNCOND|F_INDIRJMP))
bc = bc_uncond_indir;
else if ((flags & (F_COND|F_DIRJMP)) == (F_COND|F_DIRJMP))
bc = bc_cond_dir;
else if ((flags & (F_COND|F_INDIRJMP)) == (F_COND|F_INDIRJMP))
bc = bc_cond_indir;
else
panic("branch has no class");
/* update instruction class profile */
stat_add_sample(bc_prof, (int)bc);
}
}
if (prof_am)
{
enum md_amode_type am;
/* update addressing mode pre-probe FSM */
MD_AMODE_PREPROBE(op, fsm);
/* compute addressing mode */
if (flags & F_MEM)
{
/* compute addressing mode */
MD_AMODE_PROBE(am, op, fsm);
/* update the addressing mode profile */
stat_add_sample(am_prof, (int)am);
/* addressing mode pre-probe FSM, after all loads and stores */
MD_AMODE_POSTPROBE(fsm);
}
}
if (prof_seg)
{
if (flags & F_MEM)
{
/* update instruction profile */
stat_add_sample(seg_prof, (int)bind_to_seg(addr));
}
}
if (prof_tsyms)
{
int tindex;
/* attempt to bind inst address to a text segment symbol */
sym_bind_addr(regs.regs_PC, &tindex, /* !exact */FALSE, sdb_text);
if (tindex >= 0)
{
if (tindex > sym_ntextsyms)
panic("bogus text symbol index");
stat_add_sample(tsym_prof, tindex);
}
/* else, could not bind to a symbol */
}
if (prof_dsyms)
{
int dindex;
if (flags & F_MEM)
{
/* attempt to bind inst address to a text segment symbol */
sym_bind_addr(addr, &dindex, /* !exact */FALSE, sdb_data);
if (dindex >= 0)
{
if (dindex > sym_ndatasyms)
panic("bogus data symbol index");
stat_add_sample(dsym_prof, dindex);
}
/* else, could not bind to a symbol */
}
}
if (prof_taddr)
{
/* add regs_PC exec event to text address profile */
stat_add_sample(taddr_prof, regs.regs_PC);
}
/* update any stats tracked by PC */
for (i=0; i<pcstat_nelt; i++)
{
counter_t newval;
int delta;
/* check if any tracked stats changed */
newval = STATVAL(pcstat_stats[i]);
delta = newval - pcstat_lastvals[i];
if (delta != 0)
{
stat_add_samples(pcstat_sdists[i], regs.regs_PC, delta);
pcstat_lastvals[i] = newval;
}
}
/* check for DLite debugger entry condition */
if (dlite_check_break(regs.regs_NPC,
is_write ? ACCESS_WRITE : ACCESS_READ,
addr, sim_num_insn, sim_num_insn))
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
/* go to the next instruction */
regs.regs_PC = regs.regs_NPC;
regs.regs_NPC += sizeof(md_inst_t);
/* finish early? */
if (max_insts && sim_num_insn >= max_insts)
return;
}
}
void
main(void)
{
struct stat_sdb_t *sdb;
struct stat_stat_t *stat, *stat1, *stat2, *stat3, *stat4, *stat5;
int an_int;
unsigned int a_uint;
float a_float;
double a_double;
static char *my_imap[8] = {
"foo", "bar", "uxxe", "blah", "gaga", "dada", "mama", "googoo"
};
/* make stats database */
sdb = stat_new();
/* register stat variables */
stat_reg_int(sdb, "stat.an_int", "An integer stat variable.",
&an_int, 1, NULL);
stat_reg_uint(sdb, "stat.a_uint", "An unsigned integer stat variable.",
&a_uint, 2, "%u (unsigned)");
stat_reg_float(sdb, "stat.a_float", "A float stat variable.",
&a_float, 3, NULL);
stat_reg_double(sdb, "stat.a_double", "A double stat variable.",
&a_double, 4, NULL);
stat_reg_formula(sdb, "stat.a_formula", "A double stat formula.",
"stat.a_float / stat.a_uint", NULL);
stat_reg_formula(sdb, "stat.a_formula1", "A double stat formula #1.",
"2 * (stat.a_formula / (1.5 * stat.an_int))", NULL);
stat_reg_formula(sdb, "stat.a_bad_formula", "A double stat formula w/error.",
"stat.a_float / (stat.a_uint - 2)", NULL);
stat = stat_reg_dist(sdb, "stat.a_dist", "An array distribution.",
0, 8, 1, PF_ALL, NULL, NULL, NULL);
stat1 = stat_reg_dist(sdb, "stat.a_dist1", "An array distribution #1.",
0, 8, 4, PF_ALL, NULL, NULL, NULL);
stat2 = stat_reg_dist(sdb, "stat.a_dist2", "An array distribution #2.",
0, 8, 1, (PF_PDF|PF_CDF), NULL, NULL, NULL);
stat3 = stat_reg_dist(sdb, "stat.a_dist3", "An array distribution #3.",
0, 8, 1, PF_ALL, NULL, my_imap, NULL);
stat4 = stat_reg_sdist(sdb, "stat.a_sdist", "A sparse array distribution.",
0, PF_ALL, NULL, NULL);
stat5 = stat_reg_sdist(sdb, "stat.a_sdist1",
"A sparse array distribution #1.",
0, PF_ALL, "0x%08lx %10lu %6.2f %6.2f",
NULL);
/* print initial stats */
fprintf(stdout, "** Initial stats...\n");
stat_print_stats(sdb, stdout);
/* adjust stats */
an_int++;
a_uint++;
a_float *= 2;
a_double *= 4;
stat_add_sample(stat, 8);
stat_add_sample(stat, 8);
stat_add_sample(stat, 1);
stat_add_sample(stat, 3);
stat_add_sample(stat, 4);
stat_add_sample(stat, 4);
stat_add_sample(stat, 7);
stat_add_sample(stat1, 32);
stat_add_sample(stat1, 32);
stat_add_sample(stat1, 1);
stat_add_sample(stat1, 12);
stat_add_sample(stat1, 17);
stat_add_sample(stat1, 18);
stat_add_sample(stat1, 30);
stat_add_sample(stat2, 8);
stat_add_sample(stat2, 8);
stat_add_sample(stat2, 1);
stat_add_sample(stat2, 3);
stat_add_sample(stat2, 4);
stat_add_sample(stat2, 4);
stat_add_sample(stat2, 7);
stat_add_sample(stat3, 8);
stat_add_sample(stat3, 8);
stat_add_sample(stat3, 1);
stat_add_sample(stat3, 3);
stat_add_sample(stat3, 4);
stat_add_sample(stat3, 4);
stat_add_sample(stat3, 7);
stat_add_sample(stat4, 800);
stat_add_sample(stat4, 800);
stat_add_sample(stat4, 1123);
stat_add_sample(stat4, 3332);
stat_add_sample(stat4, 4000);
stat_add_samples(stat4, 4001, 18);
stat_add_sample(stat4, 7);
stat_add_sample(stat5, 800);
stat_add_sample(stat5, 800);
stat_add_sample(stat5, 1123);
stat_add_sample(stat5, 3332);
stat_add_sample(stat5, 4000);
stat_add_samples(stat5, 4001, 18);
stat_add_sample(stat5, 7);
/* print final stats */
fprintf(stdout, "** Final stats...\n");
stat_print_stats(sdb, stdout);
/* all done */
stat_delete(sdb);
exit(0);
}
