/**Function************************************************************* Synopsis [Deletes the manager.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void ABC_ReleaseManager( ABC_Manager mng ) { CSAT_Target_ResultT * p_res = ABC_Get_Target_Result( mng,0 ); ABC_TargetResFree(p_res); if ( mng->tNode2Name ) stmm_free_table( mng->tNode2Name ); if ( mng->tName2Node ) stmm_free_table( mng->tName2Node ); if ( mng->pMmNames ) Mem_FlexStop( mng->pMmNames, 0 ); if ( mng->pNtk ) Abc_NtkDelete( mng->pNtk ); if ( mng->pTarget ) Abc_NtkDelete( mng->pTarget ); if ( mng->vNodes ) Vec_PtrFree( mng->vNodes ); if ( mng->vValues ) Vec_IntFree( mng->vValues ); ABC_FREE( mng->pDumpFileName ); ABC_FREE( mng ); Abc_Stop(); }
/**Function************************************************************* Synopsis [Stops the manager.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Super2_ManStop( Super2_Man_t * pMan ) { Extra_MmFixedStop( pMan->pMem ); stmm_free_table( pMan->tTable ); ABC_FREE( pMan ); }
/**Function************************************************************* Synopsis [Transfers names from one netlist to the other.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Abc_NtkDress( Abc_Ntk_t * pNtkLogic, char * pFileName, int fVerbose ) { Abc_Ntk_t * pNtkOrig, * pNtkLogicOrig; Abc_Ntk_t * pMiter, * pMiterFraig; stmm_table * tMapping; assert( Abc_NtkIsLogic(pNtkLogic) ); // get the original netlist pNtkOrig = Io_ReadNetlist( pFileName, Io_ReadFileType(pFileName), 1 ); if ( pNtkOrig == NULL ) return; assert( Abc_NtkIsNetlist(pNtkOrig) ); Abc_NtkCleanCopy(pNtkLogic); Abc_NtkCleanCopy(pNtkOrig); // convert it into the logic network pNtkLogicOrig = Abc_NtkToLogic( pNtkOrig ); // check that the networks have the same PIs/POs/latches if ( !Abc_NtkCompareSignals( pNtkLogic, pNtkLogicOrig, 1, 1 ) ) { Abc_NtkDelete( pNtkOrig ); Abc_NtkDelete( pNtkLogicOrig ); return; } // convert the current logic network into an AIG pMiter = Abc_NtkStrash( pNtkLogic, 1, 0, 0 ); // convert it into the AIG and make the netlist point to the AIG Abc_NtkAppend( pMiter, pNtkLogicOrig, 1 ); Abc_NtkTransferCopy( pNtkOrig ); Abc_NtkDelete( pNtkLogicOrig ); if ( fVerbose ) { printf( "After mitering:\n" ); printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) ); printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) ); } // fraig the miter (miter nodes point to the fraiged miter) pMiterFraig = Abc_NtkIvyFraig( pMiter, 100, 1, 0, 1, 0 ); // make netlists point to the fraiged miter Abc_NtkTransferCopy( pNtkLogic ); Abc_NtkTransferCopy( pNtkOrig ); Abc_NtkDelete( pMiter ); if ( fVerbose ) { printf( "After fraiging:\n" ); printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) ); printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) ); } // derive mapping from the fraiged nodes into their prototype nodes in the original netlist tMapping = Abc_NtkDressDeriveMapping( pNtkOrig ); // transfer the names to the new netlist Abc_NtkDressTransferNames( pNtkLogic, tMapping, fVerbose ); // clean up stmm_free_table( tMapping ); Abc_NtkDelete( pMiterFraig ); Abc_NtkDelete( pNtkOrig ); }
/**Function************************************************************* Synopsis [Implements the given retiming on the sequential AIG.] Description [Returns 0 of initial state computation fails.] SideEffects [] SeeAlso [] ***********************************************************************/ int Seq_NtkImplementRetimingBackward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves, int fVerbose ) { Seq_RetEdge_t RetEdge; stmm_table * tTable; stmm_generator * gen; Vec_Int_t * vValues; Abc_Ntk_t * pNtkProb, * pNtkMiter, * pNtkCnf; Abc_Obj_t * pNode, * pNodeNew; int * pModel, RetValue, i, clk; // return if the retiming is trivial if ( Vec_PtrSize(vMoves) == 0 ) return 1; // create the network for the initial state computation // start the table and the array of PO values pNtkProb = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_SOP, 1 ); tTable = stmm_init_table( stmm_numcmp, stmm_numhash ); vValues = Vec_IntAlloc( 100 ); // perform the backward moves and build the network for initial state computation RetValue = 0; Vec_PtrForEachEntry( vMoves, pNode, i ) RetValue |= Abc_ObjRetimeBackward( pNode, pNtkProb, tTable, vValues ); // add the PIs corresponding to the white spots stmm_foreach_item( tTable, gen, (char **)&RetEdge, (char **)&pNodeNew ) Abc_ObjAddFanin( pNodeNew, Abc_NtkCreatePi(pNtkProb) ); // add the PI/PO names Abc_NtkAddDummyPiNames( pNtkProb ); Abc_NtkAddDummyPoNames( pNtkProb ); Abc_NtkAddDummyAssertNames( pNtkProb ); // make sure everything is okay with the network structure if ( !Abc_NtkDoCheck( pNtkProb ) ) { printf( "Seq_NtkImplementRetimingBackward: The internal network check has failed.\n" ); Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL ); Abc_NtkDelete( pNtkProb ); stmm_free_table( tTable ); Vec_IntFree( vValues ); return 0; } // check if conflict is found if ( RetValue ) { printf( "Seq_NtkImplementRetimingBackward: A top level conflict is detected. DC latch values are used.\n" ); Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL ); Abc_NtkDelete( pNtkProb ); stmm_free_table( tTable ); Vec_IntFree( vValues ); return 0; } // get the miter cone pNtkMiter = Abc_NtkCreateTarget( pNtkProb, pNtkProb->vCos, vValues ); Abc_NtkDelete( pNtkProb ); Vec_IntFree( vValues ); if ( fVerbose ) printf( "The number of ANDs in the AIG = %5d.\n", Abc_NtkNodeNum(pNtkMiter) ); // transform the miter into a logic network for efficient CNF construction // pNtkCnf = Abc_Ntk_Renode( pNtkMiter, 0, 100, 1, 0, 0 ); // Abc_NtkDelete( pNtkMiter ); pNtkCnf = pNtkMiter; // solve the miter clk = clock(); // RetValue = Abc_NtkMiterSat_OldAndRusty( pNtkCnf, 30, 0 ); RetValue = Abc_NtkMiterSat( pNtkCnf, (sint64)500000, (sint64)50000000, 0, 0, NULL, NULL ); if ( fVerbose ) if ( clock() - clk > 100 ) { PRT( "SAT solving time", clock() - clk ); } pModel = pNtkCnf->pModel; pNtkCnf->pModel = NULL; Abc_NtkDelete( pNtkCnf ); // analyze the result if ( RetValue == -1 || RetValue == 1 ) { Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL ); if ( RetValue == 1 ) printf( "Seq_NtkImplementRetimingBackward: The problem is unsatisfiable. DC latch values are used.\n" ); else printf( "Seq_NtkImplementRetimingBackward: The SAT problem timed out. DC latch values are used.\n" ); stmm_free_table( tTable ); return 0; } // set the values of the latches Abc_NtkRetimeSetInitialValues( pNtk, tTable, pModel ); stmm_free_table( tTable ); free( pModel ); return 1; }