void Check_CD_Command(void)
{
#ifdef DEBUG_CD
fprintf(debug_SCD_file, "CHECK CD COMMAND\n");
#endif
// Check CDD
if (CDD_Complete)
{
CDD_Complete = 0;
#ifdef DEBUG_CD
fprintf(debug_SCD_file, "CDD exporting status\n");
fprintf(debug_SCD_file, "Status=%.4X, Minute=%.4X, Seconde=%.4X, Frame=%.4X, Ext=%.4X\n", CDD.Status, CDD.Minute, CDD.Seconde, CDD.Frame, CDD.Ext);
#endif
CDD_Export_Status();
if (Int_Mask_S68K & 0x10) sub68k_interrupt(4, -1);
}
// Check CDC
if (SCD.Status_CDC & 1) // CDC is reading data ...
{
#ifdef DEBUG_CD
fprintf(debug_SCD_file, "Send a read command\n");
#endif
// DATA ?
if (SCD.TOC.Tracks[SCD.Cur_Track - SCD.TOC.First_Track].Type) CDD.Control |= 0x0100;
else CDD.Control &= ~0x0100; // AUDIO
if (File_Add_Delay == 0)
{
if (CD_Load_System == CDROM_) ASPI_Read_One_LBA_CDC();
else FILE_Read_One_LBA_CDC();
}
else File_Add_Delay--;
}
if (SCD.Status_CDD == FAST_FOW)
{
SCD.Cur_LBA += 10;
CDC_Update_Header();
}
else if (SCD.Status_CDD == FAST_REV)
{
SCD.Cur_LBA -= 10;
if (SCD.Cur_LBA < -150) SCD.Cur_LBA = -150;
CDC_Update_Header();
}
}
void Update_CDC_TRansfert(void)
{
unsigned int dep, length, add_dest;
uint8_t *dest;
if ((SCD.Status_CDC & 0x08) == 0)
return;
switch (CDC.RS0 & 0x0700)
{
case 0x0200: // MAIN CPU
case 0x0300: // SUB CPU
// Data ready in host port
CDC.RS0 |= 0x4000;
return;
break;
case 0x0400: // PCM RAM
dest = (unsigned char *) Ram_PCM;
dep = ((CDC.DMA_Adr & 0x03FF) << 2) + PCM_Chip.Bank;
add_dest = 2;
break;
case 0x0500: // PRG RAM
dest = &Ram_Prg.u8[0];
dep = (CDC.DMA_Adr & 0xFFFF) << 3;
add_dest = 2;
LOG_MSG(lc89510, LOG_MSG_LEVEL_DEBUG1,
"DMA transfert PRG RAM : adr = %.8X", dep);
break;
case 0x0700: // WORD RAM
if (Ram_Word_State >= 2)
{
dest = &Ram_Word_1M.u8[0];
add_dest = 2;
if (Ram_Word_State & 1)
dep = ((CDC.DMA_Adr & 0x3FFF) << 3);
else
dep = ((CDC.DMA_Adr & 0x3FFF) << 3) + 0x20000;
}
else
{
dest = &Ram_Word_2M.u8[0];
dep = ((CDC.DMA_Adr & 0x7FFF) << 3);
add_dest = 2;
}
break;
default:
return;
}
if (CDC.DBC.N <= (CDC_DMA_SPEED * 2))
{
length = (CDC.DBC.N + 1) >> 1;
SCD.Status_CDC &= ~0x08; // Last transfert
CDC.RS0 |= 0x8000; // End data transfert
CDC.RS0 &= ~0x4000; // no more data ready
CDC.IFSTAT |= 0x08; // No more data transfert in progress
// DTEIEN = Data Trasnfert End Interrupt Enable ?
if (CDC.IFCTRL & 0x40)
{
CDC.IFSTAT &= ~0x40;
if (Int_Mask_S68K & 0x20)
sub68k_interrupt (5, -1);
LOG_MSG(lc89510, LOG_MSG_LEVEL_DEBUG1,
"CDC - DTE interrupt");
}
}
