int sii9022xInitChip()
{
int rcc,retries = 10;
swI2CInit(DEFAULT_I2C_SCL, DEFAULT_I2C_SDA);
/* enter TPI mode */
i2cWriteReg(SII9022A_I2C_ADDRESS,0xc7,0);
do{
msleep(1);
rcc = i2cReadReg(SII9022A_I2C_ADDRESS,0x1B);
}while((rcc != SII9022_DEVICE_ID) && retries--);
if(rcc != SII9022_DEVICE_ID){
printk("cannot detect sii9022a chip:rcc=%x\n",rcc);
return -1;
}
return 0;
}
static int hw_tst_edid(struct ufb_data * ufb,int scl,int sda)
{
#define PATTERN_TST_CNT 3
int i;
uint8_t head[8];
static const uint8_t pattern[8] = {0,255,255,255,255,255,255,0};
swI2CInit((void *)ufb,scl,sda);
i = 0;
while(i<PATTERN_TST_CNT){
head[i] = swI2CReadReg(ufb,0xa0,i);
//printk("head[%d]=%d\n",i,head[i]);
i++;
}
i=0;
while(i<PATTERN_TST_CNT){
if(head[i]!=pattern[i])
return 0;
i++;
}
return 1;
#undef PATTERN_TST_CNT
}
/*
* sii164InitChip
* This function initialize and detect the DVI controller chip.
*
* Input:
* edgeSelect - Edge Select:
* 0 = Input data is falling edge latched (falling edge
* latched first in dual edge mode)
* 1 = Input data is rising edge latched (rising edge
* latched first in dual edge mode)
* busSelect - Input Bus Select:
* 0 = Input data bus is 12-bits wide
* 1 = Input data bus is 24-bits wide
* dualEdgeClkSelect - Dual Edge Clock Select
* 0 = Input data is single edge latched
* 1 = Input data is dual edge latched
* hsyncEnable - Horizontal Sync Enable:
* 0 = HSYNC input is transmitted as fixed LOW
* 1 = HSYNC input is transmitted as is
* vsyncEnable - Vertical Sync Enable:
* 0 = VSYNC input is transmitted as fixed LOW
* 1 = VSYNC input is transmitted as is
* deskewEnable - De-skewing Enable:
* 0 = De-skew disabled
* 1 = De-skew enabled
* deskewSetting - De-skewing Setting (increment of 260psec)
* 0 = 1 step --> minimum setup / maximum hold
* 1 = 2 step
* 2 = 3 step
* 3 = 4 step
* 4 = 5 step
* 5 = 6 step
* 6 = 7 step
* 7 = 8 step --> maximum setup / minimum hold
* continuousSyncEnable- SYNC Continuous:
* 0 = Disable
* 1 = Enable
* pllFilterEnable - PLL Filter Enable
* 0 = Disable PLL Filter
* 1 = Enable PLL Filter
* pllFilterValue - PLL Filter characteristics:
* 0~7 (recommended value is 4)
*
* Output:
* 0 - Success
* -1 - Fail.
*/
long sii164InitChip(
unsigned char edgeSelect,
unsigned char busSelect,
unsigned char dualEdgeClkSelect,
unsigned char hsyncEnable,
unsigned char vsyncEnable,
unsigned char deskewEnable,
unsigned char deskewSetting,
unsigned char continuousSyncEnable,
unsigned char pllFilterEnable,
unsigned char pllFilterValue
)
{
unsigned char config;
/* Initialize the i2c bus */
#ifdef USE_HW_I2C
/* Use fast mode. */
hwI2CInit(1);
#else
swI2CInit(DEFAULT_I2C_SCL, DEFAULT_I2C_SDA);
#endif
/* Check if SII164 Chip exists */
if ((sii164GetVendorID() == SII164_VENDOR_ID) && (sii164GetDeviceID() == SII164_DEVICE_ID))
{
/*
* Initialize SII164 controller chip.
*/
/* Select the edge */
if (edgeSelect == 0)
config = SII164_CONFIGURATION_LATCH_FALLING;
else
config = SII164_CONFIGURATION_LATCH_RISING;
/* Select bus wide */
if (busSelect == 0)
config |= SII164_CONFIGURATION_BUS_12BITS;
else
config |= SII164_CONFIGURATION_BUS_24BITS;
/* Select Dual/Single Edge Clock */
if (dualEdgeClkSelect == 0)
config |= SII164_CONFIGURATION_CLOCK_SINGLE;
else
config |= SII164_CONFIGURATION_CLOCK_DUAL;
/* Select HSync Enable */
if (hsyncEnable == 0)
config |= SII164_CONFIGURATION_HSYNC_FORCE_LOW;
else
config |= SII164_CONFIGURATION_HSYNC_AS_IS;
/* Select VSync Enable */
if (vsyncEnable == 0)
config |= SII164_CONFIGURATION_VSYNC_FORCE_LOW;
else
config |= SII164_CONFIGURATION_VSYNC_AS_IS;
i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
/* De-skew enabled with default 111b value.
This will fix some artifacts problem in some mode on board 2.2.
Somehow this fix does not affect board 2.1.
*/
if (deskewEnable == 0)
config = SII164_DESKEW_DISABLE;
else
config = SII164_DESKEW_ENABLE;
switch (deskewSetting)
{
case 0:
config |= SII164_DESKEW_1_STEP;
break;
case 1:
config |= SII164_DESKEW_2_STEP;
break;
case 2:
config |= SII164_DESKEW_3_STEP;
break;
case 3:
config |= SII164_DESKEW_4_STEP;
break;
case 4:
config |= SII164_DESKEW_5_STEP;
break;
case 5:
config |= SII164_DESKEW_6_STEP;
break;
case 6:
config |= SII164_DESKEW_7_STEP;
break;
case 7:
config |= SII164_DESKEW_8_STEP;
break;
}
i2cWriteReg(SII164_I2C_ADDRESS, SII164_DESKEW, config);
/* Enable/Disable Continuous Sync. */
if (continuousSyncEnable == 0)
config = SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE;
else
config = SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE;
/* Enable/Disable PLL Filter */
if (pllFilterEnable == 0)
config |= SII164_PLL_FILTER_DISABLE;
else
config |= SII164_PLL_FILTER_ENABLE;
/* Set the PLL Filter value */
config |= ((pllFilterValue & 0x07) << 1);
i2cWriteReg(SII164_I2C_ADDRESS, SII164_PLL, config);
/* Recover from Power Down and enable output. */
config = i2cReadReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION);
config |= SII164_CONFIGURATION_POWER_NORMAL;
i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
return 0;
}
/* Return -1 if initialization fails. */
return (-1);
}
