#define LMI_RET_GPIO_PORT 4
#define LMI_RET_GPIO_PIN 4
#define LMI_RETENTION_PIN stm_gpio(LMI_RET_GPIO_PORT, LMI_RET_GPIO_PIN)
#define SYSCONF_SYSTEM(x) (MPE41_SYSTEM_SYSCONF_BASE + \
((x) - 600) * 0x4)
#define SYSCONF_DDR0_PWR_DWN SYSCONF_SYSTEM(608)
#define SYSCONF_DDR0_PWR_ACK SYSCONF_SYSTEM(670)
#define SYSCONF_DDR1_PWR_DWN SYSCONF_SYSTEM(613)
#define SYSCONF_DDR1_PWR_ACK SYSCONF_SYSTEM(672)
static const unsigned long __fli7610_hom_ddr_0[] = {
OR32(MPE41_DDR0_PCTL_BASE + DDR_DTU_CFG, DDR_DTU_CFG_ENABLE),
synopsys_ddr32_in_hom(MPE41_DDR0_PCTL_BASE),
};
static const unsigned long __fli7610_hom_ddr_1[] = {
OR32(MPE41_DDR1_PCTL_BASE + DDR_DTU_CFG, DDR_DTU_CFG_ENABLE),
synopsys_ddr32_in_hom(MPE41_DDR1_PCTL_BASE),
};
static const unsigned long __fli7610_hom_lmi_retention[] = {
/*
* Enable retention mode gpio
*/
POKE32(SBC_GPIO_PORT(LMI_RET_GPIO_PORT) + STM_GPIO_REG_CLR_POUT,
1 << LMI_RET_GPIO_PIN),
};
#define PCLK 30000000
#define BAUDRATE_VAL_M1(bps) \
((((bps * (1 << 14)) + (1 << 13)) / (PCLK / (1 << 6))))
#define SBC_MBX 0xfe4b4000
#define SBC_MBX_WRITE_STATUS(x) (SBC_MBX + 0x4 + 0x4 * (x))
#define SBC_GPIO_PORT(_nr) (0xfe610000 + (_nr) * 0x1000)
#define LMI_RET_GPIO_PORT 3
#define LMI_RET_GPIO_PIN 3
#define LMI_RETENTION_PIN stm_gpio(LMI_RET_GPIO_PORT, LMI_RET_GPIO_PIN)
static unsigned long stxh205_hom_table[] __cacheline_aligned = {
synopsys_ddr32_in_hom(DDR3SS_REG),
/*
* Enable retention mode gpio
*
*/
POKE32(SBC_GPIO_PORT(LMI_RET_GPIO_PORT) + STM_GPIO_REG_CLR_POUT,
1 << LMI_RET_GPIO_PIN),
/*
* Send message 'ENTER_PASSIVE' (0x5)
*/
POKE32(SBC_MBX_WRITE_STATUS(0), 0x5),
/* END. */
END_MARKER,