/** \brief Write a buffer to non-volatile RAM
*
* This routine writes \c count Bytes to the NVRAM destination pointed
* to by \c dst from the source buffer pointed to by \c src.
*
* \param dst the write destination in the NVRAM address space
* \param src the source buffer in program data memory space
* \param count the number of Bytes to write
*
* \return Nothing.
*/
void nvram_write(nvram_addr_t dst, const void *src, size_t count)
{
#if XMEGA
nvm_wait_until_ready();
nvm_user_sig_write_buffer((flash_addr_t)(dst + SENSOR_NVM_OFFSET),
src, count, true);
/* check for blank, erase if needed */
#elif UC3
const bool erase_page = true;
volatile void *const flash_addr
= (volatile void *)(dst + SENSOR_NVM_BASE + SENSOR_NVM_OFFSET);
sysclk_enable_pbb_module(SYSCLK_FLASH_REGS);
(void)flash_memcpy(flash_addr, src, count, erase_page);
sysclk_disable_pbb_module(SYSCLK_FLASH_REGS);
#endif
}
/**
* \brief Disable the USB generic clock
*/
void sysclk_disable_usb(void)
{
genclk_disable(AVR32_PM_GCLK_USBB);
sysclk_disable_hsb_module(SYSCLK_USBB_DATA);
sysclk_disable_pbb_module(SYSCLK_USBB_REGS);
}
/**
* \brief Disable a peripheral's clock from its base address.
*
* Disables the clock to a peripheral, given its base address. If the peripheral
* has an associated clock on the HSB bus, this will be disabled also.
*
* \param module Pointer to the module's base address.
*/
void sysclk_disable_peripheral_clock(const volatile void *module)
{
switch ((uintptr_t)module) {
#if !SAM4LS
case AESA_ADDR:
sysclk_disable_hsb_module(SYSCLK_AESA_HSB);
break;
#endif
case IISC_ADDR:
sysclk_disable_pba_module(SYSCLK_IISC);
break;
case SPI_ADDR:
sysclk_disable_pba_module(SYSCLK_SPI);
break;
case TC0_ADDR:
sysclk_disable_pba_module(SYSCLK_TC0);
break;
case TC1_ADDR:
sysclk_disable_pba_module(SYSCLK_TC1);
break;
case TWIM0_ADDR:
sysclk_disable_pba_module(SYSCLK_TWIM0);
break;
case TWIS0_ADDR:
sysclk_disable_pba_module(SYSCLK_TWIS0);
break;
case TWIM1_ADDR:
sysclk_disable_pba_module(SYSCLK_TWIM1);
break;
case TWIS1_ADDR:
sysclk_disable_pba_module(SYSCLK_TWIS1);
break;
case USART0_ADDR:
sysclk_disable_pba_module(SYSCLK_USART0);
break;
case USART1_ADDR:
sysclk_disable_pba_module(SYSCLK_USART1);
break;
case USART2_ADDR:
sysclk_disable_pba_module(SYSCLK_USART2);
break;
case USART3_ADDR:
sysclk_disable_pba_module(SYSCLK_USART3);
break;
case ADCIFE_ADDR:
sysclk_disable_pba_module(SYSCLK_ADCIFE);
break;
case DACC_ADDR:
sysclk_disable_pba_module(SYSCLK_DACC);
break;
case ACIFC_ADDR:
sysclk_disable_pba_module(SYSCLK_ACIFC);
break;
case GLOC_ADDR:
sysclk_disable_pba_module(SYSCLK_GLOC);
break;
case ABDACB_ADDR:
sysclk_disable_pba_module(SYSCLK_ABDACB);
break;
case TRNG_ADDR:
sysclk_disable_pba_module(SYSCLK_TRNG);
break;
case PARC_ADDR:
sysclk_disable_pba_module(SYSCLK_PARC);
break;
case CATB_ADDR:
sysclk_disable_pba_module(SYSCLK_CATB);
break;
case TWIM2_ADDR:
sysclk_disable_pba_module(SYSCLK_TWIM2);
break;
case TWIM3_ADDR:
sysclk_disable_pba_module(SYSCLK_TWIM3);
break;
#if !SAM4LS
case LCDCA_ADDR:
sysclk_disable_pba_module(SYSCLK_LCDCA);
break;
#endif
case HFLASHC_ADDR:
sysclk_disable_pbb_module(SYSCLK_HFLASHC_REGS);
break;
case HCACHE_ADDR:
sysclk_disable_hsb_module(SYSCLK_HRAMC1_DATA);
sysclk_disable_pbb_module(SYSCLK_HRAMC1_REGS);
break;
case HMATRIX_ADDR:
sysclk_disable_pbb_module(SYSCLK_HMATRIX);
break;
case PDCA_ADDR:
sysclk_disable_hsb_module(SYSCLK_PDCA_HSB);
sysclk_disable_pbb_module(SYSCLK_PDCA_PB);
break;
case CRCCU_ADDR:
sysclk_disable_hsb_module(SYSCLK_CRCCU_DATA);
sysclk_disable_pbb_module(SYSCLK_CRCCU_REGS);
break;
case USBC_ADDR:
sysclk_disable_hsb_module(SYSCLK_USBC_DATA);
sysclk_disable_pbb_module(SYSCLK_USBC_REGS);
break;
case PEVC_ADDR:
sysclk_disable_pbb_module(SYSCLK_PEVC);
break;
case PM_ADDR:
sysclk_disable_pbc_module(SYSCLK_PM);
break;
case CHIPID_ADDR:
sysclk_disable_pbc_module(SYSCLK_CHIPID);
break;
case SCIF_ADDR:
sysclk_disable_pbc_module(SYSCLK_SCIF);
break;
case FREQM_ADDR:
sysclk_disable_pbc_module(SYSCLK_FREQM);
break;
case GPIO_ADDR:
sysclk_disable_pbc_module(SYSCLK_GPIO);
break;
case BPM_ADDR:
sysclk_disable_pbd_module(SYSCLK_BPM);
break;
case BSCIF_ADDR:
sysclk_disable_pbd_module(SYSCLK_BSCIF);
break;
case AST_ADDR:
sysclk_disable_pbd_module(SYSCLK_AST);
break;
case WDT_ADDR:
sysclk_disable_pbd_module(SYSCLK_WDT);
break;
case EIC_ADDR:
sysclk_disable_pbd_module(SYSCLK_EIC);
break;
case PICOUART_ADDR:
sysclk_disable_pbd_module(SYSCLK_PICOUART);
break;
default:
Assert(false);
return;
}
// Disable PBA divided clock if possible.
#define PBADIV_CLKSRC_MASK ((1 << SYSCLK_TC0) | \
(1 << SYSCLK_TC1) | \
(1 << SYSCLK_USART0) | \
(1 << SYSCLK_USART1) | \
(1 << SYSCLK_USART2) | \
(1 << SYSCLK_USART3))
if ((PM->PM_PBAMASK & PBADIV_CLKSRC_MASK) == 0) {
sysclk_disable_pba_divmask(PBA_DIVMASK_Msk);
}
}
