/*! \brief Main function. Execution starts here. */ int main(void) { irq_initialize_vectors(); cpu_irq_enable(); // Initialize the sleep manager sleepmgr_init(); sysclk_init(); board_init(); ui_init(); ui_powerdown(); #if UC3A3 // Init Hmatrix bus sysclk_enable_pbb_module(SYSCLK_HMATRIX); init_hmatrix(); #endif #if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE) at45dbx_init(); #endif #if ((defined SD_MMC_MCI_0_MEM) && (SD_MMC_MCI_0_MEM == ENABLE)) \ || ((defined SD_MMC_MCI_1_MEM) && (SD_MMC_MCI_1_MEM == ENABLE)) // Initialize SD/MMC with MCI PB clock. sysclk_enable_pbb_module(SYSCLK_MCI); sysclk_enable_hsb_module(SYSCLK_DMACA); sd_mmc_mci_resources_init(); #endif // Start USB stack to authorize VBus monitoring udc_start(); if (!udc_include_vbus_monitoring()) { // VBUS monitoring is not available on this product // thereby VBUS has to be considered as present main_vbus_action(true); } // The main loop manages only the power mode // because the USB management is done by interrupt while (true) { sleepmgr_enter_sleep(); if (main_b_msc_enable) { udi_msc_process_trans(); } } }
/** * \brief Enable the USB generic clock * * \pre The USB generic clock must be configured to 48MHz. * CONFIG_USBCLK_SOURCE and CONFIG_USBCLK_DIV must be defined with proper * configuration. The selected clock source must also be configured. */ void sysclk_enable_usb(void) { // Note: the SYSCLK_PBB_BRIDGE clock is enabled by // sysclk_enable_pbb_module(). sysclk_enable_pbb_module(SYSCLK_USBC_REGS); sysclk_enable_hsb_module(SYSCLK_USBC_DATA); genclk_enable_config(AVR32_USBC_GCLK_NUM, CONFIG_USBCLK_SOURCE, CONFIG_USBCLK_DIV); }
/** \brief Write a buffer to non-volatile RAM * * This routine writes \c count Bytes to the NVRAM destination pointed * to by \c dst from the source buffer pointed to by \c src. * * \param dst the write destination in the NVRAM address space * \param src the source buffer in program data memory space * \param count the number of Bytes to write * * \return Nothing. */ void nvram_write(nvram_addr_t dst, const void *src, size_t count) { #if XMEGA nvm_wait_until_ready(); nvm_user_sig_write_buffer((flash_addr_t)(dst + SENSOR_NVM_OFFSET), src, count, true); /* check for blank, erase if needed */ #elif UC3 const bool erase_page = true; volatile void *const flash_addr = (volatile void *)(dst + SENSOR_NVM_BASE + SENSOR_NVM_OFFSET); sysclk_enable_pbb_module(SYSCLK_FLASH_REGS); (void)flash_memcpy(flash_addr, src, count, erase_page); sysclk_disable_pbb_module(SYSCLK_FLASH_REGS); #endif }
// top-level peripheral init static void init_avr32(void) { volatile avr32_tc_t *tc = APP_TC; // clocks // setup clocks sysclk_init(); // not sure why but when need to explictly enable clock for static mem ctlr sysclk_enable_pbb_module(SYSCLK_SMC_REGS); flashc_set_bus_freq(FCPU_HZ); // need this for high-speed operation flashc_set_wait_state(1); /// interrupts // print_dbg("\r\n irq_initialize_vectors() "); irq_initialize_vectors(); // disable all interrupts for now // print_dbg("\r\n cpu_irq_disable() "); cpu_irq_disable(); // serial usb print_dbg("\r\n init_ftdi_usart() "); init_ftdi_usart(); // external sram print_dbg("\r\n smc_init(FHSB_HZ) "); smc_init(FHSB_HZ); // initialize spi1: OLED, ADC, SD/MMC print_dbg("\r\n init_spi1() "); init_spi1(); // initialize PDCA controller print_dbg("\r\n init_local_pdca() "); init_local_pdca(); // initialize blackfin resources print_dbg("\r\n init_bfin_resources() "); init_bfin_resources(); // initialize application timer print_dbg("\r\n init_tc(tc) "); init_tc(tc); // initialize other GPIO print_dbg("\r\n init_gpio() "); init_gpio(); // register interrupts print_dbg("\r\n register_interrupts() "); register_interrupts(); // initialize the OLED screen print_dbg("\r\n init_oled() "); init_oled(); // enable interrupts print_dbg("\r\n cpu_irq_enable() "); cpu_irq_enable(); // usb host controller init_usb_host(); // initialize usb classes print_dbg("\r\n init_monome "); init_monome(); // init_midi(); // init_hid(); }
void memories_initialization(void) { //-- Hmatrix bus configuration // This improve speed performance #ifdef AVR32_HMATRIXB union { unsigned long scfg; avr32_hmatrixb_scfg_t SCFG; } u_avr32_hmatrixb_scfg; sysclk_enable_pbb_module(SYSCLK_HMATRIX); // For the internal-flash HMATRIX slave, use last master as default. u_avr32_hmatrixb_scfg.scfg = AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH]; u_avr32_hmatrixb_scfg.SCFG.defmstr_type = AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH] = u_avr32_hmatrixb_scfg.scfg; // For the internal-SRAM HMATRIX slave, use last master as default. u_avr32_hmatrixb_scfg.scfg = AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM]; u_avr32_hmatrixb_scfg.SCFG.defmstr_type = AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM] = u_avr32_hmatrixb_scfg.scfg; # ifdef AVR32_HMATRIXB_SLAVE_EBI // For the EBI HMATRIX slave, use last master as default. u_avr32_hmatrixb_scfg.scfg = AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI]; u_avr32_hmatrixb_scfg.SCFG.defmstr_type = AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI] = u_avr32_hmatrixb_scfg.scfg; # endif #endif #ifdef AVR32_HMATRIX union { unsigned long scfg; avr32_hmatrix_scfg_t SCFG; } u_avr32_hmatrix_scfg; sysclk_enable_pbb_module(SYSCLK_HMATRIX); // For the internal-flash HMATRIX slave, use last master as default. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH]; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] = u_avr32_hmatrix_scfg.scfg; // For the internal-SRAM HMATRIX slave, use last master as default. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM]; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM] = u_avr32_hmatrix_scfg.scfg; # ifdef AVR32_HMATRIX_SLAVE_EBI // For the EBI HMATRIX slave, use last master as default. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI]; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI] = u_avr32_hmatrix_scfg.scfg; # endif #endif #ifdef AVR32_HMATRIX_MASTER_USBB_DMA union { unsigned long mcfg; avr32_hmatrix_mcfg_t MCFG; } u_avr32_hmatrix_mcfg; // For the USBB DMA HMATRIX master, use infinite length burst. u_avr32_hmatrix_mcfg.mcfg = AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA]; u_avr32_hmatrix_mcfg.MCFG.ulbt = AVR32_HMATRIX_ULBT_INFINITE; AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA] = u_avr32_hmatrix_mcfg.mcfg; // For the USBB DPRAM HMATRIX slave, use the USBB DMA as fixed default master. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM]; u_avr32_hmatrix_scfg.SCFG.fixed_defmstr = AVR32_HMATRIX_MASTER_USBB_DMA; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM] = u_avr32_hmatrix_scfg.scfg; #endif #if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE) at45dbx_init(); #endif #if ((defined SD_MMC_0_MEM) && (SD_MMC_0_MEM == ENABLE)) \ || ((defined SD_MMC_1_MEM) && (SD_MMC_1_MEM == ENABLE)) sd_mmc_init(); #endif }
/** * \brief Enable the USB generic clock * * \pre The USB generic clock must be configured to 48MHz. * CONFIG_USBCLK_SOURCE and CONFIG_USBCLK_DIV must be defined with proper * configuration. The selected clock source must also be configured. */ void sysclk_enable_usb(void) { sysclk_enable_pbb_module(SYSCLK_USBB_REGS); sysclk_enable_hsb_module(SYSCLK_USBB_DATA); genclk_enable_config(AVR32_PM_GCLK_USBB, CONFIG_USBCLK_SOURCE, CONFIG_USBCLK_DIV); }
/** * \brief Enable a peripheral's clock from its base address. * * Enables the clock to a peripheral, given its base address. If the peripheral * has an associated clock on the HSB bus, this will be enabled also. * * \param module Pointer to the module's base address. */ void sysclk_enable_peripheral_clock(const volatile void *module) { switch ((uintptr_t)module) { #if !SAM4LS case AESA_ADDR: sysclk_enable_hsb_module(SYSCLK_AESA_HSB); break; #endif case IISC_ADDR: sysclk_enable_pba_module(SYSCLK_IISC); break; case SPI_ADDR: sysclk_enable_pba_module(SYSCLK_SPI); break; case TC0_ADDR: sysclk_enable_pba_module(SYSCLK_TC0); sysclk_enable_pba_divmask(PBA_DIVMASK_TIMER_CLOCK2 | PBA_DIVMASK_TIMER_CLOCK3 | PBA_DIVMASK_TIMER_CLOCK4 | PBA_DIVMASK_TIMER_CLOCK5 ); break; case TC1_ADDR: sysclk_enable_pba_module(SYSCLK_TC1); sysclk_enable_pba_divmask(PBA_DIVMASK_TIMER_CLOCK2 | PBA_DIVMASK_TIMER_CLOCK3 | PBA_DIVMASK_TIMER_CLOCK4 | PBA_DIVMASK_TIMER_CLOCK5 ); break; case TWIM0_ADDR: sysclk_enable_pba_module(SYSCLK_TWIM0); break; case TWIS0_ADDR: sysclk_enable_pba_module(SYSCLK_TWIS0); break; case TWIM1_ADDR: sysclk_enable_pba_module(SYSCLK_TWIM1); break; case TWIS1_ADDR: sysclk_enable_pba_module(SYSCLK_TWIS1); break; case USART0_ADDR: sysclk_enable_pba_module(SYSCLK_USART0); sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART); break; case USART1_ADDR: sysclk_enable_pba_module(SYSCLK_USART1); sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART); break; case USART2_ADDR: sysclk_enable_pba_module(SYSCLK_USART2); sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART); break; case USART3_ADDR: sysclk_enable_pba_module(SYSCLK_USART3); sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART); break; case ADCIFE_ADDR: sysclk_enable_pba_module(SYSCLK_ADCIFE); break; case DACC_ADDR: sysclk_enable_pba_module(SYSCLK_DACC); break; case ACIFC_ADDR: sysclk_enable_pba_module(SYSCLK_ACIFC); break; case GLOC_ADDR: sysclk_enable_pba_module(SYSCLK_GLOC); break; case ABDACB_ADDR: sysclk_enable_pba_module(SYSCLK_ABDACB); break; case TRNG_ADDR: sysclk_enable_pba_module(SYSCLK_TRNG); break; case PARC_ADDR: sysclk_enable_pba_module(SYSCLK_PARC); break; case CATB_ADDR: sysclk_enable_pba_module(SYSCLK_CATB); break; case TWIM2_ADDR: sysclk_enable_pba_module(SYSCLK_TWIM2); break; case TWIM3_ADDR: sysclk_enable_pba_module(SYSCLK_TWIM3); break; #if !SAM4LS case LCDCA_ADDR: sysclk_enable_pba_module(SYSCLK_LCDCA); break; #endif case HFLASHC_ADDR: sysclk_enable_hsb_module(SYSCLK_HFLASHC_DATA); sysclk_enable_pbb_module(SYSCLK_HFLASHC_REGS); break; case HCACHE_ADDR: sysclk_enable_hsb_module(SYSCLK_HRAMC1_DATA); sysclk_enable_pbb_module(SYSCLK_HRAMC1_REGS); break; case HMATRIX_ADDR: sysclk_enable_pbb_module(SYSCLK_HMATRIX); break; case PDCA_ADDR: sysclk_enable_hsb_module(SYSCLK_PDCA_HSB); sysclk_enable_pbb_module(SYSCLK_PDCA_PB); break; case CRCCU_ADDR: sysclk_enable_hsb_module(SYSCLK_CRCCU_DATA); sysclk_enable_pbb_module(SYSCLK_CRCCU_REGS); break; case USBC_ADDR: sysclk_enable_hsb_module(SYSCLK_USBC_DATA); sysclk_enable_pbb_module(SYSCLK_USBC_REGS); break; case PEVC_ADDR: sysclk_enable_pbb_module(SYSCLK_PEVC); break; case PM_ADDR: sysclk_enable_pbc_module(SYSCLK_PM); break; case CHIPID_ADDR: sysclk_enable_pbc_module(SYSCLK_CHIPID); break; case SCIF_ADDR: sysclk_enable_pbc_module(SYSCLK_SCIF); break; case FREQM_ADDR: sysclk_enable_pbc_module(SYSCLK_FREQM); break; case GPIO_ADDR: sysclk_enable_pbc_module(SYSCLK_GPIO); break; case BPM_ADDR: sysclk_enable_pbd_module(SYSCLK_BPM); break; case BSCIF_ADDR: sysclk_enable_pbd_module(SYSCLK_BSCIF); break; case AST_ADDR: sysclk_enable_pbd_module(SYSCLK_AST); break; case WDT_ADDR: sysclk_enable_pbd_module(SYSCLK_WDT); break; case EIC_ADDR: sysclk_enable_pbd_module(SYSCLK_EIC); break; case PICOUART_ADDR: sysclk_enable_pbd_module(SYSCLK_PICOUART); break; default: Assert(false); return; } }
/*! \brief Main function. */ int main(void) { bool valid_block_found[NF_N_DEVICES]; U32 u32_nf_ids, i_dev, i_block; U8 maker_id, device_id, byte3; U32 i, time_s, time_e; U8 data; // start init sysclk_init(); // Enable clock for require module sysclk_enable_hsb_module(SYSCLK_EBI); sysclk_enable_pbb_module(SYSCLK_SMC_REGS); sysclk_enable_pbb_module(SYSCLK_HMATRIX); // Initialize the board. // The board-specific conf_board.h file contains the configuration of the board // initialization. board_init(); init_stdio(); #ifdef NF_ADDON // addon nandflash board for EVK1104 (not mounted by default) // Unselect NF on board gpio_set_gpio_pin(AVR32_PIN_PX53); gpio_set_gpio_pin(AVR32_PIN_PX52); #endif nf_init(sysclk_get_cpu_hz()); nf_unprotect(); printf("\x0C"); printf("Nand Flash example.\r\n===================\r\n\r\n"); // - Simple test of the NF communication through the SMC. // - Find all bad blocks. // - Find a valid block for the remaining tests. nf_reset_nands(NF_N_DEVICES); printf("\tDetecting Nand Flash device(s).\r\n"); for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ ) { // Performs some init here... valid_block_found[i_dev] = false; // Test Maker and Device ids u32_nf_ids = nf_read_id( NF_READ_ID_CMD, i_dev ); maker_id = MSB0(u32_nf_ids); device_id = MSB1(u32_nf_ids); byte3 = MSB3(u32_nf_ids); printf("\t\tNF %ld: [Maker=0x%02x] [Device=0x%02x] [byte3=0x%02x]\r\n", i_dev, maker_id, device_id, byte3); if( maker_id==M_ID_MICRON ) { printf("\t\t Micron chip"); if( (device_id==0xDA) && (byte3==0x15) ) printf("- MT29F2G08AACWP device\r\n"); else if( (device_id==0xDA) && (byte3==0x95) ) printf("- MT29F2G08AADWP device\r\n"); else { printf("- *** Error: unexpected chip detected. Please check the board settings and hardware.\r\n"); return -1; } } else { printf("\t\t *** Error: unexpected chip detected. Please check the board settings and hardware.\r\n"); return -1; } } printf("\r\n\tTesting bad blocks.\r\n"); for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ ) { printf("\t\tNF %ld:\r\n", i_dev); nf_select(i_dev); for( i_block=0 ; i_block<G_N_BLOCKS ; i_block++ ) { nf_open_page_read( nf_block_2_page(i_block), NF_SPARE_POS + G_OFST_BLK_STATUS ); if( (nf_rd_data()!=0xFF) ) { // The block is bad. printf("\t\t\tBlock %ld (0x%lx) is bad.\r\n", i_block, i_block); } else { if( !valid_block_found[i_dev] ) { valid_block_found[i_dev]= true; valid_block_addr[i_dev] = i_block; printf("\t\t\tFirst valid block is at address %ld (0x%lx).\r\n", i_block, i_block); } } } } for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ ) if( !valid_block_found[i_dev] ) { printf("Error %d\r\n", __LINE__); return 0; } // - Ensure good NF behaviour through simple commands. // Erase, Program, Read // - Measures NF timings. printf("\r\n\tMeasuring NF timings.\r\n"); for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ ) { printf("\t\tNF %ld:\r\n", i_dev); nf_select(i_dev); nf_erase_block( nf_block_2_page(valid_block_addr[0]), false); time_s = Get_sys_count(); nf_wait_busy(); time_e = Get_sys_count(); // Verify that the block is erased. nf_open_page_read( nf_block_2_page(valid_block_addr[0]), 0); for( i= 0; i<2048 ; i++ ) { data = nf_rd_data(); if( data!=0xFF ) { printf("\tError: offset %d is not erased (read %d).\r\n", (U8)i, data); return 0; } } printf("\t\t\tTime to erase a page:%ld cy (%ld us)\r\n", time_e-time_s, cpu_cy_2_us(time_e-time_s, sysclk_get_cpu_hz())); nf_open_page_write( nf_block_2_page(valid_block_addr[0]), 0); for( i=0 ; i<2048 ; i++ ) nf_wr_data(i%256); nf_wr_cmd(NF_PAGE_PROGRAM_CMD); time_s = Get_sys_count(); nf_wait_busy(); time_e = Get_sys_count(); printf("\t\t\tTime to program a page:%ld cy (%ld us)\r\n", time_e-time_s, cpu_cy_2_us(time_e-time_s, sysclk_get_cpu_hz())); time_s = Get_sys_count(); nf_open_page_read( nf_block_2_page(valid_block_addr[0]), 0); time_e = Get_sys_count(); printf("\t\t\tTime to access to a page:%ld cy (%ld us)\r\n", time_e-time_s, cpu_cy_2_us(time_e-time_s, sysclk_get_cpu_hz())); for( i= 0; i<2048 ; i++ ) { data = nf_rd_data(); if( data!= i%256) { printf("\tError: expect %d, read %d\r\n", (U8)i, data); return 0; } } } printf("Example DONE\r\n"); return 0; }
void memories_initialization(void) { //-- Hmatrix bus configuration // This improve speed performance #ifdef AVR32_HMATRIXB union { unsigned long scfg; avr32_hmatrixb_scfg_t SCFG; } u_avr32_hmatrixb_scfg; sysclk_enable_pbb_module(SYSCLK_HMATRIX); // For the internal-flash HMATRIX slave, use last master as default. u_avr32_hmatrixb_scfg.scfg = AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH]; u_avr32_hmatrixb_scfg.SCFG.defmstr_type = AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH] = u_avr32_hmatrixb_scfg.scfg; // For the internal-SRAM HMATRIX slave, use last master as default. u_avr32_hmatrixb_scfg.scfg = AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM]; u_avr32_hmatrixb_scfg.SCFG.defmstr_type = AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM] = u_avr32_hmatrixb_scfg.scfg; # ifdef AVR32_HMATRIXB_SLAVE_EBI // For the EBI HMATRIX slave, use last master as default. u_avr32_hmatrixb_scfg.scfg = AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI]; u_avr32_hmatrixb_scfg.SCFG.defmstr_type = AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI] = u_avr32_hmatrixb_scfg.scfg; # endif #endif #ifdef AVR32_HMATRIX union { unsigned long scfg; avr32_hmatrix_scfg_t SCFG; } u_avr32_hmatrix_scfg; sysclk_enable_pbb_module(SYSCLK_HMATRIX); // For the internal-flash HMATRIX slave, use last master as default. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH]; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] = u_avr32_hmatrix_scfg.scfg; // For the internal-SRAM HMATRIX slave, use last master as default. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM]; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM] = u_avr32_hmatrix_scfg.scfg; # ifdef AVR32_HMATRIX_SLAVE_EBI // For the EBI HMATRIX slave, use last master as default. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI]; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI] = u_avr32_hmatrix_scfg.scfg; # endif #endif #ifdef AVR32_HMATRIX_MASTER_USBB_DMA union { unsigned long mcfg; avr32_hmatrix_mcfg_t MCFG; } u_avr32_hmatrix_mcfg; // For the USBB DMA HMATRIX master, use infinite length burst. u_avr32_hmatrix_mcfg.mcfg = AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA]; u_avr32_hmatrix_mcfg.MCFG.ulbt = AVR32_HMATRIX_ULBT_INFINITE; AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA] = u_avr32_hmatrix_mcfg.mcfg; // For the USBB DPRAM HMATRIX slave, use the USBB DMA as fixed default master. u_avr32_hmatrix_scfg.scfg = AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM]; u_avr32_hmatrix_scfg.SCFG.fixed_defmstr = AVR32_HMATRIX_MASTER_USBB_DMA; u_avr32_hmatrix_scfg.SCFG.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT; AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM] = u_avr32_hmatrix_scfg.scfg; #endif #if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE) sysclk_enable_peripheral_clock(AT45DBX_SPI_MODULE); at45dbx_init(); #endif #if ((defined SD_MMC_MCI_0_MEM) && (SD_MMC_MCI_0_MEM == ENABLE)) \ || ((defined SD_MMC_MCI_1_MEM) && (SD_MMC_MCI_1_MEM == ENABLE)) sysclk_enable_pbb_module(SYSCLK_MCI); sysclk_enable_hsb_module(SYSCLK_DMACA); sd_mmc_mci_init(SD_SLOT_8BITS, sysclk_get_pbb_hz(), sysclk_get_cpu_hz()); #endif #if (defined SD_MMC_SPI_MEM) && (SD_MMC_SPI_MEM == ENABLE) // SPI options. spi_options_t spiOptions = { .reg = SD_MMC_SPI_NPCS, .baudrate = SD_MMC_SPI_MASTER_SPEED, // Defined in conf_sd_mmc_spi.h. .bits = SD_MMC_SPI_BITS, // Defined in conf_sd_mmc_spi.h. .spck_delay = 0, .trans_delay = 0, .stay_act = 1, .spi_mode = 0, .modfdis = 1 }; sysclk_enable_peripheral_clock(SD_MMC_SPI); // If the SPI used by the SD/MMC is not enabled. if (!spi_is_enabled(SD_MMC_SPI)) { // Initialize as master. spi_initMaster(SD_MMC_SPI, &spiOptions); // Set selection mode: variable_ps, pcs_decode, delay. spi_selectionMode(SD_MMC_SPI, 0, 0, 0); // Enable SPI. spi_enable(SD_MMC_SPI); } // Initialize SD/MMC with SPI PB clock. sd_mmc_spi_init(spiOptions,sysclk_get_pba_hz()); #endif // SD_MMC_SPI_MEM == ENABLE }