static int __init bootstrap_init(void)
{
int rc;
int save_size = mioa701_bootstrap_lg + (sizeof(u32) * 3);
rc = sysdev_class_register(&mioa701_sysclass);
if (rc) {
printk(KERN_ERR "Failed registering mioa701 sys class\n");
return -ENODEV;
}
rc = sysdev_register(&sysdev_bootstrap);
if (rc) {
printk(KERN_ERR "Failed registering mioa701 sys device\n");
return -ENODEV;
}
rc = sysdev_driver_register(&mioa701_sysclass, &driver_bootstrap);
if (rc) {
printk(KERN_ERR "Failed registering PMU sys driver\n");
return -ENODEV;
}
save_buffer = kmalloc(save_size, GFP_KERNEL);
if (!save_buffer)
return -ENOMEM;
printk(KERN_INFO "MioA701: allocated %d bytes for bootstrap\n",
save_size);
return 0;
}
static int __init s5p6442_dma_init(void)
{
#ifdef CONFIG_OLD_DMA_PL330
return sysdev_driver_register(&s5p6442_sysclass, &s5p6442_dma_driver);
#else
platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
return 0;
#endif
}
int __init dvfm_stats_init(void)
{
int ret;
memset(&op_ticks_array, 0, sizeof(struct op_cycle_type) * OP_NUM);
ret = sysdev_driver_register(&cpu_sysdev_class, &dvfm_stats_driver);
if (ret)
printk(KERN_ERR "Can't register DVFM STATS in sysfs\n");
return ret;
}
static __init int exynos4_pm_drvinit(void)
{
unsigned int tmp;
s3c_pm_init();
/* All wakeup disable */
tmp = __raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
}
static __init int exynos4_pm_drvinit(void)
{
unsigned int tmp;
s3c_pm_init();
/* All wakeup disable */
tmp = __raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
/* Disable XXTI pad in system level normal mode */
__raw_writel(0x0, S5P_XXTI_CONFIGURATION);
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
}
static int __init mtrr_init_finialize(void)
{
if (!mtrr_if)
return 0;
if (use_intel())
mtrr_state_warn();
else {
/* The CPUs haven't MTRR and seemes not support SMP. They have
* specific drivers, we use a tricky method to support
* suspend/resume for them.
* TBD: is there any system with such CPU which supports
* suspend/resume? if no, we should remove the code.
*/
sysdev_driver_register(&cpu_sysdev_class,
&mtrr_sysdev_driver);
}
return 0;
}
static __init int s5pv310_pm_drvinit(void)
{
unsigned int tmp;
/* All wakeup disable */
tmp = __raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
/* Disable XXTI pad in system level normal mode */
__raw_writel(0x0, S5P_XXTI_CONFIGURATION);
/* Enable ARMCLK down feature with both ARM cores in IDLE mode */
tmp = __raw_readl(S5P_PWR_CTRL);
tmp |= ARMCLK_DOWN_ENABLE;
__raw_writel(tmp, S5P_PWR_CTRL);
return sysdev_driver_register(&s5pv310_sysclass, &s5pv310_pm_driver);
}
static int __init mtrr_init_finialize(void)
{
if (!mtrr_if)
return 0;
if (use_intel()) {
if (!changed_by_mtrr_cleanup)
mtrr_state_warn();
return 0;
}
/*
* The CPU has no MTRR and seems to not support SMP. They have
* specific drivers, we use a tricky method to support
* suspend/resume for them.
*
* TBD: is there any system with such CPU which supports
* suspend/resume? If no, we should remove the code.
*/
sysdev_driver_register(&cpu_sysdev_class, &mtrr_sysdev_driver);
return 0;
}
static int __init init_tsi108_pic_sysfs(void)
{
int rc;
if (!tsi108_csr_base)
return -ENODEV;
printk(KERN_DEBUG "Registering tsi108_pic with sysfs...\n");
rc = sysdev_class_register(&tsi108_pic_sysclass);
if (rc) {
printk(KERN_ERR "Failed registering tsi108_pic sys class\n");
return -ENODEV;
}
rc = sysdev_register(&device_tsi108_pic);
if (rc) {
printk(KERN_ERR "Failed registering tsi108_pic sys device\n");
return -ENODEV;
}
rc = sysdev_driver_register(&tsi108_pic_sysclass, &driver_tsi108_pic);
if (rc) {
printk(KERN_ERR "Failed registering tsi108_pic sys driver\n");
return -ENODEV;
}
return 0;
}
static int __init pmb_sysdev_init(void)
{
return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
}
static int s3c2442_clk_init(void)
{
return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
}
static int __init s3c2442_pm_drvinit(void)
{
return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver);
}
static int __init s3c2442_pll_12mhz(void)
{
return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
}
static int s3c6410_irq_init(void)
{
return sysdev_driver_register(&s3c6410_sysclass, &s3c6410_irq_driver);
}
static int __init s5pc100_dma_init(void)
{
return sysdev_driver_register(&s5pc100_sysclass, &s5pc100_dma_driver);
}
static int __init s3c2440_pll_16934400(void)
{
return sysdev_driver_register(&s3c2440_sysclass,
&s3c2440_plls169344_drv);
}
static __init int s3c2412_pm_init(void)
{
return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver);
}
static __init int exynos5_pm_drvinit(void)
{
s3c_pm_init();
return sysdev_driver_register(&exynos5_sysclass, &exynos5_pm_driver);
}
static int s3c2440_cpufreq_init(void)
{
return sysdev_driver_register(&s3c2440_sysclass,
&s3c2440_cpufreq_driver);
}
static int __init sw_dma_drvinit(void)
{
return sysdev_driver_register(&sw_sysclass, &sw_dma_driver);
}
/**
* mtrr_init - initialize mtrrs on the boot CPU
*
* This needs to be called early; before any of the other CPUs are
* initialized (i.e. before smp_init()).
*
*/
static int __init mtrr_init(void)
{
init_ifs();
if (cpu_has_mtrr) {
mtrr_if = &generic_mtrr_ops;
size_or_mask = 0xff000000; /* 36 bits */
size_and_mask = 0x00f00000;
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
/* The original Athlon docs said that
total addressable memory is 44 bits wide.
It was not really clear whether its MTRRs
follow this or not. (Read: 44 or 36 bits).
However, "x86-64_overview.pdf" explicitly
states that "previous implementations support
36 bit MTRRs" and also provides a way to
query the width (in bits) of the physical
addressable memory on the Hammer family.
*/
if (boot_cpu_data.x86 == 15
&& (cpuid_eax(0x80000000) >= 0x80000008)) {
u32 phys_addr;
phys_addr = cpuid_eax(0x80000008) & 0xff;
size_or_mask =
~((1 << (phys_addr - PAGE_SHIFT)) - 1);
size_and_mask = ~size_or_mask & 0xfff00000;
}
/* Athlon MTRRs use an Intel-compatible interface for
* getting and setting */
break;
case X86_VENDOR_CENTAUR:
if (boot_cpu_data.x86 == 6) {
/* VIA Cyrix family have Intel style MTRRs, but don't support PAE */
size_or_mask = 0xfff00000; /* 32 bits */
size_and_mask = 0;
}
break;
default:
break;
}
} else {
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
if (cpu_has_k6_mtrr) {
/* Pre-Athlon (K6) AMD CPU MTRRs */
mtrr_if = mtrr_ops[X86_VENDOR_AMD];
size_or_mask = 0xfff00000; /* 32 bits */
size_and_mask = 0;
}
break;
case X86_VENDOR_CENTAUR:
if (cpu_has_centaur_mcr) {
mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
size_or_mask = 0xfff00000; /* 32 bits */
size_and_mask = 0;
}
break;
case X86_VENDOR_CYRIX:
if (cpu_has_cyrix_arr) {
mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
size_or_mask = 0xfff00000; /* 32 bits */
size_and_mask = 0;
}
break;
default:
break;
}
}
printk(KERN_INFO "mtrr: v%s\n",MTRR_VERSION);
if (mtrr_if) {
set_num_var_ranges();
init_table();
init_other_cpus();
return sysdev_driver_register(&cpu_sysdev_class,
&mtrr_sysdev_driver);
}
return -ENXIO;
}
static int __init s3c2443_irq_init(void)
{
return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver);
}
static int __init s3c2412_dma_init(void)
{
return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
}
static int __init s3c2410a_pll_init(void)
{
return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv);
}
static __init int s5pv310_pm_drvinit(void)
{
unsigned int tmp;
/* All wakeup disable */
tmp = __raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
/* Disable XXTI pad in system level normal mode */
__raw_writel(0x0, S5P_XXTI_CONFIGURATION);
/* SCLK_APLL divider 7 */
tmp = __raw_readl(S5P_CLKDIV_CPU);
tmp &= ~(0x7 << 24);
tmp |= (0x7 << 24);
__raw_writel(tmp, S5P_CLKDIV_CPU);
do {
tmp = __raw_readl(S5P_CLKDIV_STATCPU);
} while (tmp & 0x1111111);
/* Not using L2 level, sclk_apll divider 0x7 */
__raw_writel(0x00003F03, S5P_CLKOUT_CMU_LEFTBUS);
/* Clockout ACLK_GPL and divider 64 */
__raw_writel(0x00003F03, S5P_CLKOUT_CMU_LEFTBUS);
/* Clockout ACLK_GPR and divider 64 */
__raw_writel(0x00003F03, S5P_CLKOUT_CMU_RIGHTBUS);
/* Clockout SCLK_HDMI27M and divider 64 */
__raw_writel(0x00003F02, S5P_CLKOUT_CMU_TOP);
/* Clockout SCLK_PWI and divider 64 */
__raw_writel(0x00003F07, S5P_CLKOUT_CMU_DMC);
/* Clockout SCLK_HPM and divider 64 */
__raw_writel(0x00003F0B, S5P_CLKOUT_CMU_CPU);
/* TV block divider 16 */
__raw_writel(0x0000000F, S5P_CLKOUT_CMU_CPU);
/* Clockout SCLK_HPM and divider 64 */
__raw_writel(0x00003F0B, S5P_CLKOUT_CMU_CPU);
/* TV block divider 16 */
tmp = __raw_readl(S5P_CLKDIV_TV);
tmp |= (0xF << 0);
__raw_writel(tmp, S5P_CLKDIV_TV);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_TV);
} while (tmp & 0x1);
/* SATA divider 16 */
tmp = __raw_readl(S5P_CLKDIV_TV);
tmp |= (0xF << 0);
__raw_writel(tmp, S5P_CLKDIV_TV);
/* SATA divider 16 */
tmp = __raw_readl(S5P_CLKDIV_FSYS0);
tmp |= (0xF << 20);
__raw_writel(tmp, S5P_CLKDIV_FSYS0);
/* Slimbus divider 16 */
tmp = __raw_readl(S5P_CLKDIV_PERIL3);
tmp |= (0xF << 4);
__raw_writel(tmp, S5P_CLKDIV_PERIL3);
/* PWI divider 16 */
tmp = __raw_readl(S5P_CLKDIV_DMC1);
tmp |= (0xF0F << 0);
__raw_writel(tmp, S5P_CLKDIV_DMC1);
/* Enable ARMCLK down feature with both ARM cores in IDLE mode */
tmp = __raw_readl(S5P_PWR_CTRL);
tmp |= ARMCLK_DOWN_ENABLE;
__raw_writel(tmp, S5P_PWR_CTRL);
return sysdev_driver_register(&s5pv310_sysclass, &s5pv310_pm_driver);
}
static __init int s3c24xx_clk_driver(void)
{
return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
}
static int imapx200_irq_init(void)
{
return sysdev_driver_register(&imapx200_sysclass, &imapx200_irq_driver);
}
