void TICKER_COUNTER_Handlr2(void)
{
uint32_t status=tc_get_status(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
if (((status & interrupmask) & TC_IER_CPCS)) {
if(lp_ticker_interrupt_counter) {
lp_ticker_interrupt_counter--;
} else {
if(lp_ticker_interrupt_offset) {
tc_stop(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
tc_write_rc(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, (uint32_t)lp_ticker_interrupt_offset);
tc_start(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
lp_ticker_interrupt_offset=0;
} else {
lp_ticker_irq_handler();
}
}
}
}
static void reset_timeout(void)
{
if (s_period_counter > 0)
{
// see how long to wait
uint16_t rc = min(0xffff,s_period_counter);
tc_write_rc(CONFIG_BSP_BUZZER_REP_TIMER, CONFIG_BSP_BUZZER_REP_CHANNEL, rc);
// remember how much we've waited
s_period_counter -= rc;
// Reset the counter
tc_start(CONFIG_BSP_BUZZER_REP_TIMER, CONFIG_BSP_BUZZER_REP_CHANNEL);
}
else
{
// make sure the timer is stopped
tc_stop(CONFIG_BSP_BUZZER_REP_TIMER, CONFIG_BSP_BUZZER_REP_CHANNEL);
}
}
/*! \brief to initialiaze hw timer
*/
uint8_t tmr_init(void)
{
uint8_t tmr_mul;
/* Configure clock service. */
#if SAM4L
sysclk_enable_peripheral_clock(TIMER);
#else
sysclk_enable_peripheral_clock(ID_TC);
#endif
/* Get system clock. */
tmr_mul = sysclk_get_peripheral_bus_hz(TIMER) / DEF_1MHZ;
tmr_mul = tmr_mul >> 1;
#if SAM4L
tc_init(TIMER, TIMER_CHANNEL_ID,
TC_CMR_TCCLKS_TIMER_CLOCK2 | TC_CMR_WAVE |
TC_CMR_WAVSEL_UP_NO_AUTO);
#elif SAM4E
tc_init(TIMER, TIMER_CHANNEL_ID,
TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_WAVE |
TC_CMR_WAVSEL_UP_RC);
#else
tc_init(TIMER, TIMER_CHANNEL_ID,
TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_WAVE |
TC_CMR_WAVSEL_UP);
#endif
/* Configure and enable interrupt on RC compare. */
configure_NVIC(TIMER, TIMER_CHANNEL_ID);
#if SAM4E
tc_get_status(TIMER, TIMER_CHANNEL_ID);
tc_enable_interrupt(TIMER, TIMER_CHANNEL_ID, TC_IER_CPCS);
tc_write_rc(TIMER, TIMER_CHANNEL_ID, UINT16_MAX);
#else
tc_get_status(TIMER, TIMER_CHANNEL_ID);
tc_enable_interrupt(TIMER, TIMER_CHANNEL_ID, TC_IER_COVFS);
#endif
tmr_disable_cc_interrupt();
tc_start(TIMER, TIMER_CHANNEL_ID);
return tmr_mul;
}
void TC0_Handler(void)
{
volatile uint32_t ul_dummy, TC_value;
/* Get the current timer counter value from a 32-bit register*/
TC_value = tc_read_tc(TC0,0);
/* Clear status bit to acknowledge interrupt */
ul_dummy = tc_get_status(TC0, 0);
if ((ul_dummy & TC_SR_CPCS) == TC_SR_CPCS) {
#if DEBUG
printf("%08x OV \n",TC_value);
#endif
time_msb++;
rtimer_clock_t now = ((rtimer_clock_t)time_msb << 32)|tc_read_tc(TC0,0);
rtimer_clock_t clock_to_wait = next_rtimer_time - now;
if(clock_to_wait <= 0x100000000 && clock_to_wait > 0)
{
// We must set now the Timer Compare Register.
// Set the auxiliary timer (TC0,1) at the write time interrupt
tc_write_rc(TC0,1,(uint32_t)clock_to_wait);
// Set and enable interrupt on RC compare
tc_enable_interrupt(TC0,1,TC_IER_CPCS);
// Start the auxiliary timer
tc_start(TC0,1);
}
}
else {
printf("ERROR: TC: Unknown interrupt.\n");
}
}
/**
* \brief Configure Timer Counter 0 to generate an interrupt with the specific
* frequency.
*
* \param freq Timer counter frequency.
*/
static void configure_tc(uint32_t freq)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Disable TC first */
tc_stop(TC0, 0);
tc_disable_interrupt(TC0, 0, TC_IER_CPCS);
/** Configure TC with the frequency and trigger on RC compare. */
tc_find_mck_divisor(freq, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type)ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/** Start the counter. */
tc_start(TC0, 0);
}
/**
* \brief Configure to trigger AFEC by TIOA output of timer.
*/
static void configure_tc_trigger(void)
{
uint32_t ul_div = 0;
uint32_t ul_tc_clks = 0;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_TC0);
/* Configure TC for a 1Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(1, ul_sysclk, &ul_div, &ul_tc_clks, ul_sysclk);
tc_init(TC0, 0, ul_tc_clks | TC_CMR_CPCTRG | TC_CMR_WAVE |
TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET);
TC0->TC_CHANNEL[0].TC_RA = (ul_sysclk / ul_div) / 2;
TC0->TC_CHANNEL[0].TC_RC = (ul_sysclk / ul_div) / 1;
/* Start the Timer. */
tc_start(TC0, 0);
afec_set_trigger(AFEC1, AFEC_TRIG_TIO_CH_0);
}
static void configure_tc(void)
{
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual est'a em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = TC_CMR_TCCLKS_TIMER_CLOCK5;
/*
* Ativa o clock do periférico TC 0
*
*/
pmc_enable_periph_clk(ID_TC0);
/*
* Configura TC para operar no modo de comparação e trigger RC
* devemos nos preocupar com o clock em que o TC irá operar !
*
* Cada TC possui 3 canais, escolher um para utilizar.
*
* Uma opção para achar o valor do divisor é utilizar a funcao
* tc_find_mck_divisor()
*/
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
tc_write_rc(TC0, 0, 534);
/*
* Devemos configurar o NVIC para receber interrupções do TC
*/
NVIC_EnableIRQ(ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
tc_start(TC0,0);
}
static void initialize_EPD_timer(void) {
uint32_t rc;
/* Configure the PMC to enable the Timer/Counter (TC) module. */
sysclk_enable_peripheral_clock(EPD_TC_TIMER_ID);
/** TC Configuration structure. */
struct tc_control_reg tc_control_par = {
/** TC Compare Output Mode */
.co_mode = CO_NORMAL,
/** TC Waveform Generation Mode */
.wg_mode = CTC_Mode1,
/** TC Clock Selection, Prescalar select */
.cs_select = EPD_TC_ClockSignalSel
};
/** Init TC to timer ctc mode. */
tc_initc(EPD_TC_TIMER_ID, EPD_TC_TIMER_CHANNEL, &tc_control_par);
/** Configure OVF value */
rc = (sysclk_get_peripheral_bus_hz(EPD_TC_TIMER_ID) /
divisors[EPD_TC_ClockSignalSel] ) /
1000 ;
tc_write_cc(EPD_TC_TIMER_ID, EPD_TC_TIMER_CHANNEL, rc);
/** Configure and enable interrupt on TC CTC compare match */
tc_set_compa_interrupt_callback(EPD_TC_TIMER_ID, EPD_timer_handler);
tc_enable_compa_int(EPD_TC_TIMER_ID);
cpu_irq_enable();
tc_start(EPD_TC_TIMER_ID, &tc_control_par);
EPD_Counter=0;
/** Configure the PMC to enable the Timer/Counter (TC) module. */
sysclk_enable_peripheral_clock(EPD_TC_TIMER_ID);
}
/**
* \brief Interrupt handler for USART. Echo the bytes received and start the
* next receive.
*/
void USART_Handler(void)
{
uint32_t ul_status;
/* Read USART Status. */
ul_status = usart_get_status(BOARD_USART);
/* Receive buffer is full. */
if (ul_status & US_CSR_RXBUFF) {
/* Disable timer. */
tc_stop(TC0, 0);
/* Echo back buffer. */
pdca_channel_write_load(PDCA_TX_CHANNEL,
(void *)gs_puc_buffer[gs_uc_buf_num],
gs_ul_size_buffer);
pdca_channel_write_reload(PDCA_TX_CHANNEL,
(void *)gs_puc_nextbuffer[gs_uc_buf_num],
gs_ul_size_nextbuffer);
if (g_uc_transend_flag) {
gs_ul_size_buffer = BUFFER_SIZE;
gs_ul_size_nextbuffer = BUFFER_SIZE;
g_uc_transend_flag = 0;
}
gs_uc_buf_num = MAX_BUF_NUM - gs_uc_buf_num;
/* Restart read on buffer. */
pdca_channel_write_load(PDCA_RX_CHANNEL,
(void *)gs_puc_buffer[gs_uc_buf_num], BUFFER_SIZE);
pdca_channel_write_reload(PDCA_RX_CHANNEL,
(void *)gs_puc_nextbuffer[gs_uc_buf_num], BUFFER_SIZE);
/* Restart timer. */
tc_start(TC0, 0);
}
}
/** @brief Init Timer interrupt (1ms)
*
* Initialize 1mSec timer 3 interrupt */
void initTimer1ms(void)
{
uint32_t ul_div, ul_tcclks;
/* Configure PMC */
pmc_enable_periph_clk(ID_TC_1MS);
/* MCK = 120000000 -> tcclks = 2 : TCLK3 = MCK/32 = 3750000 = 0.266us ->
* ul_div = 1ms/0.2666us = 3750 */
ul_tcclks = 2;
ul_div = 3750;
tc_init(TC_1MS, TC_1MS_CHN, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC_1MS, TC_1MS_CHN, ul_div);
/* Configure and enable interrupt on RC compare */
NVIC_SetPriority((IRQn_Type)ID_TC_1MS, 0);
NVIC_EnableIRQ((IRQn_Type)ID_TC_1MS);
tc_enable_interrupt(TC_1MS, TC_1MS_CHN, TC_IER_CPCS);
/** Start the timer. TC1, chanel 0 = TC3 */
tc_start(TC_1MS, TC_1MS_CHN);
}
/**
* \brief Configure to trigger ADC by TIOA output of timer.
*/
static void configure_tc_trigger(void)
{
uint32_t ul_div = 0;
uint32_t ul_tc_clks = 0;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_TC0);
/* TIOA configuration */
ioport_set_pin_mode(PIN_TC0_TIOA0, PIN_TC0_TIOA0_MUX);
ioport_disable_pin(PIN_TC0_TIOA0);
/* Configure TC for a 10Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(10, ul_sysclk, &ul_div, &ul_tc_clks, ul_sysclk);
tc_init(TC0, 0, ul_tc_clks | TC_CMR_CPCTRG | TC_CMR_WAVE |
TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET);
TC0->TC_CHANNEL[0].TC_RA = (ul_sysclk / ul_div) / 2;
TC0->TC_CHANNEL[0].TC_RC = (ul_sysclk / ul_div) / 1;
/* Start the Timer. */
tc_start(TC0, 0);
}
/**
* \brief Configure TC TC_CHANNEL_WAVEFORM in waveform operating mode.
*/
static void tc_waveform_initialize(void)
{
uint32_t ra, rc;
/* Configure the PMC to enable the TC module. */
sysclk_enable_peripheral_clock(ID_TC_WAVEFORM);
/* Init TC to waveform mode. */
tc_init(TC, TC_CHANNEL_WAVEFORM,
/* Waveform Clock Selection */
gc_waveconfig[gs_uc_configuration].ul_intclock
| TC_CMR_WAVE /* Waveform mode is enabled */
| TC_CMR_ACPA_SET /* RA Compare Effect: set */
| TC_CMR_ACPC_CLEAR /* RC Compare Effect: clear */
| TC_CMR_CPCTRG /* UP mode with automatic trigger on RC Compare */
);
/* Configure waveform frequency and duty cycle. */
#if (SAM4L)
rc = (sysclk_get_peripheral_bus_hz(TC) /
divisors[gc_waveconfig[gs_uc_configuration].ul_intclock]) /
gc_waveconfig[gs_uc_configuration].us_frequency;
#else
rc = (sysclk_get_peripheral_hz() /
divisors[gc_waveconfig[gs_uc_configuration].ul_intclock]) /
gc_waveconfig[gs_uc_configuration].us_frequency;
#endif
tc_write_rc(TC, TC_CHANNEL_WAVEFORM, rc);
ra = (100 - gc_waveconfig[gs_uc_configuration].us_dutycycle) * rc / 100;
tc_write_ra(TC, TC_CHANNEL_WAVEFORM, ra);
/* Enable TC TC_CHANNEL_WAVEFORM. */
tc_start(TC, TC_CHANNEL_WAVEFORM);
printf("Start waveform: Frequency = %d Hz,Duty Cycle = %2d%%\n\r",
gc_waveconfig[gs_uc_configuration].us_frequency,
gc_waveconfig[gs_uc_configuration].us_dutycycle);
}
/**
* Configure Timer Counter 0 to generate an interrupt every 200ms.
*/
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure TC0 */
sysclk_enable_peripheral_clock(TC0);
/* Configure TC for a 5Hz frequency and trigger on RC compare. */
if (!tc_find_mck_divisor(5, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk)) {
puts("No valid divisor found!\r");
return;
}
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 5);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type) TC00_IRQn);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/* Start the counter. */
tc_start(TC0, 0);
}
void config_tccapture_freq(void){
/** Configure PIO Pins for TC */
ioport_set_pin_mode(PIN_TC0_TIOA2, PIN_TC0_TIOA2_MUX );
/** Disable I/O to enable peripheral mode) */
ioport_disable_pin(PIN_TC0_TIOA2);
sysclk_enable_peripheral_clock(ID_TC2);
tc_init(TC0, TC_CHANNEL_CAP_FREQ,
TC_CAPTURE_TCCLKS | // Clock Selection = MCLK/32 CLK3
TC_CMR_LDRA_RISING | // RA Loading = Rising edge of TIOA
TC_CMR_LDRB_FALLING | // RB Loading = Falling Edge of TIOA
TC_CMR_ABETRG | // External Trigger = TIOA
TC_CMR_ETRGEDG_FALLING // External Trigger Edge = Falling Edge
);
NVIC_DisableIRQ(TC2_IRQn);
NVIC_ClearPendingIRQ(TC2_IRQn);
NVIC_SetPriority(TC2_IRQn, PRIORITY_MEASURE);
NVIC_EnableIRQ(TC2_IRQn);
tc_enable_interrupt(TC0, TC_CHANNEL_CAP_FREQ, TC_IER_LDRBS);
tc_start(TC0, TC_CHANNEL_CAP_FREQ);
}
/**
* \brief Application entry point for usart_serial example.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
/* Initialize the SAM system. */
sysclk_init();
board_init();
/* Configure UART for debug message output. */
configure_console();
/* Output example information. */
puts(STRING_HEADER);
puts("-- Start to echo serial inputs with PDCA -- \r\n\r");
/* Configure TC. */
configure_tc();
/* Enable PDCA module clock */
pdca_enable(PDCA);
/* Init PDCA channel with the pdca_options.*/
pdca_channel_set_config(PDCA_RX_CHANNEL, &pdca_rx_options);
pdca_channel_set_config(PDCA_TX_CHANNEL, &pdca_tx_options);
/* Enable PDCA channel, start receiving data. */
pdca_channel_enable(PDCA_RX_CHANNEL);
pdca_channel_enable(PDCA_TX_CHANNEL);
/* Enable USART RXBUFF interrupt */
usart_enable_interrupt(BOARD_USART, US_IER_RXBUFF);
/* Configure and enable interrupt of USART. */
NVIC_EnableIRQ(USART_IRQn);
/* Start timer. */
tc_start(TC0, 0);
while (1) {
}
}
void config_tccapture_duty(void){
/** Configure PIO Pins for TC */
ioport_set_pin_mode(PIO_PC23_IDX, IOPORT_MODE_MUX_B );
/** Disable I/O to enable peripheral mode) */
ioport_disable_pin(PIO_PC23_IDX);
sysclk_enable_peripheral_clock(ID_TC3);
tc_init(TC1, TC_CHANNEL_CAP_DUTY,
TC_CAP_DUTY_TCCLKS | // Clock Selection = MCLK/32
TC_CMR_LDRA_RISING | // RA Loading = Rising edge of TIOA
TC_CMR_LDRB_FALLING | // RB Loading = Falling Edge of TIOA
TC_CMR_ABETRG | // External Trigger = TIOA
TC_CMR_ETRGEDG_FALLING // External Trigger Edge = Falling Edge
);
NVIC_DisableIRQ(TC3_IRQn);
NVIC_ClearPendingIRQ(TC3_IRQn);
NVIC_SetPriority(TC3_IRQn, PRIORITY_MEASURE);
NVIC_EnableIRQ(TC3_IRQn);
tc_enable_interrupt(TC1, TC_CHANNEL_CAP_DUTY, TC_IER_LDRBS);
tc_start(TC1, TC_CHANNEL_CAP_DUTY);
}
/**
* Initialize the timer counter (TC0).
*
*/
void sys_init_timing(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Clear tick value. */
gs_ul_clk_tick = 0;
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC0);
/* Configure TC for a 1kHz frequency and therefore a 1ms rate */
tc_find_mck_divisor(1000, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 1000);
/* Configure and enable interrupt on RC compare. */
NVIC_EnableIRQ((IRQn_Type)ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/* Start timer. */
tc_start(TC0, 0);
}
/**
* \brief Initializes the TC subsystem ready to generate a LED PWM wave.
*
* Initializes the on-chip TC module in PWM generation mode, and configures the
* board LED as an output so that the LED brightness can be adjusted.
*/
static void pwm_timer_init(void)
{
// Assign output pin to timer/counter 0 channel B
gpio_enable_module_pin(AVR32_TC0_B0_0_0_PIN,
AVR32_TC0_B0_0_0_FUNCTION);
// Timer waveform options
const tc_waveform_opt_t waveform_options = {
//! Channel selection.
.channel = 0,
//! Software trigger effect on TIOB.
.bswtrg = TC_EVT_EFFECT_NOOP,
//! External event effect on TIOB.
.beevt = TC_EVT_EFFECT_NOOP,
//! RC compare effect on TIOB.
.bcpc = TC_EVT_EFFECT_CLEAR,
//! RB compare effect on TIOB.
.bcpb = TC_EVT_EFFECT_SET,
//! Software trigger effect on TIOA.
.aswtrg = TC_EVT_EFFECT_NOOP,
//! External event effect on TIOA.
.aeevt = TC_EVT_EFFECT_NOOP,
//! RC compare effect on TIOA.
.acpc = TC_EVT_EFFECT_NOOP,
//! RA compare effect on TIOA.
.acpa = TC_EVT_EFFECT_NOOP,
//! Waveform selection
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,
//! External event trigger enable.
.enetrg = false,
//! External event selection (non-zero for Channel B to work)
.eevt = !0,
//! External event edge selection.
.eevtedg = TC_SEL_NO_EDGE,
//! Counter disable when RC compare.
.cpcdis = false,
//! Counter clock stopped with RC compare.
.cpcstop = false,
//! Burst signal selection.
.burst = false,
//! Clock inversion selection.
.clki = false,
//! Internal source clock 5, fPBA/128.
.tcclks = TC_CLOCK_SOURCE_TC5,
};
// Setup timer/counter waveform mode
sysclk_enable_peripheral_clock(&AVR32_TC0);
tc_init_waveform(&AVR32_TC0, &waveform_options);
// Write the TOP (RC) and COMPARE (RB) values
tc_write_rb(&AVR32_TC0, 0, 1); // Set RB value.
tc_write_rc(&AVR32_TC0, 0, 255); // Set RC value.
// Start the timer PWM channel
tc_start(&AVR32_TC0, 0);
}
/**
* \brief Application main routine
*/
int main(void)
{
board_init();
sysclk_init();
irq_initialize_vectors();
cpu_irq_enable();
pwm_timer_init();
touch_init();
while (true) {
touch_handler();
}
}
bool standalone_mode_run(void)
{
char tempstring1[24];
while(detect_lcd()==false);
usart_write_line(LCD_USART, "play stndprog\r\n");
while(detect_lcd()==false);
usart_write_line(LCD_USART, "DMETER_VALUE 1 1\r\n");
while(detect_lcd()==false);
sprintf(tempstring1,"DMETER_VALUE 2 %u\r\n",t_experiment.N_experiments);
usart_write_line(LCD_USART, tempstring1);
while(detect_lcd()==false);
usart_write_line(LCD_USART, "DMETER_VALUE 3 1\r\n");
while(detect_lcd()==false);
sprintf(tempstring1,"DMETER_VALUE 4 %u\r\n",t_experiment.N_sequences);
usart_write_line(LCD_USART, tempstring1);
while(detect_lcd()==false);
reset_SD_sink_ptr(); //start saving data at data_base_addr
DAC1->dr0=t_experiment.t_Vgain; //set gain of RF amp
tc_write_rc(SLOW_TC,SLOW_TC_slow_CHANNEL,t_experiment.t_sequence[0].t_TR);
tc_start(SLOW_TC, SLOW_TC_slow_CHANNEL); //start slow timer
tc_start(SLOW_TC, SLOW_TC_fast_CHANNEL); //start slow timer
pdca_disable(USB_USART_RX_PDCA_CHANNEL); //Not going to need USB USART for a while
pdca_disable(USB_USART_TX_PDCA_CHANNEL);
bool progscreen=true; //state variable for user interface
for(uint16_t experimentcount=0;experimentcount<t_experiment.N_experiments;experimentcount++)
{
for(uint8_t sequencecount=0;sequencecount<t_experiment.N_sequences;sequencecount++)
{
t_currentsequence=t_experiment.t_sequence[sequencecount]; //get sequence
while((tc_read_sr(SLOW_TC, SLOW_TC_slow_CHANNEL) & AVR32_TC_SR1_CPCS_MASK)==0);
tc_write_rc(SLOW_TC,SLOW_TC_slow_CHANNEL,t_experiment.t_sequence[sequencecount].t_TR);
char *LCDCMD=get_LCD_cmd();
if((progscreen==true) && (strcmp(LCDCMD,"BR2\r")==0)) //BR2 is first cancel button
{
progscreen=false;
usart_write_line(LCD_USART, "play confcanc\r\n");
while(detect_lcd()==false);
}
else if((progscreen==false) && (strcmp(LCDCMD,"BR3\r")==0)) //BR3 is confirm cancel button
{
usart_write_line(LCD_USART, "play modesel\r\n"); //maybe modsel isn't necessary here, but will be done after return?
return false;
}
else if((progscreen==false) && (strcmp(LCDCMD,"BR1\r")==0)) //BR1 if resume button
{
progscreen=true;
usart_write_line(LCD_USART, "play stndprog\r\n");
while(detect_lcd()==false);
sprintf(tempstring1,"DMETER_VALUE 1 %u\r",(experimentcount+1));
usart_write_line(LCD_USART, tempstring1);
while(detect_lcd()==false);
sprintf(tempstring1,"DMETER_VALUE 2 %u\r",t_experiment.N_experiments);
usart_write_line(LCD_USART, tempstring1);
while(detect_lcd()==false);
sprintf(tempstring1,"DMETER_VALUE 3 %u\r",(sequencecount+1));
usart_write_line(LCD_USART, tempstring1);
while(detect_lcd()==false);
sprintf(tempstring1,"DMETER_VALUE 4 %u\r",t_experiment.N_sequences);
usart_write_line(LCD_USART, tempstring1);
while(detect_lcd()==false);
}
else if(progscreen==true)
{
sprintf(tempstring1,"DMETER_VALUE 1 %u\r",(experimentcount+1));
gpio_set_gpio_pin(GEN1_pin);
usart_write_line(LCD_USART, tempstring1);
while(wait_for_CR()==false);
gpio_clr_gpio_pin(GEN1_pin);
sprintf(tempstring1,"DMETER_VALUE 3 %u\r",(sequencecount+1));
gpio_set_gpio_pin(GEN1_pin);
usart_write_line(LCD_USART, tempstring1);
while(wait_for_CR()==false);
gpio_clr_gpio_pin(GEN1_pin);
}
executesequence_SDstorage_multiprep_combined();
}
}
return true;
}
/**
* \name PWM functions
* @{
*/
void ui_pwm_led_init(uint8_t lednum)
{
/* Timer waveform options */
static tc_waveform_opt_t waveform_options = {
/* Channel selection. */
.channel = 1,
.bswtrg = TC_EVT_EFFECT_NOOP,
.beevt = TC_EVT_EFFECT_NOOP,
.bcpc = TC_EVT_EFFECT_NOOP,
.bcpb = TC_EVT_EFFECT_NOOP,
.aswtrg = TC_EVT_EFFECT_NOOP,
.aeevt = TC_EVT_EFFECT_NOOP,
.acpc = TC_EVT_EFFECT_NOOP,
.acpa = TC_EVT_EFFECT_NOOP,
/* Waveform selection */
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,
/* External event trigger enable. */
.enetrg = false,
/* External event selection (non-zero for Channel B to work) */
.eevt = !0,
/* External event edge selection. */
.eevtedg = TC_SEL_NO_EDGE,
.cpcdis = false,
.cpcstop = false,
.burst = false,
.clki = false,
/* Internal source clock 5, fPBA/128. */
.tcclks = TC_CLOCK_SOURCE_TC5,
};
switch (lednum) {
case LED0:
/* Assign output pin to timer/counter 0 channel A */
/* Channel selection. */
waveform_options.channel = 1;
waveform_options.bcpc = TC_EVT_EFFECT_NOOP;
waveform_options.bcpb = TC_EVT_EFFECT_NOOP;
/* RC compare effect on TIOA. */
waveform_options.acpc = TC_EVT_EFFECT_CLEAR;
/* RA compare effect on TIOA. */
waveform_options.acpa = TC_EVT_EFFECT_SET;
/* Setup timer/counter waveform mode */
sysclk_enable_peripheral_clock(&AVR32_TC0);
tc_init_waveform(&AVR32_TC0, &waveform_options);
/* Write the TOP (RC) and COMPARE (RA) values */
tc_write_ra(&AVR32_TC0, 1, 1); /* Set RA value. */
tc_write_rc(&AVR32_TC0, 1, 255); /* Set RC value. */
/* Start the timer PWM channel */
tc_start(&AVR32_TC0, 1);
break;
case LED1:
/* Assign output pin to timer/counter 1 channel B */
/* Channel selection. */
waveform_options.channel = 2;
waveform_options.acpc = TC_EVT_EFFECT_NOOP;
waveform_options.acpa = TC_EVT_EFFECT_NOOP;
/* RC compare effect on TIOB. */
waveform_options.bcpc = TC_EVT_EFFECT_CLEAR;
/* RB compare effect on TIOB. */
waveform_options.bcpb = TC_EVT_EFFECT_SET;
/* Setup timer/counter waveform mode */
sysclk_enable_peripheral_clock(&AVR32_TC1);
tc_init_waveform(&AVR32_TC1, &waveform_options);
/* Write the TOP (RC) and COMPARE (RB) values */
tc_write_rb(&AVR32_TC1, 2, 1); /* Set RB value. */
tc_write_rc(&AVR32_TC1, 2, 255); /* Set RC value. */
/* Start the timer PWM channel */
tc_start(&AVR32_TC1, 2);
break;
default:
break;
}
}
void ui_pwm_update(uint8_t channum, uint8_t brightness)
{
switch (channum) {
case LED0:
if (brightness != 0) {
gpio_enable_module_pin(AVR32_TC0_A1_0_1_PIN,
AVR32_TC0_A1_0_1_FUNCTION);
tc_start(&AVR32_TC0, 1);
tc_write_ra(&AVR32_TC0, 1, brightness);
} else {
tc_stop(&AVR32_TC0, 1);
LED_Off(LED0);
}
break;
case LED1:
if (brightness != 0) {
gpio_enable_module_pin(AVR32_TC1_B2_0_PIN,
AVR32_TC1_B2_0_FUNCTION);
tc_start(&AVR32_TC1, 2);
tc_write_rb(&AVR32_TC1, 2, brightness);
} else {
tc_stop(&AVR32_TC1, 2);
LED_Off(LED0);
}
break;
default:
break;
}
}
/* End of PWM */
/** @} */
/**
* \name Display functions
* @{
*/
static void ui_display_enable(void)
{
delay_init(sysclk_get_cpu_hz());
et024006_Init( sysclk_get_cpu_hz(), sysclk_get_hsb_hz());
/* Clear the display i.e. make it black */
et024006_DrawFilledRect(0, 0, ET024006_WIDTH, ET024006_HEIGHT, BLACK );
/* Set the backlight. */
gpio_set_gpio_pin(ET024006DHU_BL_PIN);
ui_display_init_rtc();
ui_display_welcome_msg();
}
// Here should be all the initialization functions for the module before 12v power
void init_module_peripherals_bp(void)
{
/* LEDs IO */
pmc_enable_periph_clk(IN_CLK_LED1_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED2_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED3_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED1_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED2_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED3_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
/* Pulse inputs/state & d reset output */
pmc_enable_periph_clk(OUT_PULSE_DET_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_DET_PIO_ID);
ioport_set_pin_dir(DATA_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_DET_PIO_ID);
ioport_set_pin_dir(CLK_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_STATE_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_STATE_PIO_ID);
ioport_set_pin_dir(DATA_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_STATE_PIO_ID);
ioport_set_pin_dir(CLK_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_RST_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(DATA_PULSE_RST_PIO_ID);
ioport_set_pin_dir(DATA_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLK_PULSE_RST_PIO_ID);
ioport_set_pin_dir(CLK_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLK_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Sload */
pmc_enable_periph_clk(DATA_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLOCK_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RESET_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RF_ATTEN_SLOAD_PIO_ID);
ioport_set_pin_dir(RF_ATTEN_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RF_ATTEN_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Delay enables */
pmc_enable_periph_clk(DATA_DELAY_EN_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(CLOCK_DELAY_EN_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(RESET_DELAY_EN_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
// Init LED interrupt,
uint32_t ul_div;
uint32_t ul_tcclks;
/* Get system clock. */
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC1);
/* Configure TC for a TC_FREQ frequency and trigger on RC compare. */
tc_find_mck_divisor(20, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 1, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 1, (ul_sysclk / ul_div) / 20);
/* Configure and enable interrupt on RC compare. */
tc_start(TC0, 1);
NVIC_DisableIRQ(TC1_IRQn);
NVIC_ClearPendingIRQ(TC1_IRQn);
//NVIC_SetPriority(TC1_IRQn, 0);
NVIC_EnableIRQ((IRQn_Type)ID_TC1);
tc_enable_interrupt(TC0, 1, TC_IER_CPCS);
/* SPI interface */
gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS);
gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS);
gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS);
//gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); // Controled by software
/* Configure an SPI peripheral. */
spi_enable_clock(SPI0);
spi_disable(SPI0);
spi_reset(SPI0);
spi_set_lastxfer(SPI0);
spi_set_master_mode(SPI0);
spi_disable_mode_fault_detect(SPI0);
/* Set variable chip select */
spi_set_variable_peripheral_select(SPI0);
/* Configure delay SPI channel */
spi_set_clock_polarity(SPI0, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_CHIP_SEL, SPI_CSR_BITS_11_BIT);
spi_configure_cs_behavior(SPI0, SPI_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Configure RF atten SPI channel */
spi_set_clock_polarity(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_ALT_CHIP_SEL, SPI_CSR_BITS_16_BIT);
spi_configure_cs_behavior(SPI0, SPI_ALT_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_ALT_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_ALT_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Enable SPI */
spi_enable(SPI0);
}
/* Setup the timer to generate the tick interrupts. */
static void prvSetupTimerInterrupt(void)
{
#if( configTICK_USE_TC==1 )
volatile avr32_tc_t *tc = &AVR32_TC;
// Options for waveform genration.
tc_waveform_opt_t waveform_opt =
{
.channel = configTICK_TC_CHANNEL, /* Channel selection. */
.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
.beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
.enetrg = FALSE, /* External event trigger enable. */
.eevt = 0, /* External event selection. */
.eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
.cpcdis = FALSE, /* Counter disable when RC compare. */
.cpcstop = FALSE, /* Counter clock stopped with RC compare. */
.burst = FALSE, /* Burst signal selection. */
.clki = FALSE, /* Clock inversion. */
.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
};
tc_interrupt_t tc_interrupt =
{
.etrgs=0,
.ldrbs=0,
.ldras=0,
.cpcs =1,
.cpbs =0,
.cpas =0,
.lovrs=0,
.covfs=0,
};
#endif
/* Disable all interrupt/exception. */
portDISABLE_INTERRUPTS();
/* Register the compare interrupt handler to the interrupt controller and
enable the compare interrupt. */
#if( configTICK_USE_TC==1 )
{
INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
/* Initialize the timer/counter. */
tc_init_waveform(tc, &waveform_opt);
/* Set the compare triggers.
Remember TC counter is 16-bits, so counting second is not possible!
That's why we configure it to count ms. */
tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
/* Start the timer/counter. */
tc_start(tc, configTICK_TC_CHANNEL);
}
#else
{
INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
prvScheduleFirstTick();
}
#endif
}
/*! \brief to initialiaze hw timer
*/
uint8_t tmr_init(void)
{
uint8_t timer_multiplier;
/* Options for waveform generation. */
tc_waveform_opt_t waveform_opt = {
.channel = TIMER_CHANNEL_ID, /* Channel selection. */
.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect
* on TIOB. */
.beevt = TC_EVT_EFFECT_NOOP, /* External event effect
* on TIOB. */
.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on
* TIOB. */
.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on
* TIOB. */
.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect
* on TIOA. */
.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect
* on TIOA. */
.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on
* TIOA */
.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on
* TIOA */
.wavsel = TC_WAVEFORM_SEL_UP_MODE, /* Waveform selection: Up
* mode without automatic
* trigger on RC compare.
**/
.enetrg = false, /* External event trigger
* enable. */
.eevt = TC_EXT_EVENT_SEL_TIOB_INPUT, /* External event
* selection. */
.eevtedg = TC_SEL_NO_EDGE, /* External event edge
* selection. */
.cpcdis = false, /* Counter disable when RC
* compare. */
.cpcstop = false, /* Counter clock stopped
* with RC compare. */
.burst = TC_BURST_NOT_GATED, /* Burst signal selection.
**/
.clki = TC_CLOCK_RISING_EDGE, /* Clock inversion. */
.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock
* 3, connected to fPBA /
* 8. */
};
sysclk_enable_peripheral_clock(TIMER);
/* Initialize the timer/counter. */
tc_init_waveform(TIMER, &waveform_opt);
/* calculate how faster the timer with current clk freq compared to
* timer with 1Mhz */
timer_multiplier = sysclk_get_peripheral_bus_hz(TIMER) / DEF_1MHZ;
/* */
timer_multiplier = timer_multiplier >> 1;
configure_irq_handler();
tmr_enable_ovf_interrupt();
tmr_disable_cc_interrupt();
tc_start(TIMER, TIMER_CHANNEL_ID);
return timer_multiplier;
}
/*! \brief to disable compare interrupt
*/
void tmr_disable_cc_interrupt(void)
{
tc_interrupt.cpcs = 0;
tc_configure_interrupts(TIMER, TIMER_CHANNEL_ID, &tc_interrupt);
}
/**
* \brief DSP task core function.
*
* \param pvParameters Junk parameter.
*/
static void dsp_task(void *pvParameters)
{
uint32_t i, j;
uint32_t adc_potentiometer = 0;
const float32_t display_factor = 700;
float32_t bin;
float32_t tmp;
/* Just to avoid compiler warnings. */
UNUSED(pvParameters);
/* Wait for user to read instructions. */
WAIT_FOR_TOUCH_EVENT;
dsp_configure_button2();
dsp_configure_tc();
dsp_configure_adc();
dsp_configure_dacc();
dsp_sin_init();
/* Enable PDC transfer. */
dsp_clean_buffer(dacc_out_buffer[0], SAMPLE_BLOCK_SIZE);
dsp_clean_buffer(dacc_out_buffer[1], SAMPLE_BLOCK_SIZE);
dsp_clean_buffer(dacc_out_buffer[2], SAMPLE_BLOCK_SIZE);
g_pdc_packet.ul_addr = (uint32_t) dacc_out_buffer[0];
g_pdc_packet.ul_size = SAMPLE_BLOCK_SIZE;
g_pdc_nextpacket.ul_addr = (uint32_t) dacc_out_buffer[1];
g_pdc_nextpacket.ul_size = SAMPLE_BLOCK_SIZE;
pdc_tx_init(dacc_pdc, &g_pdc_packet, &g_pdc_nextpacket);
pdc_enable_transfer(dacc_pdc, PERIPH_PTCR_TXTEN);
/* Start Timer counter 0 channel 0 for ADC-DACC trigger. */
tc_start(TC0, 1);
/** DSP task loop. */
while (1) {
/* Using input wave signal. */
if (g_mode_select == 1) {
if (xSemaphoreTake(dacc_notification_semaphore,
max_block_time_ticks)) {
/* Copy dsp_sfx into wav_in_buffer and prepare Q15 format. */
for (i = 0, j = 0; i < 512; ++j) {
tmp = (((dsp_sfx[offset] - (float) 128)) / 100);
/* Store Audio sample real part in memory. */
wav_in_buffer[i++] = tmp;
/* Store Audio sample imaginary part in memory. */
wav_in_buffer[i++] = 0;
/* Prepare buffer for DACC. */
dacc_out_buffer[cur_dac_buffer][j] = (uint16_t)((tmp * 100
* sin_buffer[slider_pos][j]) + 128);
/* Update the wave file offset pointer. */
if (offset < dsp_sfx_size - 1) {
offset++;
} else {
offset = WAVE_OFFSET;
}
}
} else {
/* Ensure we take the semaphore. */
continue;
}
} else {
/* Using generated input sinus signal. */
if (xSemaphoreTake(dacc_notification_semaphore,
max_block_time_ticks)) {
/*
* Read potentiometer value and generate
* sinus signal accordingly.
*/
adc_potentiometer_old = adc_potentiometer;
adc_potentiometer = (afec_channel_get_value(AFEC0,
ADC_CHANNEL_POTENTIOMETER));
adc_potentiometer = adc_potentiometer * 10000 / 4096;
if (adc_potentiometer > adc_potentiometer_old &&
adc_potentiometer -
adc_potentiometer_old < ADC_POTENTIOMETER_NOISE) {
adc_potentiometer = adc_potentiometer_old;
} else if (adc_potentiometer_old > adc_potentiometer &&
adc_potentiometer_old -
adc_potentiometer < ADC_POTENTIOMETER_NOISE) {
adc_potentiometer = adc_potentiometer_old;
}
/* Generate the sinus signal. */
dsp_sin_input(adc_potentiometer);
/* Prepare buffer for DACC. */
for (i = 0, j = 0; i < 512; ++j, i += 2) {
/*
* 2048 is the 0 position for DACC.
* 50 is an amplification factor.
*/
dacc_out_buffer[cur_dac_buffer][j] =
(uint16_t)((wav_in_buffer[i] * sin_buffer[slider_pos][j])
* 50 + 2048);
}
}
}
afec_start_software_conversion(AFEC0);
/* Perform FFT and bin Magnitude calculation */
arm_float_to_q15(wav_in_buffer, cfft_q15, SAMPLE_BLOCK_SIZE * 2);
arm_cfft_radix4_init_q15(&cfft_instance, SAMPLE_BLOCK_SIZE, 0, 1);
arm_cfft_radix4_q15(&cfft_instance, cfft_q15);
arm_cmplx_mag_q15(cfft_q15, mag_in_buffer_q15, SAMPLE_BLOCK_SIZE);
arm_q15_to_float(mag_in_buffer_q15, mag_in_buffer, 128);
/*
* Prepare bins rendering for web page and display.
* Limit to 99, even if we got 128 magnitudes to display.
* Bins are printed using col, incremented by mean of 2 to keep
* a clean rendering. Hence we cannot render all the magnitudes,
* because of the screen width. It would require a 128*2 space.
*/
for (i = 0; i < 99; ++i) {
bin = (mag_in_buffer[i] * display_factor);
if (bin > 0) {
if (bin > 98) {
bin = 98;
}
mag_in_buffer_int[i] = (uint32_t)bin;
} else {
mag_in_buffer_int[i] = 0;
}
}
/* Notify GFX task to start refreshing screen (if necessary). */
if (g_mode_select == 1 || (g_mode_select == 0 &&
adc_potentiometer != adc_potentiometer_old)) {
xSemaphoreGive(gfx_notification_semaphore);
}
}
}
// [main_tc_configure]
static void configure_tc(void)
{
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual est'a em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/*
* Ativa o clock do periférico TC 0
*
*/
pmc_enable_periph_clk(ID_TC0);
/*
* Configura TC para operar no modo de comparação e trigger RC
* devemos nos preocupar com o clock em que o TC irá operar !
*
* Cada TC possui 3 canais, escolher um para utilizar.
*
* Configurações de modo de operação :
* #define TC_CMR_ABETRG (0x1u << 10) : TIOA or TIOB External Trigger Selection
* #define TC_CMR_CPCTRG (0x1u << 14) : RC Compare Trigger Enable
* #define TC_CMR_WAVE (0x1u << 15) : Waveform Mode
*
* Configurações de clock :
* #define TC_CMR_TCCLKS_TIMER_CLOCK1 : Clock selected: internal MCK/2 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK2 : Clock selected: internal MCK/8 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK3 : Clock selected: internal MCK/32 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK4 : Clock selected: internal MCK/128 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK5 : Clock selected: internal SLCK clock signal
*
* MCK = 120_000_000
* SLCK = 32_768 (rtc)
*
* Uma opção para achar o valor do divisor é utilizar a funcao
* tc_find_mck_divisor()
*/
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
/*
* Aqui devemos configurar o valor do RC que vai trigar o reinicio da contagem
* devemos levar em conta a frequência que queremos que o TC gere as interrupções
* e tambem a frequencia com que o TC está operando.
*
* Devemos configurar o RC para o mesmo canal escolhido anteriormente.
*
* ^
* | Contador (incrementado na frequencia escolhida do clock)
* |
* | Interrupcao
* |------#----------- RC
* | /
* | /
* | /
* |-----------------> t
*
*
*/
tc_write_rc(TC0, 0, 8192);
/*
* Devemos configurar o NVIC para receber interrupções do TC
*/
NVIC_EnableIRQ(ID_TC0);
/*
* Opções possíveis geradoras de interrupção :
*
* Essas configurações estão definidas no head : tc.h
*
* #define TC_IER_COVFS (0x1u << 0) Counter Overflow
* #define TC_IER_LOVRS (0x1u << 1) Load Overrun
* #define TC_IER_CPAS (0x1u << 2) RA Compare
* #define TC_IER_CPBS (0x1u << 3) RB Compare
* #define TC_IER_CPCS (0x1u << 4) RC Compare
* #define TC_IER_LDRAS (0x1u << 5) RA Loading
* #define TC_IER_LDRBS (0x1u << 6) RB Loading
* #define TC_IER_ETRGS (0x1u << 7) External Trigger
*/
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
tc_start(TC0,0);
}
/*! \brief Configure timer ISR to fire regularly.
*/
void
init_timer (void)
{
volatile avr32_tc_t *tc = EXAMPLE_TC;
/* options for waveform generation. */
static const tc_waveform_opt_t WAVEFORM_OPT = {
.channel = EXAMPLE_TC_CHANNEL, /* Channel selection. */
.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
.beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode with automatic trigger(reset) on RC compare. */
.enetrg = 0u, /* External event trigger enable. */
.eevt = 0u, /* External event selection. */
.eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
.cpcdis = 0u, /* Counter disable when RC compare. */
.cpcstop = 0u, /* Counter clock stopped with RC compare. */
.burst = 0u, /* Burst signal selection. */
.clki = 0u, /* Clock inversion. */
.tcclks = TC_CLOCK_SOURCE_TC3 /* Internal source clock 3, connected to fPBA / 8. */
};
static const tc_interrupt_t TC_INTERRUPT = {
.etrgs = 0u,
.ldrbs = 0u,
.ldras = 0u,
.cpcs = 1u,
.cpbs = 0u,
.cpas = 0u,
.lovrs = 0u,
.covfs = 0u
};
/* initialize the timer/counter. */
tc_init_waveform (tc, &WAVEFORM_OPT);
/* set the compare triggers. */
tc_write_rc (tc, EXAMPLE_TC_CHANNEL, EXAMPLE_RC_VALUE);
/* configure Timer interrupt. */
tc_configure_interrupts (tc, EXAMPLE_TC_CHANNEL, &TC_INTERRUPT);
/* start the timer/counter. */
tc_start (tc, EXAMPLE_TC_CHANNEL);
}
/*! \brief Timer compare ISR.
*/
#if (defined __GNUC__)
__attribute__ ((__interrupt__))
#elif (defined __ICCAVR32__)
__interrupt
#endif
static void
tc_irq (void)
{
/* update the current time */
current_time_ms_touch++;
/* every 25th ms */
if ((current_time_ms_touch % measurement_period_ms) == 0u)
{
/* set flag: it's time to measure touch */
time_to_measure_touch = 1u;
}
/* clear the interrupt flag. This is a side effect of reading the TC SR. */
tc_read_sr (EXAMPLE_TC, EXAMPLE_TC_CHANNEL);
}
/**
* \brief TC Initialization
*
* Initializes and start the TC module with the following:
* - Counter in Up mode with automatic reset on RC compare match.
* - fPBA/8 is used as clock source for TC
* - Enables RC compare match interrupt
* \param tc Base address of the TC module
*/
static void tc_init(volatile avr32_tc_t *tc)
{
// Options for waveform generation.
static const tc_waveform_opt_t waveform_opt = {
// Channel selection.
.channel = EXAMPLE_TC_CHANNEL,
// Software trigger effect on TIOB.
.bswtrg = TC_EVT_EFFECT_NOOP,
// External event effect on TIOB.
.beevt = TC_EVT_EFFECT_NOOP,
// RC compare effect on TIOB.
.bcpc = TC_EVT_EFFECT_NOOP,
// RB compare effect on TIOB.
.bcpb = TC_EVT_EFFECT_NOOP,
// Software trigger effect on TIOA.
.aswtrg = TC_EVT_EFFECT_NOOP,
// External event effect on TIOA.
.aeevt = TC_EVT_EFFECT_NOOP,
// RC compare effect on TIOA.
.acpc = TC_EVT_EFFECT_NOOP,
/*
* RA compare effect on TIOA.
* (other possibilities are none, set and clear).
*/
.acpa = TC_EVT_EFFECT_NOOP,
/*
* Waveform selection: Up mode with automatic trigger(reset)
* on RC compare.
*/
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,
// External event trigger enable.
.enetrg = false,
// External event selection.
.eevt = 0,
// External event edge selection.
.eevtedg = TC_SEL_NO_EDGE,
// Counter disable when RC compare.
.cpcdis = false,
// Counter clock stopped with RC compare.
.cpcstop = false,
// Burst signal selection.
.burst = false,
// Clock inversion.
.clki = false,
// Internal source clock 3, connected to fPBA / 8.
.tcclks = TC_CLOCK_SOURCE_TC3
};
// Options for enabling TC interrupts
static const tc_interrupt_t tc_interrupt = {
.etrgs = 0,
.ldrbs = 0,
.ldras = 0,
.cpcs = 1, // Enable interrupt on RC compare alone
.cpbs = 0,
.cpas = 0,
.lovrs = 0,
.covfs = 0
};
// Initialize the timer/counter.
tc_init_waveform(tc, &waveform_opt);
/*
* Set the compare triggers.
* We configure it to count every 1 milliseconds.
* We want: (1 / (fPBA / 8)) * RC = 1 ms, hence RC = (fPBA / 8) / 1000
* to get an interrupt every 10 ms.
*/
tc_write_rc(tc, EXAMPLE_TC_CHANNEL, (sysclk_get_pba_hz() / 8 / 1000));
// configure the timer interrupt
tc_configure_interrupts(tc, EXAMPLE_TC_CHANNEL, &tc_interrupt);
// Start the timer/counter.
tc_start(tc, EXAMPLE_TC_CHANNEL);
}
/*! \brief Main function:
* - Configure the CPU to run at 12MHz
* - Configure the USART
* - Register the TC interrupt (GCC only)
* - Configure, enable the CPCS (RC compare match) interrupt, and start a
* TC channel in waveform mode
* - In an infinite loop, update the USART message every second.
*/
int main(void)
{
volatile avr32_tc_t *tc = EXAMPLE_TC;
uint32_t timer = 0;
/**
* \note the call to sysclk_init() will disable all non-vital
* peripheral clocks, except for the peripheral clocks explicitly
* enabled in conf_clock.h.
*/
sysclk_init();
// Enable the clock to the selected example Timer/counter peripheral module.
sysclk_enable_peripheral_clock(EXAMPLE_TC);
// Initialize the USART module for trace messages
init_dbg_rs232(sysclk_get_pba_hz());
// Disable the interrupts
cpu_irq_disable();
#if defined (__GNUC__)
// Initialize interrupt vectors.
INTC_init_interrupts();
// Register the RTC interrupt handler to the interrupt controller.
INTC_register_interrupt(&tc_irq, EXAMPLE_TC_IRQ, EXAMPLE_TC_IRQ_PRIORITY);
#endif
// Enable the interrupts
cpu_irq_enable();
// Initialize the timer module
tc_init(tc);
while (1) {
// Update the display on USART every second.
if ((update_timer) && (!(tc_tick%1000))) {
timer++;
// Set cursor to the position (1; 5)
print_dbg("\x1B[5;1H");
// Print the timer value
print_dbg("ATMEL AVR UC3 - Timer/Counter Example 3\n\rTimer: ");
print_dbg_ulong(timer);
print_dbg(" s");
// Reset the timer update flag to wait till next timer interrupt
update_timer = false;
}
}
}
/**
* \brief TC Initialization
*
* Initializes and start the TC module with the following:
* - Counter in Up mode with automatic reset on RC compare match.
* - fPBA/8 is used as clock source for TC
* - Enables RC compare match interrupt
* \param tc Base address of the TC module
*/
static void tc_init(volatile avr32_tc_t *tc)
{
// Options for waveform generation.
static const tc_waveform_opt_t waveform_opt = {
// Channel selection.
.channel = EXAMPLE_TC_CHANNEL,
// Software trigger effect on TIOB.
.bswtrg = TC_EVT_EFFECT_NOOP,
// External event effect on TIOB.
.beevt = TC_EVT_EFFECT_NOOP,
// RC compare effect on TIOB.
.bcpc = TC_EVT_EFFECT_NOOP,
// RB compare effect on TIOB.
.bcpb = TC_EVT_EFFECT_NOOP,
// Software trigger effect on TIOA.
.aswtrg = TC_EVT_EFFECT_NOOP,
// External event effect on TIOA.
.aeevt = TC_EVT_EFFECT_NOOP,
// RC compare effect on TIOA.
.acpc = TC_EVT_EFFECT_NOOP,
/* RA compare effect on TIOA.
* (other possibilities are none, set and clear).
*/
.acpa = TC_EVT_EFFECT_NOOP,
/* Waveform selection: Up mode with automatic trigger(reset)
* on RC compare.
*/
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,
// External event trigger enable.
.enetrg = false,
// External event selection.
.eevt = 0,
// External event edge selection.
.eevtedg = TC_SEL_NO_EDGE,
// Counter disable when RC compare.
.cpcdis = false,
// Counter clock stopped with RC compare.
.cpcstop = false,
// Burst signal selection.
.burst = false,
// Clock inversion.
.clki = false,
// Internal source clock 3, connected to fPBA / 8.
.tcclks = TC_CLOCK_SOURCE_TC3
};
// Options for enabling TC interrupts
static const tc_interrupt_t tc_interrupt = {
.etrgs = 0,
.ldrbs = 0,
.ldras = 0,
.cpcs = 1, // Enable interrupt on RC compare alone
.cpbs = 0,
.cpas = 0,
.lovrs = 0,
.covfs = 0
};
// Initialize the timer/counter.
tc_init_waveform(tc, &waveform_opt);
/*
* Set the compare triggers.
* We configure it to count every 10 milliseconds.
* We want: (1 / (fPBA / 8)) * RC = 10 ms, hence RC = (fPBA / 8) / 100
* to get an interrupt every 10 ms.
*/
tc_write_rc(tc, EXAMPLE_TC_CHANNEL, (sysclk_get_pba_hz() / 8 / 100));
// configure the timer interrupt
tc_configure_interrupts(tc, EXAMPLE_TC_CHANNEL, &tc_interrupt);
// Start the timer/counter.
tc_start(tc, EXAMPLE_TC_CHANNEL);
}
/**
* \brief Main function
*
* Main function performs the following:
* - Configure the TC Module
* - Register the TC interrupt
* - Configure, enable the CPCS (RC compare match) interrupt,
* - and start a TC channel in waveform mode
*/
int main(void)
{
volatile avr32_tc_t *tc = EXAMPLE_TC;
uint32_t timer = 0;
/**
* \note the call to sysclk_init() will disable all non-vital
* peripheral clocks, except for the peripheral clocks explicitly
* enabled in conf_clock.h.
*/
sysclk_init();
// Enable the clock to the selected example Timer/counter peripheral module.
sysclk_enable_peripheral_clock(EXAMPLE_TC);
// Disable the interrupts
cpu_irq_disable();
// Initialize interrupt vectors.
INTC_init_interrupts();
// Register the RTC interrupt handler to the interrupt controller.
INTC_register_interrupt(&tc_irq, EXAMPLE_TC_IRQ, EXAMPLE_TC_IRQ_PRIORITY);
// Enable the interrupts
cpu_irq_enable();
// Initialize the timer module
tc_init(tc);
while(1) {
// Update the timer every 10 milli second.
if ((update_timer)) {
timer++;
/*
* TODO: Place a breakpoint here and watch the update of timer
* variable in the Watch Window.
*/
// Reset the timer update flag to wait till next timer interrupt
update_timer = false;
}
}
}
int main(void)
{
//-------------------------USART INTERRUPT REGISTRATION.------------//
// Set Clock: Oscillator needs to initialized once: First
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
// -------------- USART INIT -----------------------------------------------
static const gpio_map_t USART_GPIO_MAP =
{
{AVR32_USART0_RXD_0_0_PIN, AVR32_USART0_RXD_0_0_FUNCTION},
{AVR32_USART0_TXD_0_0_PIN, AVR32_USART0_TXD_0_0_FUNCTION}
};
// USART options.
static const usart_options_t USART_OPTIONS =
{
.baudrate = USART_BAUDRATE,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = USART_NORMAL_CHMODE
};
// Assign GPIO to USART
gpio_enable_module(USART_GPIO_MAP, sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0]));
// Init USART
usart_init_rs232(USART_0, &USART_OPTIONS, FOSC0);
Disable_global_interrupt();
INTC_init_interrupts(); // Init Interrupt Table: Once at first
// Register USART Interrupt (hinzufügen)
INTC_register_interrupt(&usart_int_handler, AVR32_USART0_IRQ, AVR32_INTC_INT0);
USART_0->ier = AVR32_USART_IER_RXRDY_MASK; // Activate ISR on RX Line
Enable_global_interrupt();
// -----------------------------------------------------------------------------------
// -------------------------- Display INIT ----------------------------------
// Map SPI Pins
static const gpio_map_t DIP204_SPI_GPIO_MAP =
{
{DIP204_SPI_SCK_PIN, DIP204_SPI_SCK_FUNCTION }, // SPI Clock.
{DIP204_SPI_MISO_PIN, DIP204_SPI_MISO_FUNCTION}, // MISO.
{DIP204_SPI_MOSI_PIN, DIP204_SPI_MOSI_FUNCTION}, // MOSI.
{DIP204_SPI_NPCS_PIN, DIP204_SPI_NPCS_FUNCTION} // Chip Select NPCS.
};
// add the spi options driver structure for the LCD DIP204
spi_options_t spiOptions =
{
.reg = DIP204_SPI_NPCS,
.baudrate = 1000000,
.bits = 8,
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 1,
.spi_mode = 0,
.modfdis = 1
};
// SPI Inits: Assign I/Os to SPI
gpio_enable_module(DIP204_SPI_GPIO_MAP,
sizeof(DIP204_SPI_GPIO_MAP) / sizeof(DIP204_SPI_GPIO_MAP[0]));
// Initialize as master
spi_initMaster(DIP204_SPI, &spiOptions);
// Set selection mode: variable_ps, pcs_decode, delay
spi_selectionMode(DIP204_SPI, 0, 0, 0);
// Enable SPI
spi_enable(DIP204_SPI);
// setup chip registers
spi_setupChipReg(DIP204_SPI, &spiOptions, FOSC0);
// initialize delay driver: Muss vor dip204_init() ausgeführt werden
delay_init( FOSC0 );
// initialize LCD
dip204_init(backlight_PWM, TRUE);
// ---------------------------------------------------------------------------------------
// ----------------- Timer Counter Init ---------------------------------
// Timer Configs: Options for waveform generation.
static const tc_waveform_opt_t WAVEFORM_OPT =
{
.channel = TC_CHANNEL, // Channel selection.
.bswtrg = TC_EVT_EFFECT_NOOP, // Software trigger effect on TIOB.
.beevt = TC_EVT_EFFECT_NOOP, // External event effect on TIOB.
.bcpc = TC_EVT_EFFECT_NOOP, // RC compare effect on TIOB.
.bcpb = TC_EVT_EFFECT_NOOP, // RB compare effect on TIOB.
.aswtrg = TC_EVT_EFFECT_NOOP, // Software trigger effect on TIOA.
.aeevt = TC_EVT_EFFECT_NOOP, // External event effect on TIOA.
.acpc = TC_EVT_EFFECT_NOOP, // RC compare effect on TIOA: toggle.
.acpa = TC_EVT_EFFECT_NOOP, // RA compare effect on TIOA: toggle
.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,// Count till RC and reset (S. 649): Waveform selection
.enetrg = FALSE, // External event trigger enable.
.eevt = 0, // External event selection.
.eevtedg = TC_SEL_NO_EDGE, // External event edge selection.
.cpcdis = FALSE, // Counter disable when RC compare.
.cpcstop = FALSE, // Counter clock stopped with RC compare.
.burst = FALSE, // Burst signal selection.
.clki = FALSE, // Clock inversion.
.tcclks = TC_CLOCK_SOURCE_TC3 // Internal source clock 3, connected to fPBA / 8.
};
// TC Interrupt Enable Register
static const tc_interrupt_t TC_INTERRUPT =
{ .etrgs = 0, .ldrbs = 0, .ldras = 0, .cpcs = 1, .cpbs = 0, .cpas = 0, .lovrs = 0, .covfs = 0
};
// 0 = No Effect | 1 = Enable ( CPCS = 1 enables the RC Compare Interrupt )
// ***************** Timer Setup ***********************************************
// Initialize the timer/counter.
tc_init_waveform(tc, &WAVEFORM_OPT); // Initialize the timer/counter waveform.
// Set the compare triggers.
tc_write_rc(tc, TC_CHANNEL, RC); // Set RC value.
tc_configure_interrupts(tc, TC_CHANNEL, &TC_INTERRUPT);
// Start the timer/counter.
tc_start(tc, TC_CHANNEL); // And start the timer/counter.
// *******************************************************************************
Disable_global_interrupt();
// Register TC Interrupt
INTC_register_interrupt(&tc_irq, AVR32_TC_IRQ0, AVR32_INTC_INT3);
Enable_global_interrupt();
// ---------------------------------------------------------------------------------------
imu_init();
//-------------------------------TWI R/W ---------------------------------------------------
sensorDaten imu_data = {0};
char disp1[30], disp2[30], disp3[30], disp4[30];
short GX,GY,GZ, AX, AY, AZ; //shifted comlete Data
RPY currMoveRPY;
Quaternion currQuat;
currQuat.q0 = 1.0;
currQuat.q1 = 0;
currQuat.q2 = 0;
currQuat.q3 = 0;
Quaternion deltaQuat;
RotMatrix rot = {0};
RPY reconverted;
calibrate_all(&imu_data);
while(1){
if(exe){
exe = false;
read_sensor(&imu_data);
AX = imu_data.acc_x + imu_data.acc_x_bias;
AY = imu_data.acc_y + imu_data.acc_y_bias;
AZ = imu_data.acc_z + imu_data.acc_z_bias;
GX = imu_data.gyro_x + imu_data.gyro_x_bias;
GY = imu_data.gyro_y + imu_data.gyro_y_bias;
GZ = imu_data.gyro_z + imu_data.gyro_z_bias;
//convert to 1G
float ax = (float)AX * (-4.0);
float ay = (float)AY * (-4.0); //wegen 2^11= 2048, /2 = 1024 entspricht 4G -> 1G = (1024/4)
float az = (float)AZ * (-4.0);
//convert to 1°/s
gx = ((float)GX/ 14.375); // in °/s
gy = ((float)GY/ 14.375);
gz = ((float)GZ/ 14.375);
//Integration over time
dGx = (gx*0.03);
dGy = (gy*0.03);
dGz = (gz*0.03);
currMoveRPY.pitch = -dGx;
currMoveRPY.roll = dGy;
currMoveRPY.yaw = dGz;
//aufaddieren auf den aktuellen Winkel IN GRAD
gxDeg += dGx;
gyDeg += dGy;
gzDeg += dGz;
//RPY in Quaternion umwandeln
RPYtoQuat(&deltaQuat, &currMoveRPY);
//normieren
normQuat(&deltaQuat);
//aufmultiplizeiren
quatMultiplication(&deltaQuat, &currQuat, &currQuat);
//nochmal normieren
normQuat(&currQuat);
//rücktransformation nicht nötig!!
char send[80];
sprintf(send,"$,%f,%f,%f,%f,#", currQuat.q0, currQuat.q1, currQuat.q2, currQuat.q3);
usart_write_line(USART_0,send);
sprintf(disp1,"q0:%.3f, GX:%3.0f",currQuat.q0,gxDeg);
sprintf(disp2,"q1:%.3f, GY:%3.0f",currQuat.q1, gyDeg);
sprintf(disp3,"q2:%.3f, GZ:%3.0f",currQuat.q2, gzDeg);
sprintf(disp4,"q3:%.3f",currQuat.q3);
dip204_clear_display();
dip204_set_cursor_position(1,1);
dip204_write_string(disp1);
dip204_set_cursor_position(1,2);
dip204_write_string(disp2);
dip204_set_cursor_position(1,3);
dip204_write_string(disp3);
dip204_set_cursor_position(1,4);
dip204_write_string(disp4);
//sprintf(data,"TEST:%s",high);
//print_dbg(data);
}
}
}
/**
* \brief adc12 Application entry point.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
uint32_t i;
uint8_t uc_key;
/* Initialize the SAM system. */
sysclk_init();
board_init();
configure_console();
/* Output example information. */
puts(STRING_HEADER);
puts("Configure system tick to get 1ms tick period.\r");
if (SysTick_Config(sysclk_get_cpu_hz() / 1000)) {
puts("-F- Systick configuration error\r");
while (1);
}
/* Set default ADC test mode. */
memset((void *)&g_adc_test_mode, 0, sizeof(g_adc_test_mode));
g_adc_test_mode.uc_trigger_mode = TRIGGER_MODE_SOFTWARE;
g_adc_test_mode.uc_pdc_en = 1;
g_adc_test_mode.uc_sequence_en = 0;
g_adc_test_mode.uc_gain_en = 0;
g_adc_test_mode.uc_offset_en = 0;
display_menu();
start_adc();
puts("Press any key to display configuration menu.\r");
while (1) {
/* ADC software trigger per 1s */
if (g_adc_test_mode.uc_trigger_mode == TRIGGER_MODE_SOFTWARE) {
mdelay(1000);
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
adc_start(ADC);
#elif SAM3U
#ifdef ADC_12B
adc12b_start(ADC12B);
#else
adc_start(ADC);
#endif
#endif
}
/* Check if the user enters a key. */
if (!uart_read(CONSOLE_UART, &uc_key)) {
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
adc_disable_interrupt(ADC, 0xFFFFFFFF); /* Disable all adc interrupt. */
#elif SAM3U
#ifdef ADC_12B
adc12b_disable_interrupt(ADC12B, 0xFFFFFFFF); /* Disable all adc interrupt. */
#else
adc_disable_interrupt(ADC, 0xFFFFFFFF); /* Disable all adc interrupt. */
#endif
#endif
tc_start(TC0, 0); /* Stop the Timer. */
#if SAM3S || SAM3U || SAM3XA || SAM4S
pwm_channel_disable(PWM, 0);
#endif
display_menu();
set_adc_test_mode();
start_adc();
puts("Press any key to display configuration menu.\r");
}
/* Check if ADC sample is done. */
if (g_adc_sample_data.us_done == ADC_DONE_MASK) {
for (i = 0; i < NUM_CHANNELS; i++) {
printf("CH%02d: %04d mv. ",
(int)g_adc_sample_data.uc_ch_num[i],
(int)(g_adc_sample_data.
us_value[i] *
VOLT_REF /
MAX_DIGITAL));
}
puts("\r");
g_adc_sample_data.us_done = 0;
}
}
}
