static void SD_HW_InitializeClock(void) { //===================================================== // SD Channel Control Register Clock Enable //===================================================== tca_ckc_setiopwdn(RB_SDMMCCHANNELCONTROLLER,0); // SD Channel Control Register Clock Enable if(SD_HW_IsSdHostNeeded(0)) { //===================================================== // SD Host Controller #0 Clock Enable //===================================================== tca_ckc_setperi(PERI_SDMMC0, ENABLE, 480000); _tca_delay(); tca_ckc_setiopwdn(RB_SDMMC0CONTROLLER,0); } if(SD_HW_IsSdHostNeeded(1)) { //===================================================== // SD Host Controller #1 Clock Enable //===================================================== tca_ckc_setperi(PERI_SDMMC1, ENABLE, 480000); _tca_delay(); tca_ckc_setiopwdn(RB_SDMMC1CONTROLLER,0); } if(SD_HW_IsSdHostNeeded(2)) { //===================================================== // SD Host Controller #2 Clock Enable //===================================================== tca_ckc_setperi(PERI_SDMMC2, ENABLE, 480000); _tca_delay(); tca_ckc_setiopwdn(RB_SDMMC2CONTROLLER,0); } if(SD_HW_IsSdHostNeeded(3)) { //===================================================== // SD Host Controller #3 Clock Enable //===================================================== tca_ckc_setperi(PERI_SDMMC3, ENABLE, 480000); _tca_delay(); tca_ckc_setiopwdn(RB_SDMMC3CONTROLLER,0); } }
static void set_adc_clock(int peri_adc) { int adc = 0; tca_ckc_setperi(PERI_ADC, MHz, peri_adc, PCDIRECTXIN); adc = tca_ckc_getperi(PERI_ADC); dbg("[%s]adc = %d\n", __func__, adc/10000); }
static int set_gpsb2_clock(int peri_gpsb2) { int gpsb2 = 0; tca_ckc_setperi(PERI_GPSB2, KHz, peri_gpsb2, PCDIRECTPLL0); gpsb2 = tca_ckc_getperi(PERI_GPSB2); dbg("[%s]gpsb2 = %d\n", __func__, gpsb2/10); }
static int set_gpsb3_clock(int peri_gpsb3) { int gpsb3 = 0; tca_ckc_setperi(PERI_GPSB3, KHz, peri_gpsb3, PCDIRECTPLL0); gpsb3 = tca_ckc_getperi(PERI_GPSB3); dbg("[%s]gpsb3 = %d\n", __func__, gpsb3/10); }
static void set_usb_clock(int peri_usb) { tca_ckc_setperi(PERI_USB11H, MHz, peri_usb, PCCLKFROM48M); #ifdef DEBUG int usb = 0; usb = tca_ckc_getperi(PERI_USB11H); dbg("[%s]usb = %d\n", __func__, usb/10000); #endif }
static void set_uart3_clock(int peri_uart3) { tca_ckc_setperi(PERI_UART3, MHz, peri_uart3, PCDIRECTPLL1); #ifdef DEBUG int uart3 = 0; uart3 = tca_ckc_getperi(PERI_UART3); dbg("[%s]uart3 = %d\n", __func__, uart3/10000); #endif }
static void set_uart2_clock(int peri_uart2) { tca_ckc_setperi(PERI_UART2, MHz, peri_uart2, PCDIRECTPLL1); #ifdef DEBUG int uart2 = 0; uart2 = tca_ckc_getperi(PERI_UART2); dbg("[%s]uart2 = %d\n", __func__, uart2/10000); #endif }
static void set_uart1_clock(int peri_uart1) { tca_ckc_setperi(PERI_UART1, MHz, peri_uart1, PCDIRECTPLL1); #ifdef DEBUG int uart1 = 0; uart1 = tca_ckc_getperi(PERI_UART1); dbg("[%s]uart1 = %d\n", __func__, uart1/10000); #endif }
static void set_uart0_clock(int peri_uart0) { tca_ckc_setperi(PERI_UART0, MHz, peri_uart0, PCDIRECTPLL1); #ifdef DEBUG int uart0 = 0; uart0 = tca_ckc_getperi(PERI_UART0); dbg("[%s]uart0 = %d\n", __func__, uart0/1000); #endif }
static void set_i2c_clock(int peri_i2c) { tca_ckc_setperi(PERI_I2C, MHz, peri_i2c, PCDIRECTXIN); #ifdef DEBUG int i2c = 0; i2c = tca_ckc_getperi(PERI_I2C); dbg("[%s]i2c = %d\n", __func__, i2c/10000); #endif }
static void set_lcd_clock(int peri_lcd) { tca_ckc_setperi(PERI_LCD, MHz, peri_lcd, PCDIRECTPLL2); #ifdef DEBUG int lcd = 0; printk("input lcd freq = %d\n", peri_lcd); lcd = tca_ckc_getperi(PERI_LCD); dbg("[%s]lcd = %d\n", __func__, lcd/10000); #endif }
static void set_sdmmc_clock(int peri_sdmmc) { tca_ckc_setperi(PERI_SDMMC, MHz, peri_sdmmc, PCDIRECTPLL1); #ifdef DEBUG int sdmmc = 0; sdmmc = tca_ckc_getperi(PERI_SDMMC); dbg("[%s]sdmmc = %d\n", __func__, sdmmc/10000); #endif }
static void set_cam_clock(int peri_cam) { tca_ckc_setperi(PERI_CAM, MHz, peri_cam, PCDIRECTPLL2); #ifdef DEBUG int cam = 0; cam = tca_ckc_getperi(PERI_CAM); dbg("[%s]cam = %d\n", __func__, cam/10000); #endif }
static void set_spi0_clock(int peri_spi0) { tca_ckc_setperi(PERI_SPIMS0, KHz, peri_spi0, PCDIRECTPLL0); #ifdef DEBUG int spi0 = 0; spi0 = tca_ckc_getperi(PERI_SPIMS0); dbg("[%s]spi0 = %d\n", __func__, spi0/10); #endif }
static void set_spi1_clock(int peri_spi1) { tca_ckc_setperi(PERI_SPIMS1, KHz, peri_spi1, PCDIRECTPLL0); #ifdef DEBUG int spi1 = 0; spi1 = tca_ckc_getperi(PERI_SPIMS1); dbg("[%s]spi1 = %d\n", __func__, spi1/10); #endif }
static void set_gpsb1_clock(int peri_gpsb1) { tca_ckc_setperi(PERI_GPSB1, KHz, peri_gpsb1, PCDIRECTPLL0); #ifdef DEBUG int gpsb1 = 0; gpsb1 = tca_ckc_getperi(PERI_GPSB1); dbg("[%s]gpsb1 = %d\n", __func__, gpsb1/10); #endif }
static void set_gpsb0_clock(int peri_gpsb0) { tca_ckc_setperi(PERI_GPSB0, KHz, peri_gpsb0, PCDIRECTPLL0); #ifdef DEBUG int gpsb0 = 0; gpsb0 = tca_ckc_getperi(PERI_GPSB0); dbg("[%s]gpsb0 = %d\n", __func__, gpsb0/10); #endif }
static void set_scaler_clock(int peri_scaler) { tca_ckc_setperi(PERI_SCALER, MHz, peri_scaler, PCDIRECTPLL2); #ifdef DEBUG int scaler = 0; scaler = tca_ckc_getperi(PERI_SCALER); dbg("[%s]scaler = %d\n", __func__, scaler/10000); #endif }
static struct lcd_panel * lcdc_io_init(unsigned char lcdc_num) { struct lcd_panel *panel; unsigned int lclk; #if 0 // reset VIOD BITSET(pDDICfg->SWRESET, Hw3); BITSET(pDDICfg->SWRESET, Hw2); BITCLR(pDDICfg->SWRESET, Hw3); BITCLR(pDDICfg->SWRESET, Hw2); #endif// panel = tccfb_get_panel(); panel->dev.power_on = GPIO_LCD_ON; panel->dev.display_on = GPIO_LCD_DISPLAY; panel->dev.bl_on = GPIO_LCD_BL; panel->dev.reset = GPIO_LCD_RESET; panel->dev.lcdc_num = lcdc_num; panel->init(panel); if(lcdc_num) { tca_ckc_setperi(PERI_LCD1,ENABLE, panel->clk_freq * panel->clk_div); lclk = tca_ckc_getperi(PERI_LCD1); } else { tca_ckc_setperi(PERI_LCD0,ENABLE, panel->clk_freq * panel->clk_div); lclk = tca_ckc_getperi(PERI_LCD0); } printf("telechips tcc88xx %s lcdc:%d clk:%d set clk:%d \n", __func__, lcdc_num, panel->clk_freq, lclk); panel->set_power(panel, 1); printf("%s end\n", __func__); return panel; }
/***************************************************************************** Function Name : tcc_composite_set_lcd2tv() ******************************************************************************/ void tcc_composite_set_lcd2tv(COMPOSITE_MODE_TYPE type) { COMPOSITE_SPEC_TYPE spec; stLTIMING CompositeTiming; stLCDCTR LcdCtrlParam; PVIOC_DISP pDISPBase; PVIOC_WMIX pWIXBase; PVIOC_RDMA pRDMA; PDDICONFIG pDDICfg = (PDDICONFIG)tcc_p2v(HwDDI_CONFIG_BASE); unsigned int width, height; unsigned int lcd_ctrl = 0; unsigned int lcd_peri = 0; #define LCDC_CLK_DIV 1 tcc_composite_get_spec(type, &spec); #if (defined(CONFIG_CPU_FREQ_TCC92X) || defined (CONFIG_CPU_FREQ_TCC93XX)) && defined(CONFIG_CPU_FREQ) tcc_cpufreq_set_limit_table(>TvClockLimitTable, TCC_FREQ_LIMIT_TV, 1); #endif if(Composite_LCDC_Num) lcd_peri = PERI_LCD1; else lcd_peri = PERI_LCD0; VIOC_DISP_SWReset(Composite_LCDC_Num); BITSET(pDDICfg->PWDN.nREG, Hw1); // PWDN - TVE BITCLR(pDDICfg->SWRESET.nREG, Hw1); // SWRESET - TVE BITSET(pDDICfg->SWRESET.nREG, Hw1); // SWRESET - TVE BITSET(pDDICfg->NTSCPAL_EN.nREG, Hw0); // NTSCPAL_EN if(Composite_LCDC_Num) { pDISPBase = (VIOC_DISP *)tcc_p2v(HwVIOC_DISP1); pWIXBase =(VIOC_WMIX *)tcc_p2v(HwVIOC_WMIX1); } else { pDISPBase = (VIOC_DISP *)tcc_p2v(HwVIOC_DISP0); pWIXBase =(VIOC_WMIX *)tcc_p2v(HwVIOC_WMIX0); } tca_ckc_setperi(lcd_peri, ENABLE, 270000); width = spec.composite_lcd_width; height = spec.composite_lcd_height; CompositeTiming.lpw = spec.composite_LPW; CompositeTiming.lpc = spec.composite_LPC + 1; CompositeTiming.lswc = spec.composite_LSWC + 1; CompositeTiming.lewc = spec.composite_LEWC + 1; CompositeTiming.vdb = spec.composite_VDB; CompositeTiming.vdf = spec.composite_VDF; CompositeTiming.fpw = spec.composite_FPW1; CompositeTiming.flc = spec.composite_FLC1; CompositeTiming.fswc = spec.composite_FSWC1; CompositeTiming.fewc = spec.composite_FEWC1; CompositeTiming.fpw2 = spec.composite_FPW2; CompositeTiming.flc2 = spec.composite_FLC2; CompositeTiming.fswc2 = spec.composite_FSWC2; CompositeTiming.fewc2 = spec.composite_FEWC2; VIOC_DISP_SetTimingParam(pDISPBase, &CompositeTiming); memset(&LcdCtrlParam, NULL, sizeof(LcdCtrlParam)); LcdCtrlParam.r2ymd = 0; LcdCtrlParam.ckg = 1; LcdCtrlParam.id= 0; LcdCtrlParam.iv = 0; LcdCtrlParam.ih = 1; LcdCtrlParam.ip = 1; LcdCtrlParam.clen = 1; LcdCtrlParam.r2y = 1; LcdCtrlParam.pxdw = 6; LcdCtrlParam.dp = 0; LcdCtrlParam.ni = 0; LcdCtrlParam.tv = 1; LcdCtrlParam.opt = 0; LcdCtrlParam.stn = 0; LcdCtrlParam.evsel = 0; LcdCtrlParam.ovp = 0; if(Composite_LCDC_Num) LcdCtrlParam.advi = 1; else LcdCtrlParam.advi = 0; VIOC_DISP_SetControlConfigure(pDISPBase, &LcdCtrlParam); VIOC_DISP_SetSize(pDISPBase, width, height); VIOC_DISP_SetBGColor(pDISPBase, 0, 0 , 0); //VIOC_DISP_TurnOn(pDISPBase); VIOC_WMIX_SetOverlayPriority(pWIXBase, 0); VIOC_WMIX_SetBGColor(pWIXBase, 0x00, 0x00, 0x00, 0xff); VIOC_WMIX_SetSize(pWIXBase, width, height); VIOC_WMIX_SetPosition(pWIXBase, 0, 0, 0); VIOC_WMIX_SetChromaKey(pWIXBase, 0, 0, 0, 0, 0, 0xF8, 0xFC, 0xF8); VIOC_WMIX_SetUpdate(pWIXBase); if(Composite_LCDC_Num) { VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_SDVENC, VIOC_OUTCFG_DISP1); } else { VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_SDVENC, VIOC_OUTCFG_DISP0); } }
/************************************************************ * Function : clock_init_early() * Description : * - set pll/peri-clock and * - set fbus clock to low (1.0V level) ************************************************************/ void clock_init_early(void) { tca_ckc_init(); tca_ckc_setfbusctrl( FBUS_IO, ENABLE, 60000); /*FBUS_IO 6 MHz */ tca_ckc_setfbusctrl( FBUS_SMU, ENABLE, 60000); /*FBUS_SMU 6 MHz */ tca_ckc_setpll(5940000, 0); tca_ckc_setpll(5000000, 1); tca_ckc_setpll(7280000, 2); tca_ckc_setpll(6720000, 3); // tca_ckc_setpll(6000000, 4); // for memory bus // tca_ckc_setpll(6480000, 5); // for cpu // tca_ckc_setfbusctrl( FBUS_CPU, ENABLE, 4000000); /*FBUS_CPU 400 MHz */ // 1.0V // tca_ckc_setfbusctrl( FBUS_MEM, ENABLE, 1250000); /*FBUS_MEM 160 MHz */ tca_ckc_setfbusctrl( FBUS_DDI, ENABLE, 1250000); /*FBUS_DDI 290 MHz */ tca_ckc_setfbusctrl( FBUS_GPU, DISABLE, 1250000); /*FBUS_GRP 320 MHz */ tca_ckc_setfbusctrl( FBUS_IO, ENABLE, 720000); /*FBUS_IO 190 MHz */ tca_ckc_setfbusctrl( FBUS_VBUS, DISABLE, 990000); /*FBUS_VBUS 300 MHz */ tca_ckc_setfbusctrl( FBUS_VCORE, DISABLE, 1250000); /*FBUS_VCODEC 290 MHz */ tca_ckc_setfbusctrl( FBUS_HSIO, ENABLE, 1080000); /*FBUS_HSIO 240 MHz */ tca_ckc_setfbusctrl( FBUS_SMU, ENABLE, 1000000); /*FBUS_SMU 200 MHz */ // init Peri. Clock tca_ckc_setperi(PERI_TCX , DISABLE, 120000); tca_ckc_setperi(PERI_TCT , ENABLE, 120000); tca_ckc_setperi(PERI_TCZ , ENABLE, 120000); tca_ckc_setperi(PERI_LCD0 , DISABLE, 10000); tca_ckc_setperi(PERI_LCDSI0 , DISABLE, 10000); tca_ckc_setperi(PERI_LCD1 , ENABLE, 960000); tca_ckc_setperi(PERI_LCDSI1 , DISABLE, 10000); tca_ckc_setperi(PERI_RESERVED0 , DISABLE, 10000); tca_ckc_setperi(PERI_LCDTIMER , DISABLE, 10000); tca_ckc_setperi(PERI_JPEG , DISABLE, 10000); tca_ckc_setperi(PERI_RESERVED1 , DISABLE, 10000); tca_ckc_setperi(PERI_RESERVED2 , DISABLE, 10000); tca_ckc_setperi(PERI_GMAC , DISABLE, 10000); tca_ckc_setperi(PERI_USBOTG , DISABLE, 10000); tca_ckc_setperi(PERI_RESERVED3 , DISABLE, 10000); tca_ckc_setperi(PERI_OUT0 , DISABLE, 10000); tca_ckc_setperi(PERI_USB20H , DISABLE, 10000); tca_ckc_setperi(PERI_HDMI , DISABLE, 10000); tca_ckc_setperi(PERI_HDMIA , DISABLE, 10000); tca_ckc_setperi(PERI_OUT1 , DISABLE, 10000); tca_ckc_setperi(PERI_EHI , DISABLE, 10000); tca_ckc_setperi(PERI_SDMMC0 , DISABLE, 10000); tca_ckc_setperi(PERI_SDMMC1 , DISABLE, 10000); tca_ckc_setperi(PERI_SDMMC2 , DISABLE, 10000); tca_ckc_setperi(PERI_SDMMC3 , DISABLE, 10000); tca_ckc_setperi(PERI_ADAI1 , DISABLE, 10000); tca_ckc_setperi(PERI_ADAM1 , DISABLE, 10000); tca_ckc_setperi(PERI_SPDIF1 , DISABLE, 10000); tca_ckc_setperi(PERI_ADAI0 , DISABLE, 10000); tca_ckc_setperi(PERI_ADAM0 , DISABLE, 10000); tca_ckc_setperi(PERI_SPDIF0 , DISABLE, 10000); tca_ckc_setperi(PERI_PDM , DISABLE, 10000); tca_ckc_setperi(PERI_RESERVED4 , DISABLE, 10000); tca_ckc_setperi(PERI_ADC , ENABLE, 120000); tca_ckc_setperi(PERI_I2C0 , ENABLE, 40000); tca_ckc_setperi(PERI_I2C1 , ENABLE, 40000); tca_ckc_setperi(PERI_I2C2 , ENABLE, 40000); tca_ckc_setperi(PERI_I2C3 , ENABLE, 40000); tca_ckc_setperi(PERI_UART0 , ENABLE, 480000); tca_ckc_setperi(PERI_UART1 , DISABLE, 10000); tca_ckc_setperi(PERI_UART2 , DISABLE, 10000); tca_ckc_setperi(PERI_UART3 , DISABLE, 10000); tca_ckc_setperi(PERI_UART4 , DISABLE, 10000); tca_ckc_setperi(PERI_UART5 , DISABLE, 10000); tca_ckc_setperi(PERI_UART6 , DISABLE, 10000); tca_ckc_setperi(PERI_UART7 , DISABLE, 10000); tca_ckc_setperi(PERI_GPSB0 , DISABLE, 10000); tca_ckc_setperi(PERI_GPSB1 , DISABLE, 10000); tca_ckc_setperi(PERI_GPSB2 , DISABLE, 10000); tca_ckc_setperi(PERI_GPSB3 , DISABLE, 10000); tca_ckc_setperi(PERI_GPSB4 , DISABLE, 10000); tca_ckc_setperi(PERI_GPSB5 , DISABLE, 10000); }
static void lcdc_io_init_composite(unsigned char lcdc_num, unsigned char type) { unsigned int lcd_reg = 0; unsigned int width, height; stCOMPOSITE_SPEC spec; stLTIMING CompositeTiming; stLCDCTR LcdCtrlParam; PVIOC_DISP pDISPBase; PVIOC_WMIX pWIXBase; PVIOC_RDMA pRDMA; PDDICONFIG pDDICfg = (PDDICONFIG)HwDDI_CONFIG_BASE; PNTSCPAL pTVE = (PNTSCPAL)HwNTSCPAL_BASE; PNTSCPAL_ENCODER_CTRL pTVE_VEN = (PNTSCPAL_ENCODER_CTRL)HwNTSCPAL_ENC_CTRL_BASE; struct fbcon_config *fb_con; printf("%s, lcdc_num=%d, type=%d\n", __func__, lcdc_num, type); if(type >= LCDC_COMPOSITE_MAX) type = defalut_composite_resolution; composite_get_spec(type, &spec); fb_con = &fb_cfg; BITSET(pDDICfg->PWDN.nREG, Hw1); // PWDN - TVE BITCLR(pDDICfg->SWRESET.nREG, Hw1); // SWRESET - TVE BITSET(pDDICfg->SWRESET.nREG, Hw1); // SWRESET - TVE BITSET(pDDICfg->NTSCPAL_EN.nREG, Hw0); // NTSCPAL_EN if(lcdc_num) { pDISPBase = (VIOC_DISP *)HwVIOC_DISP1; pWIXBase =(VIOC_WMIX *)HwVIOC_WMIX1; tca_ckc_setperi(PERI_LCD1, ENABLE, spec.composite_clock*spec.composite_divider); VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_SDVENC, VIOC_OUTCFG_DISP1); } else { pDISPBase = (VIOC_DISP *)HwVIOC_DISP0; pWIXBase =(VIOC_WMIX *)HwVIOC_WMIX0; tca_ckc_setperi(PERI_LCD0, ENABLE, spec.composite_clock*spec.composite_divider); VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_SDVENC, VIOC_OUTCFG_DISP0); } printf("lcdc_num = %d, LCDC0 clk:%d, LCDC1 clk:%d, divide:%d\n", lcdc_num, tca_ckc_getperi(PERI_LCD0), tca_ckc_getperi(PERI_LCD1), spec.composite_divider); //LCDC_IO_Set(lcdc_num, spec.composite_bus_width); // hdmi power wake up tca_ckc_setippwdn(PMU_ISOL_VDAC, 0); //tca_ckc_setperi(PERI_HDMI, ENABLE, 10000); width = spec.composite_width; height = spec.composite_height; lcdc_set_logo(lcdc_num, width, height, fb_con); CompositeTiming.lpw = spec.composite_LPW; CompositeTiming.lpc = spec.composite_LPC + 1; CompositeTiming.lswc = spec.composite_LSWC + 1; CompositeTiming.lewc = spec.composite_LEWC + 1; CompositeTiming.vdb = spec.composite_VDB; CompositeTiming.vdf = spec.composite_VDF; CompositeTiming.fpw = spec.composite_FPW1; CompositeTiming.flc = spec.composite_FLC1; CompositeTiming.fswc = spec.composite_FSWC1; CompositeTiming.fewc = spec.composite_FEWC1; CompositeTiming.fpw2 = spec.composite_FPW2; CompositeTiming.flc2 = spec.composite_FLC2; CompositeTiming.fswc2 = spec.composite_FSWC2; CompositeTiming.fewc2 = spec.composite_FEWC2; VIOC_DISP_SetTimingParam(pDISPBase, &CompositeTiming); memset(&LcdCtrlParam, NULL, sizeof(LcdCtrlParam)); LcdCtrlParam.r2ymd = 3; LcdCtrlParam.ckg = 1; //LcdCtrlParam.id= 0; LcdCtrlParam.iv = 1; LcdCtrlParam.ih = 1; LcdCtrlParam.ip = 1; LcdCtrlParam.clen = 1; LcdCtrlParam.r2y = 1; LcdCtrlParam.pxdw = 6; //LcdCtrlParam.dp = 0; //LcdCtrlParam.ni = 0; LcdCtrlParam.tv = 1; //LcdCtrlParam.opt = 0; //LcdCtrlParam.stn = 0; //LcdCtrlParam.evsel = 0; //LcdCtrlParam.ovp = 0; VIOC_DISP_SetControlConfigure(pDISPBase, &LcdCtrlParam); VIOC_DISP_SetSize(pDISPBase, width, height); VIOC_DISP_SetBGColor(pDISPBase, 0, 0 , 0); //VIOC_DISP_TurnOn(pDISPBase); VIOC_WMIX_SetOverlayPriority(pWIXBase, 24); VIOC_WMIX_SetBGColor(pWIXBase, 0x00, 0x00, 0x00, 0xff); VIOC_WMIX_SetSize(pWIXBase, width, height); VIOC_WMIX_SetUpdate(pWIXBase); //Disconnect LCDC with NTSC/PAL encoder BITCLR(pTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN); //Set ECMDA Register if(type == LCDC_COMPOSITE_NTSC) { pTVE->ECMDA.nREG = HwTVECMDA_PWDENC_PD | // [7] Power down mode for entire digital logic of TV encoder HwTVECMDA_FDRST_1 | // [6] Chroma is free running as compared to H-sync HwTVECMDA_FSCSEL_NTSC | // [5:4] Color subcarrier frequency is 3.57954545 MHz for NTSC HwTVECMDA_PEDESTAL | // [3] Video Output has a pedestal (0 is NTSC-J) HwTVECMDA_PIXEL_601 | // [2] Input data is at 601 rates. HwTVECMDA_IFMT_525 | // [1] Output data has 525 lines HwTVECMDA_PHALT_NTSC | // [0] NTSC encoded chroma signal output 0; } else { pTVE->ECMDA.nREG = HwTVECMDA_FDRST_1 | // [6] Chroma is free running as compared to H-sync HwTVECMDA_FSCSEL_PALX | // [5:4] Color subcarrier frequency is 4.43361875 MHz for PAL-B,D,G,H,I,N HwTVECMDA_PIXEL_601 | // [2] Input data is at 601 rates. HwTVECMDA_IFMT_625 | // [1] Output data has 625 lines HwTVECMDA_PHALT_PAL | // [0] PAL encoded chroma signal output 0; } //Set DACSEL Register BITSET(pTVE->DACSEL.nREG, HwTVEDACSEL_DACSEL_CVBS); //Set DACPD Register #if defined(TCC892X) BITCLR(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #else BITSET(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #endif BITSET(pTVE->ICNTL.nREG, HwTVEICNTL_VSIP_HIGH); BITSET(pTVE->ICNTL.nREG, HwTVEICNTL_HSVSP_RISING); #if 0 // COMPOSITE_CCIR656 BITCSET(pTVE->ICNTL.nREG, HwTVEICNTL_ISYNC_MASK, HwTVEICNTL_ISYNC_ESAV_F); #else BITCSET(pTVE->ICNTL.nREG, HwTVEICNTL_ISYNC_MASK, HwTVEICNTL_ISYNC_HVSI); #endif //Set the Vertical Offset BITCSET(pTVE->HVOFFST.nREG, 0x07, ((0 & 0x700)>>8)); pTVE->HOFFST.nREG = (0 & 0xFF); //Set the Horizontal Offset BITCSET(pTVE->HVOFFST.nREG, 0x08, ((1 & 0x100)>>5)); pTVE->VOFFST.nREG = (1 & 0xFF); //Set the Digital Output Format BITCSET(pTVE->HVOFFST.nREG, HwTVEHVOFFST_INSEL_MASK, HwTVEHVOFFST_INSEL(2)); //Set HSVSO Register BITCSET(pTVE->HSVSO.nREG, 0x07, ((0 & 0x700)>>8)); pTVE->HSOE.nREG = (0 & 0xFF); BITCSET(pTVE->HSVSO.nREG, 0x38, ((0 & 0x700)>>5)); pTVE->HSOB.nREG = (0 & 0xFF); BITCSET(pTVE->HSVSO.nREG, 0x40, ((0 & 0x100)>>2)); pTVE->VSOB.nREG = (0 & 0xFF); //Set VSOE Register BITCSET(pTVE->VSOE.nREG, 0x1F, (0 & 0x1F)); BITCSET(pTVE->VSOE.nREG, 0xC0, (0 & 0x03)<<6); BITCSET(pTVE->VSOE.nREG, 0x20, (0 & 0x01)<<5); //Set the Connection Type BITSET(pTVE_VEN->VENCIF.nREG, HwTVEVENCIF_FMT_1); BITSET(pTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN); #if defined(TCC892X) BITSET(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #else BITCLR(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #endif BITCLR(pTVE->ECMDA.nREG, HwTVECMDA_PWDENC_PD); VIOC_DISP_TurnOn(pDISPBase); }
static void lcdc_io_init_component(unsigned char lcdc_num, unsigned char type) { unsigned int lcd_reg = 0; unsigned int width, height; stCOMPONENT_SPEC spec; stLTIMING ComponentTiming; stLCDCTR LcdCtrlParam; PVIOC_DISP pDISPBase; PVIOC_WMIX pWIXBase; PDDICONFIG pDDICfg = (PDDICONFIG)HwDDI_CONFIG_BASE; PNTSCPAL pTVE = (PNTSCPAL)HwNTSCPAL_BASE; PGPIO pGPIO = (PGPIO)HwGPIO_BASE; struct fbcon_config *fb_con; printf("%s, lcdc_num=%d, type=%d\n", __func__, lcdc_num, type); if(type >= LCDC_COMPONENT_MAX) type = defalut_component_resolution; #if defined(COMPONENT_CHIP_THS8200) #if defined(TARGET_BOARD_STB) /* THS8200 Power Control - GPIO_F16 */ gpio_set(TCC_GPF(16), 1); #else #endif #endif #ifndef DEFAULT_DISPLAY_OUTPUT_DUAL BITSET(pTVE->DACPD, HwTVEDACPD_PD_EN); #endif component_get_spec(type, &spec); LCDC_IO_Set(lcdc_num, spec.component_bus_width); fb_con = &fb_cfg; if(lcdc_num) { pDISPBase = (VIOC_DISP *)HwVIOC_DISP1; pWIXBase =(VIOC_WMIX *)HwVIOC_WMIX1; tca_ckc_setperi(PERI_LCD1, ENABLE, spec.component_clock*spec.component_divider); //VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_MRGB, VIOC_OUTCFG_DISP1); } else { pDISPBase = (VIOC_DISP *)HwVIOC_DISP0; pWIXBase =(VIOC_WMIX *)HwVIOC_WMIX0; tca_ckc_setperi(PERI_LCD0, ENABLE, spec.component_clock*spec.component_divider); //VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_MRGB, VIOC_OUTCFG_DISP0); } printf("LCDC0 clk:%d, LCDC1 clk:%d, PLL:%d, divide:%d\n", tca_ckc_getperi(PERI_LCD0), tca_ckc_getperi(PERI_LCD1), tca_ckc_getpll(PCDIRECTPLL0), spec.component_divider); width = spec.component_width; height = spec.component_height; lcdc_set_logo(lcdc_num, width, height, fb_con); ComponentTiming.lpw = spec.component_LPW; ComponentTiming.lpc = spec.component_LPC + 1; ComponentTiming.lswc = spec.component_LSWC + 1; ComponentTiming.lewc = spec.component_LEWC + 1; ComponentTiming.vdb = spec.component_VDB; ComponentTiming.vdf = spec.component_VDF; ComponentTiming.fpw = spec.component_FPW1; ComponentTiming.flc = spec.component_FLC1; ComponentTiming.fswc = spec.component_FSWC1; ComponentTiming.fewc = spec.component_FEWC1; ComponentTiming.fpw2 = spec.component_FPW2; ComponentTiming.flc2 = spec.component_FLC2; ComponentTiming.fswc2 = spec.component_FSWC2; ComponentTiming.fewc2 = spec.component_FEWC2; VIOC_DISP_SetTimingParam(pDISPBase, &ComponentTiming); memset(&LcdCtrlParam, NULL, sizeof(LcdCtrlParam)); switch(type) { case LCDC_COMPONENT_480I_NTSC: case LCDC_COMPONENT_576I_PAL: break; case LCDC_COMPONENT_720P: LcdCtrlParam.r2ymd = 3; LcdCtrlParam.ckg = 1; LcdCtrlParam.id= 0; LcdCtrlParam.iv = 1; LcdCtrlParam.ih = 1; LcdCtrlParam.ip = 0; LcdCtrlParam.pxdw = 12; LcdCtrlParam.ni = 1; break; case LCDC_COMPONENT_1080I: LcdCtrlParam.r2ymd = 3; LcdCtrlParam.ckg = 1; LcdCtrlParam.id= 1; LcdCtrlParam.iv = 1; LcdCtrlParam.ih = 0; LcdCtrlParam.ip = 1; LcdCtrlParam.pxdw = 12; LcdCtrlParam.ni = 0; LcdCtrlParam.tv = 1; break; default: break; } VIOC_DISP_SetControlConfigure(pDISPBase, &LcdCtrlParam); VIOC_DISP_SetSize(pDISPBase, width, height); VIOC_DISP_SetBGColor(pDISPBase, 0, 0 , 0); VIOC_WMIX_SetOverlayPriority(pWIXBase, 0); VIOC_WMIX_SetBGColor(pWIXBase, 0x00, 0x00, 0x00, 0xff); VIOC_WMIX_SetSize(pWIXBase, width, height); VIOC_WMIX_SetUpdate(pWIXBase); #if defined(TARGET_BOARD_STB) /* VE_FIELD: GPIO_E27 */ gpio_config(TCC_GPE(27), GPIO_FN0|GPIO_OUTPUT|GPIO_HIGH); #endif /* Enable Component Chip */ #if defined(COMPONENT_CHIP_CS4954) if(type == LCDC_COMPONENT_480I_NTSC) cs4954_enable(COMPONENT_MODE_NTSC_M); // NTSC_M else cs4954_enable(COMPONENT_MODE_PAL_B); // PAL_B #elif defined(COMPONENT_CHIP_THS8200) if(type == LCDC_COMPONENT_720P) ths8200_enable(COMPONENT_MODE_720P); // 720P else ths8200_enable(COMPONENT_MODE_1080I); // 1080I #endif VIOC_DISP_TurnOn(pDISPBase); }
static void lcdc_io_init_hdmi(unsigned char lcdc_num) { uint width, height; VIOC_DISP *pDISP; VIOC_WMIX *pWIMX; stLTIMING HDMI_TIMEp; stLCDCTR pCtrlParam; volatile PCLK_XXX_TYPE *pLCDC_CKC; volatile PCKC pCKC = (PCKC)HwCKC_BASE; volatile PDDICONFIG pDDI_Config = (PDDICONFIG)HwDDI_CONFIG_BASE; struct fbcon_config *fb_con; const struct HDMIVideoParameter video = { #if (HDMI_MODE_TYPE == 1) /* video.mode =*/ HDMI, #else /* video.mode =*/ DVI, #endif /* video.resolution =*/ gRefHdmiVideoModeList[HDMI_VIDEO_MODE_TYPE].vfmt_val, /* video.colorSpace =*/ HDMI_CS_RGB, /* video.colorDepth =*/ HDMI_CD_24, /* video.colorimetry =*/ HDMI_COLORIMETRY_NO_DATA, /* video.pixelAspectRatio =*/ gRefHdmiVideoModeList[HDMI_VIDEO_MODE_TYPE].ratio, }; const struct HDMIAudioParameter audio = { /* audio.inputPort =*/ I2S_PORT, /* audio.outPacket =*/ HDMI_ASP, /* audio.formatCode =*/ LPCM_FORMAT, /* audio.channelNum =*/ CH_2, /* audio.sampleFreq =*/ SF_44KHZ, /* audio.wordLength =*/ WORD_16, /* audio.i2sParam.bpc =*/ I2S_BPC_16, /* audio.i2sParam.format =*/ I2S_BASIC, /* audio.i2sParam.clk =*/ I2S_64FS }; printf("%s LCDC NUM:%d \n", __func__, lcdc_num); fb_con = &fb_cfg; if(0) {//lcdc_num) { #if defined(DEFAULT_DISPLAY_OUTPUT_DUAL) fb_con = &fb1_cfg; #endif } else { #if defined(DEFAULT_DISPLAY_OUTPUT_DUAL) fb_con = &fb0_cfg; #endif } if(lcdc_num) { pDISP = (VIOC_DISP *)HwVIOC_DISP1; pWIMX = (VIOC_WMIX *)HwVIOC_WMIX1; pLCDC_CKC = (PCLK_XXX_TYPE *)((&pCKC->PCLKCTRL00)+PERI_LCD1); tca_ckc_setperi(PERI_LCD1, ENABLE, 1000000); VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_HDMI, VIOC_OUTCFG_DISP1); } else { pDISP = (VIOC_DISP *)HwVIOC_DISP0; pWIMX = (VIOC_WMIX *)HwVIOC_WMIX0; pLCDC_CKC = (PCLK_XXX_TYPE *)((&pCKC->PCLKCTRL00)+PERI_LCD0); tca_ckc_setperi(PERI_LCD0, ENABLE, 1000000); VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_HDMI, VIOC_OUTCFG_DISP0); } pLCDC_CKC->bREG.DIV = 0; pLCDC_CKC->bREG.SEL = PCDIVIDXTIN_HDMIPCLK; pLCDC_CKC->bREG.EN = 1; tca_ckc_setippwdn(PMU_ISOL_HDMI, 0); tca_ckc_setperi(PERI_HDMI, ENABLE, 10000); width = gRefHdmiVideoModeList[HDMI_VIDEO_MODE_TYPE].width; height = gRefHdmiVideoModeList[HDMI_VIDEO_MODE_TYPE].height; HDMI_TIMEp.lpw= LCDCTimimgParams[video.resolution].lpw; HDMI_TIMEp.lpc= LCDCTimimgParams[video.resolution].lpc + 1; HDMI_TIMEp.lswc= LCDCTimimgParams[video.resolution].lswc+ 1; HDMI_TIMEp.lewc= LCDCTimimgParams[video.resolution].lewc+ 1; HDMI_TIMEp.vdb = LCDCTimimgParams[video.resolution].vdb; HDMI_TIMEp.vdf = LCDCTimimgParams[video.resolution].vdf; HDMI_TIMEp.fpw = LCDCTimimgParams[video.resolution].fpw; HDMI_TIMEp.flc = LCDCTimimgParams[video.resolution].flc; HDMI_TIMEp.fswc = LCDCTimimgParams[video.resolution].fswc; HDMI_TIMEp.fewc = LCDCTimimgParams[video.resolution].fewc; HDMI_TIMEp.fpw2 = LCDCTimimgParams[video.resolution].fpw2; HDMI_TIMEp.flc2 = LCDCTimimgParams[video.resolution].flc2; HDMI_TIMEp.fswc2 = LCDCTimimgParams[video.resolution].fswc2; HDMI_TIMEp.fewc2 = LCDCTimimgParams[video.resolution].fewc2; VIOC_DISP_SetTimingParam(pDISP, &HDMI_TIMEp); memset(&pCtrlParam, NULL, sizeof(pCtrlParam)); pCtrlParam.id= LCDCTimimgParams[video.resolution].id; pCtrlParam.iv= LCDCTimimgParams[video.resolution].iv; pCtrlParam.ih= LCDCTimimgParams[video.resolution].ih; pCtrlParam.ip= LCDCTimimgParams[video.resolution].ip; pCtrlParam.clen = 0; if(video.colorSpace == HDMI_CS_RGB) { pCtrlParam.r2y = 0; pCtrlParam.pxdw = 12; //RGB888 } else { pCtrlParam.r2y = 1; pCtrlParam.pxdw = 8; //RGB888 } pCtrlParam.dp = LCDCTimimgParams[video.resolution].dp; pCtrlParam.ni = LCDCTimimgParams[video.resolution].ni; pCtrlParam.tv = LCDCTimimgParams[video.resolution].tv; pCtrlParam.opt = 0; pCtrlParam.stn = 0; pCtrlParam.evsel = 0; pCtrlParam.ovp = 0; VIOC_DISP_SetControlConfigure(pDISP, &pCtrlParam); VIOC_WMIX_SetOverlayPriority(pWIMX, 24); VIOC_WMIX_SetBGColor(pWIMX, 0x00, 0x00, 0x00, 0xff); VIOC_WMIX_SetSize(pWIMX, width, height); VIOC_WMIX_SetChromaKey(pWIMX, 0, 0, 0, 0, 0, 0xF8, 0xFC, 0xF8); VIOC_WMIX_SetUpdate(pWIMX); BITSET(pDDI_Config->PWDN.nREG, Hw2); BITCLR(pDDI_Config->SWRESET.nREG, Hw2); BITSET(pDDI_Config->SWRESET.nREG, Hw2); hdmi_ddi_config_init(); hdmi_set_hdmi_mode(video.mode); hdmi_set_video_mode(&video); lcdc_set_logo(lcdc_num, width, height, fb_con); VIOC_DISP_SetSize (pDISP, width, height); VIOC_DISP_SetBGColor(pDISP, 0, 0 , 0); VIOC_DISP_TurnOn(pDISP); if (video.mode == HDMI) hdmi_set_audio_mode(&audio); hdmi_start(); }
void clock_init_early(void) { tca_ckc_init(); tca_ckc_setpll(5940000, 0); tca_ckc_setpll(5000000, 1); tca_ckc_setpll(4320000, 2); tca_ckc_setpll(6720000, 3); // tca_ckc_setpll(6000000, 4); // tca_ckc_setpll(6480000, 5); // tca_ckc_setfbusctrl( CLKCTRL0, ENABLE, 0, 8000000, DIRECTPLL5); /*FBUS_CPU 800 MHz*/ // 1.2V tca_ckc_setfbusctrl( CLKCTRL1, ENABLE, 0, 2500000, DIRECTPLL1); /*FBUS_DDI 290 MHz*/ // tca_ckc_setfbusctrl( CLKCTRL2, ENABLE, 0, 3200000, DIRECTPLL3); /*FBUS_MEM 320 MHz */ tca_ckc_setfbusctrl( CLKCTRL3, DISABLE, 0, 2500000, DIRECTPLL1); /*FBUS_GRP 320 MHz */ tca_ckc_setfbusctrl( CLKCTRL4, ENABLE, 0, 1680000, DIRECTPLL3); /*FBUS_IOB 190 MHz */ tca_ckc_setfbusctrl( CLKCTRL5, DISABLE, 0, 2970000, DIRECTPLL0); /*FBUS_VBUS 300 MHz */ tca_ckc_setfbusctrl( CLKCTRL6, DISABLE, 0, 2500000, DIRECTPLL1); /*FBUS_VCODEC 290 MHz */ tca_ckc_setfbusctrl( CLKCTRL7, ENABLE, 0, 2000000, DIRECTPLL5); /*FBUS_SMU 200 MHz */ tca_ckc_setfbusctrl( CLKCTRL8, ENABLE, 0, 2160000, DIRECTPLL2); /*FBUS_HSIO 240 MHz */ tca_ckc_setfbusctrl( CLKCTRL9, DISABLE, 0, 2970000, DIRECTPLL0); /*CAMBUS 330 MHz */ // init Peri. Clock tca_ckc_setperi(PERI_TCX , DISABLE, 120000, PCDIRECTXIN); tca_ckc_setperi(PERI_TCT , ENABLE, 120000, PCDIRECTXIN); tca_ckc_setperi(PERI_TCZ , ENABLE, 120000, PCDIRECTXIN); tca_ckc_setperi(PERI_LCD0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_LCD1 , ENABLE, 960000,PCDIRECTPLL3); tca_ckc_setperi(PERI_LCDSI0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_LCDSI1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_HDMIA , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_DSI , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_RESERVED0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_HDMI , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_USB11H , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_SDMMC0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_MSTICK , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_I2C0 , ENABLE, 40000, PCDIRECTXIN); tca_ckc_setperi(PERI_UART0 , ENABLE, 480000,PCDIRECTPLL3); tca_ckc_setperi(PERI_UART1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_UART2 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_UART3 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_UART4 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_UART5 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_GPSB0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_GPSB1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_GPSB2 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_GPSB3 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_GPSB4 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_GPSB5 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_ADC , ENABLE, 120000, PCDIRECTXIN); tca_ckc_setperi(PERI_SPDIF , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_EHI0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_EHI1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_AUD , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_PDM , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_SDMMC1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_SDMMC2 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_SDMMC3 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_DAI0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_DAI1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_DAI2 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_I2C1 , ENABLE, 40000, PCDIRECTXIN); tca_ckc_setperi(PERI_SATA_REF0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_SATA_REF1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_SATAH0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_SATAH1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_USB20H , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_GMAC , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_CIFMC , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_CIFSC , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_ISPJ , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_ISPS , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_FILTER , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_RESERVED1 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_RESERVED2 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_RESERVED3 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_OUT0 , DISABLE, 10000, PCDIRECTXIN); tca_ckc_setperi(PERI_OUT1 , DISABLE, 10000, PCDIRECTXIN); }
struct fbcon_config *lcdc_init(void) { #if defined(_M805_8923_) || defined(_M805_8925_) || (HW_REV == 0x1006) || (HW_REV == 0x1008) #define LCDC_NUM 0 #else #define LCDC_NUM 1 #endif struct lcd_panel *panel_info; struct fbcon_config *fbcon_cfg; struct tcc_lcdc_image_update Image_info; unsigned int lclk; #if 0 // reset VIOD BITSET(pDDICfg->SWRESET, Hw3); BITSET(pDDICfg->SWRESET, Hw2); BITCLR(pDDICfg->SWRESET, Hw3); BITCLR(pDDICfg->SWRESET, Hw2); #endif// panel_info = tccfb_get_panel(); panel_info->dev.power_on = GPIO_LCD_ON; panel_info->dev.display_on = GPIO_LCD_DISPLAY; panel_info->dev.bl_on = GPIO_LCD_BL; panel_info->dev.reset = GPIO_LCD_RESET; panel_info->dev.lcdc_num = LCDC_NUM; panel_info->init(panel_info); if(panel_info->dev.lcdc_num) { tca_ckc_setperi(PERI_LCD1,ENABLE, panel_info->clk_freq * panel_info->clk_div); lclk = tca_ckc_getperi(PERI_LCD1); } else { tca_ckc_setperi(PERI_LCD0,ENABLE, panel_info->clk_freq * panel_info->clk_div); lclk = tca_ckc_getperi(PERI_LCD0); } printf("telechips tcc88xx %s lcdc:%d clk:%d set clk:%d \n", __func__, LCDC_NUM, panel_info->clk_freq, lclk); dprintf(INFO, "lcdc: panel is %d x %d %dbpp\n", panel_info->xres, panel_info->yres, fb_cfg.bpp); #ifdef DISPLAY_SPLASH_SCREEN_DIRECT fb_cfg.stride = fb_cfg.width; #else fb_cfg.width = panel_info->xres; fb_cfg.height = panel_info->yres; fb_cfg.stride = fb_cfg.width; fb_cfg.bpp = LCDC_FB_BPP; fb_cfg.format = FB_FORMAT_RGB565; fb_cfg.base = dma_alloc(4096, fb_cfg.width * fb_cfg.height * (fb_cfg.bpp/8)); if (fb_cfg.base == NULL) dprintf(INFO, "lcdc: framebuffer alloc failed!\n"); #endif// dprintf(INFO, "fb_cfg base:0x%x xres:%d yres:%d bpp:%d \n",fb_cfg.base, fb_cfg.width, fb_cfg.height, fb_cfg.bpp); Image_info.addr0 = (unsigned int)fb_cfg.base; Image_info.Lcdc_layer = 0; Image_info.enable = 1; Image_info.Frame_width = Image_info.Image_width = fb_cfg.width; Image_info.Frame_height = Image_info.Image_height = fb_cfg.height; printf(INFO, "Frame_width:%d Image_width:%d width:%d \n",Image_info.Frame_width, Image_info.Image_width, fb_cfg.width); printf(INFO, "Frame_height:%d Image_height:%d width:%d \n",Image_info.Frame_height, Image_info.Image_height, fb_cfg.height); if(Image_info.Image_width > panel_info->xres) Image_info.Image_width = panel_info->xres; if(panel_info->xres > Image_info.Frame_width) Image_info.offset_x = (panel_info->xres - Image_info.Frame_width)/2; else Image_info.offset_x = 0; if(panel_info->yres > Image_info.Frame_height) Image_info.offset_y = (panel_info->yres - Image_info.Frame_height)/2; else Image_info.offset_y = 0; #ifdef _LCD_32BPP_ Image_info.fmt = TCC_LCDC_IMG_FMT_RGB888; #else Image_info.fmt = TCC_LCDC_IMG_FMT_RGB565; #endif tcclcd_image_ch_set(panel_info->dev.lcdc_num, &Image_info); panel_info->set_power(panel_info, 1); mdelay(1); panel_info->set_backlight_level(panel_info, DEFAULT_BACKLIGTH); fbcon_cfg = &fb_cfg; return fbcon_cfg; }