static void dec10_movem_m_r(DisasContext *dc) { int i, pfix = dc->tb_flags & PFIX_FLAG; TCGv addr, t0; LOG_DIS("%s [r%d], r%d pi=%d ir=%x\n", __func__, dc->src, dc->dst, dc->postinc, dc->ir); addr = tcg_temp_new(); t0 = tcg_temp_new(); crisv10_prepare_memaddr(dc, addr, 4); tcg_gen_mov_tl(t0, addr); for (i = dc->dst; i >= 0; i--) { gen_load(dc, cpu_R[i], addr, 4, 0); tcg_gen_addi_tl(addr, addr, 4); } if (pfix && dc->mode == CRISV10_MODE_AUTOINC) { tcg_gen_mov_tl(cpu_R[dc->src], t0); } if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) { tcg_gen_mov_tl(cpu_R[dc->src], addr); } tcg_temp_free(addr); tcg_temp_free(t0); }
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { REQUIRE_EXT(ctx, RVM); TCGv source1 = tcg_temp_new(); TCGv source2 = tcg_temp_new(); gen_get_gpr(source1, a->rs1); gen_get_gpr(source2, a->rs2); tcg_gen_mulu2_tl(source2, source1, source1, source2); gen_set_gpr(a->rd, source1); tcg_temp_free(source1); tcg_temp_free(source2); return true; }
static void dec10_reg_mul(DisasContext *dc, int size, int sext) { int op = sext ? CC_OP_MULS : CC_OP_MULU; TCGv t[2]; t[0] = tcg_temp_new(); t[1] = tcg_temp_new(); dec10_reg_prep_sext(dc, size, sext, t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4); tcg_temp_free(t[0]); tcg_temp_free(t[1]); }
static int dec10_alux_m(DisasContext *dc, int op) { unsigned int size = (dc->size & 1) ? 2 : 1; unsigned int sx = !!(dc->size & 2); int insn_len = 2; int rd = dc->dst; TCGv t; LOG_DIS("addx size=%d sx=%d op=%d %d\n", size, sx, dc->src, dc->dst); t = tcg_temp_new(); cris_cc_mask(dc, CC_MASK_NZVC); insn_len += dec10_prep_move_m(dc, sx, size, t); cris_alu(dc, op, cpu_R[dc->dst], cpu_R[rd], t, 4); if (dc->dst == 15) { tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; return insn_len; } tcg_temp_free(t); return insn_len; }
static int dec10_prep_move_m(DisasContext *dc, int s_ext, int memsize, TCGv dst) { unsigned int rs; uint32_t imm; int is_imm; int insn_len = 0; rs = dc->src; is_imm = rs == 15 && !(dc->tb_flags & PFIX_FLAG); LOG_DIS("rs=%d rd=%d is_imm=%d mode=%d pfix=%d\n", rs, dc->dst, is_imm, dc->mode, dc->tb_flags & PFIX_FLAG); /* Load [$rs] onto T1. */ if (is_imm) { if (memsize != 4) { if (s_ext) { if (memsize == 1) imm = ldsb_code(dc->pc + 2); else imm = ldsw_code(dc->pc + 2); } else { if (memsize == 1) imm = ldub_code(dc->pc + 2); else imm = lduw_code(dc->pc + 2); } } else imm = ldl_code(dc->pc + 2); tcg_gen_movi_tl(dst, imm); if (dc->mode == CRISV10_MODE_AUTOINC) { insn_len += memsize; if (memsize == 1) insn_len++; tcg_gen_addi_tl(cpu_R[15], cpu_R[15], insn_len); } } else { TCGv addr; addr = tcg_temp_new(); cris_flush_cc_state(dc); crisv10_prepare_memaddr(dc, addr, memsize); gen_load(dc, dst, addr, memsize, 0); if (s_ext) t_gen_sext(dst, dst, memsize); else t_gen_zext(dst, dst, memsize); insn_len += crisv10_post_memaddr(dc, memsize); tcg_temp_free(addr); } if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) { dc->dst = dc->src; } return insn_len; }
static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext) { TCGv t[2]; t[0] = tcg_temp_new(); t[1] = tcg_temp_new(); dec10_reg_prep_sext(dc, size, sext, t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); if (op == CC_OP_LSL || op == CC_OP_LSR || op == CC_OP_ASR) { tcg_gen_andi_tl(t[1], t[1], 63); } assert(dc->dst != 15); cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size); tcg_temp_free(t[0]); tcg_temp_free(t[1]); }
static void dec_lw(DisasContext *dc) { TCGv t0; LOG_DIS("lw r%d, (r%d+%d)\n", dc->r1, dc->r0, sign_extend(dc->imm16, 16)); t0 = tcg_temp_new(); tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16)); tcg_gen_qemu_ld32s(cpu_R[dc->r1], t0, MEM_INDEX); tcg_temp_free(t0); }
static void dec_sw(DisasContext *dc) { TCGv t0; LOG_DIS("sw (r%d+%d), r%d\n", dc->r0, sign_extend(dc->imm16, 16), dc->r1); t0 = tcg_temp_new(); tcg_gen_addi_tl(t0, cpu_R[dc->r0], sign_extend(dc->imm16, 16)); tcg_gen_qemu_st32(cpu_R[dc->r1], t0, MEM_INDEX); tcg_temp_free(t0); }
static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size) { unsigned int insn_len = 2; TCGv addr; LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst); addr = tcg_temp_new(); crisv10_prepare_memaddr(dc, addr, size); gen_store_v10(dc, addr, cpu_R[dc->dst], size); insn_len += crisv10_post_memaddr(dc, size); return insn_len; }
static void dec_b(DisasContext *dc) { if (dc->r0 == R_RA) { LOG_DIS("ret\n"); } else if (dc->r0 == R_EA) { LOG_DIS("eret\n"); } else if (dc->r0 == R_BA) { LOG_DIS("bret\n"); } else { LOG_DIS("b r%d\n", dc->r0); } /* restore IE.IE in case of an eret */ if (dc->r0 == R_EA) { TCGv t0 = tcg_temp_new(); TCGLabel *l1 = gen_new_label(); tcg_gen_andi_tl(t0, cpu_ie, IE_EIE); tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_EIE, l1); tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE); gen_set_label(l1); tcg_temp_free(t0); } else if (dc->r0 == R_BA) { TCGv t0 = tcg_temp_new(); TCGLabel *l1 = gen_new_label(); tcg_gen_andi_tl(t0, cpu_ie, IE_BIE); tcg_gen_ori_tl(cpu_ie, cpu_ie, IE_IE); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, IE_BIE, l1); tcg_gen_andi_tl(cpu_ie, cpu_ie, ~IE_IE); gen_set_label(l1); tcg_temp_free(t0); } tcg_gen_mov_tl(cpu_pc, cpu_R[dc->r0]); dc->is_jmp = DISAS_JUMP; }
static unsigned int dec10_ind_move_pr_m(DisasContext *dc) { unsigned int insn_len = 2, size = preg_sizes_v10[dc->dst]; TCGv addr, t0; LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); addr = tcg_temp_new(); crisv10_prepare_memaddr(dc, addr, size); if (dc->dst == PR_CCS) { t0 = tcg_temp_new(); cris_evaluate_flags(dc); tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG); gen_store_v10(dc, addr, t0, size); tcg_temp_free(t0); } else { gen_store_v10(dc, addr, cpu_PR[dc->dst], size); } t0 = tcg_temp_new(); insn_len += crisv10_post_memaddr(dc, size); cris_lock_irq(dc); return insn_len; }
static void dec10_reg_abs(DisasContext *dc) { TCGv t0; LOG_DIS("abs $r%u, $r%u\n", dc->src, dc->dst); assert(dc->dst != 15); t0 = tcg_temp_new(); tcg_gen_sari_tl(t0, cpu_R[dc->src], 31); tcg_gen_xor_tl(cpu_R[dc->dst], cpu_R[dc->src], t0); tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4); tcg_temp_free(t0); }
static unsigned int dec10_ind_move_m_pr(DisasContext *dc) { unsigned int insn_len = 2, rd = dc->dst; TCGv t, addr; LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); cris_lock_irq(dc); addr = tcg_temp_new(); t = tcg_temp_new(); insn_len += dec10_prep_move_m(dc, 0, 4, t); if (rd == 15) { tcg_gen_mov_tl(env_btarget, t); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; return insn_len; } tcg_gen_mov_tl(cpu_PR[rd], t); dc->cpustate_changed = 1; tcg_temp_free(addr); tcg_temp_free(t); return insn_len; }
static void gen_lvsr(DisasContext *ctx) { TCGv_ptr rd; TCGv EA; if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); return; } EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); rd = gen_avr_ptr(rD(ctx->opcode)); gen_helper_lvsr(rd, EA); tcg_temp_free(EA); tcg_temp_free_ptr(rd); }
/* * pop_shack() * Pop next host eip from shadow stack. */ void pop_shack(TCGv_ptr cpu_env, TCGv next_eip) { #ifdef OPT_SHACK /* declare variables */ int lab_end = gen_new_label(); TCGv tcg_next_eip = tcg_temp_local_new(); TCGv_ptr tcg_top_host_eip = tcg_temp_local_new_ptr(); TCGv_ptr tcg_shack_top = tcg_temp_new_ptr(); TCGv_ptr tcg_shack = tcg_temp_new_ptr(); TCGv tcg_top_guest_eip = tcg_temp_new(); /* check if shack is empty */ tcg_gen_mov_tl(tcg_next_eip, next_eip); tcg_gen_ld_ptr(tcg_shack_top, cpu_env, offsetof(CPUState, shack_top)); //load shack top tcg_gen_ld_ptr(tcg_shack, cpu_env, offsetof(CPUState, shack)); //load shack tcg_gen_brcond_i32(TCG_COND_EQ, tcg_shack_top, tcg_shack, lab_end); // if(shack_top == shack): jmp to lab_end /* shack not empty -> update shack top*/ tcg_gen_ld_ptr(tcg_shack_top, cpu_env, offsetof(CPUState, shack_top)); //load shack top tcg_gen_subi_i32(tcg_shack_top, tcg_shack_top, sizeof (void *)); //else: shack_top-- tcg_gen_st_tl(tcg_shack_top, cpu_env, offsetof(CPUState, shack_top)); // store shack top /* check if shack_top->guest_eip == tcg_next_eip */ tcg_gen_ld_ptr(tcg_shack_top, tcg_shack_top, 0); // shack top = shack[shack_top] tcg_gen_ld_tl(tcg_top_guest_eip, tcg_shack_top, offsetof(struct shadow_pair, guest_eip)); //tcg_top_guest_eip = tcg_shack_top->guest_eip tcg_gen_brcond_i32(TCG_COND_NE, tcg_top_guest_eip, tcg_next_eip, lab_end); // if(shack_top->guest_eip != next_eip): jmp to lab_end /* check if shack_top->host_eip is valid */ tcg_gen_ld_ptr(tcg_shack_top, cpu_env, offsetof(CPUState, shack_top)); //load shack top tcg_gen_ld_ptr(tcg_shack_top, tcg_shack_top, 0); // shack top = shack[shack_top] tcg_gen_ld_ptr(tcg_top_host_eip, tcg_shack_top, offsetof(struct shadow_pair, host_eip)); //tcg_top_host_eip = tcg_shack_top->host_eip tcg_gen_brcond_i32(TCG_COND_EQ, tcg_top_host_eip, tcg_const_ptr(NULL), lab_end); // if(shack_top->host_eip == NULL): jmp to lab_end /* update return addr*/ *gen_opc_ptr++ = INDEX_op_jmp; *gen_opparam_ptr++ = tcg_top_host_eip; /* clean up */ gen_set_label(lab_end); tcg_temp_free_ptr(tcg_shack_top); tcg_temp_free_ptr(tcg_shack); tcg_temp_free_ptr(tcg_top_host_eip); tcg_temp_free(tcg_top_guest_eip); tcg_temp_free(tcg_next_eip); #endif }
static void dec10_reg_alux(DisasContext *dc, int op) { int size = (dc->size & 1) + 1; TCGv t; LOG_DIS("movx.%d $r%d, $r%d\n", size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); t = tcg_temp_new(); if (dc->ir & 32) t_gen_sext(t, cpu_R[dc->src], size); else t_gen_zext(t, cpu_R[dc->src], size); cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); tcg_temp_free(t); }
static void dec_nor(DisasContext *dc) { if (dc->format == OP_FMT_RI) { LOG_DIS("nori r%d, r%d, %d\n", dc->r0, dc->r1, zero_extend(dc->imm16, 16)); } else { LOG_DIS("nor r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } if (dc->format == OP_FMT_RI) { TCGv t0 = tcg_temp_new(); tcg_gen_movi_tl(t0, zero_extend(dc->imm16, 16)); tcg_gen_nor_tl(cpu_R[dc->r1], cpu_R[dc->r0], t0); tcg_temp_free(t0); } else { tcg_gen_nor_tl(cpu_R[dc->r2], cpu_R[dc->r0], cpu_R[dc->r1]); } }
static void dec10_reg_swap(DisasContext *dc) { TCGv t0; LOG_DIS("not $r%d, $r%d\n", dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); t0 = tcg_temp_new(); t_gen_mov_TN_reg(t0, dc->src); if (dc->dst & 8) tcg_gen_not_tl(t0, t0); if (dc->dst & 4) t_gen_swapw(t0, t0); if (dc->dst & 2) t_gen_swapb(t0, t0); if (dc->dst & 1) t_gen_swapr(t0, t0); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4); tcg_temp_free(t0); }
static unsigned int dec10_ind_move_m_r(DisasContext *dc, unsigned int size) { unsigned int insn_len = 2; TCGv t; LOG_DIS("%s: move.%d [$r%d], $r%d\n", __func__, size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); t = tcg_temp_new(); insn_len += dec10_prep_move_m(dc, 0, size, t); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, size); if (dc->dst == 15) { tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; return insn_len; } tcg_temp_free(t); return insn_len; }
static void dec_sl(DisasContext *dc) { if (dc->format == OP_FMT_RI) { LOG_DIS("sli r%d, r%d, %d\n", dc->r1, dc->r0, dc->imm5); } else { LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } if (!(dc->features & LM32_FEATURE_SHIFT)) { qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not available\n"); t_gen_illegal_insn(dc); return; } if (dc->format == OP_FMT_RI) { tcg_gen_shli_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5); } else { TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f); tcg_gen_shl_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0); tcg_temp_free(t0); } }
/* * pop_shack() * Pop next host eip from shadow stack. */ void pop_shack(TCGv_ptr cpu_env, TCGv next_eip) { // labels int label_end = gen_new_label(); // prepare registers TCGv_ptr temp_shack_start = tcg_temp_local_new_ptr(); // store shack start TCGv_ptr temp_shack_top = tcg_temp_local_new_ptr(); // store shack top TCGv eip_on_shack = tcg_temp_local_new(); TCGv_ptr host_slot_addr = tcg_temp_local_new(); TCGv_ptr host_addr = tcg_temp_new(); // load common values tcg_gen_ld_ptr(temp_shack_start, cpu_env, offsetof(CPUState, shack)); tcg_gen_ld_ptr(temp_shack_top, cpu_env, offsetof(CPUState, shack_top)); // check if stack empty? tcg_gen_brcond_ptr(TCG_COND_EQ,temp_shack_top,temp_shack_start,label_end); // stack not empty, pop one tcg_gen_subi_ptr(temp_shack_top, temp_shack_top, sizeof(uint64_t)); // decrease top tcg_gen_st_ptr(temp_shack_top, cpu_env, offsetof(CPUState, shack_top)); // store back top tcg_gen_ld_tl(eip_on_shack, temp_shack_top, 0); // get eip // check if the same? tcg_gen_brcond_ptr(TCG_COND_NE,tcg_const_tl(next_eip),eip_on_shack,label_end); // go to "end" if not the same tcg_gen_ld_tl(host_slot_addr, temp_shack_top, sizeof(unsigned long)); // get slot addr tcg_gen_ld_ptr(host_addr, host_slot_addr, 0) ; // get host addr tcg_gen_brcond_ptr(TCG_COND_EQ,tcg_const_tl(0),host_addr,label_end); // go to "end" if addr is zero // jump! *gen_opc_ptr++ = INDEX_op_jmp; *gen_opparam_ptr++ = GET_TCGV_I32(host_addr); // label: end gen_set_label(label_end); tcg_temp_free(eip_on_shack); tcg_temp_free_ptr(host_slot_addr); tcg_temp_free_ptr(host_addr); tcg_temp_free_ptr(temp_shack_top); tcg_temp_free_ptr(temp_shack_start); }
static unsigned int dec10_ind(DisasContext *dc) { unsigned int insn_len = 2; unsigned int size = dec10_size(dc->size); uint32_t imm; int32_t simm; TCGv t[2]; if (dc->size != 3) { switch (dc->opcode) { case CRISV10_IND_MOVE_M_R: return dec10_ind_move_m_r(dc, size); break; case CRISV10_IND_MOVE_R_M: return dec10_ind_move_r_m(dc, size); break; case CRISV10_IND_CMP: LOG_DIS("cmp size=%d op=%d %d\n", size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); insn_len += dec10_ind_alu(dc, CC_OP_CMP, size); break; case CRISV10_IND_TEST: LOG_DIS("test size=%d op=%d %d\n", size, dc->src, dc->dst); cris_evaluate_flags(dc); cris_cc_mask(dc, CC_MASK_NZVC); cris_alu_m_alloc_temps(t); insn_len += dec10_prep_move_m(dc, 0, size, t[0]); tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], t[0], tcg_const_tl(0), size); cris_alu_m_free_temps(t); break; case CRISV10_IND_ADD: LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); insn_len += dec10_ind_alu(dc, CC_OP_ADD, size); break; case CRISV10_IND_SUB: LOG_DIS("sub size=%d op=%d %d\n", size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); insn_len += dec10_ind_alu(dc, CC_OP_SUB, size); break; case CRISV10_IND_BOUND: LOG_DIS("bound size=%d op=%d %d\n", size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); insn_len += dec10_ind_bound(dc, size); break; case CRISV10_IND_AND: LOG_DIS("and size=%d op=%d %d\n", size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); insn_len += dec10_ind_alu(dc, CC_OP_AND, size); break; case CRISV10_IND_OR: LOG_DIS("or size=%d op=%d %d\n", size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); insn_len += dec10_ind_alu(dc, CC_OP_OR, size); break; case CRISV10_IND_MOVX: insn_len = dec10_alux_m(dc, CC_OP_MOVE); break; case CRISV10_IND_ADDX: insn_len = dec10_alux_m(dc, CC_OP_ADD); break; case CRISV10_IND_SUBX: insn_len = dec10_alux_m(dc, CC_OP_SUB); break; case CRISV10_IND_CMPX: insn_len = dec10_alux_m(dc, CC_OP_CMP); break; case CRISV10_IND_MUL: /* This is a reg insn coded in the mem indir space. */ LOG_DIS("mul pc=%x opcode=%d\n", dc->pc, dc->opcode); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_mul(dc, size, dc->ir & (1 << 10)); break; case CRISV10_IND_BDAP_M: insn_len = dec10_bdap_m(dc, size); break; default: LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", dc->pc, size, dc->opcode, dc->src, dc->dst); cpu_abort(dc->env, "Unhandled opcode"); break; } return insn_len; } switch (dc->opcode) { case CRISV10_IND_MOVE_M_SPR: insn_len = dec10_ind_move_m_pr(dc); break; case CRISV10_IND_MOVE_SPR_M: insn_len = dec10_ind_move_pr_m(dc); break; case CRISV10_IND_JUMP_M: if (dc->src == 15) { LOG_DIS("jump.%d %d r%d r%d direct\n", size, dc->opcode, dc->src, dc->dst); imm = ldl_code(dc->pc + 2); if (dc->mode == CRISV10_MODE_AUTOINC) insn_len += size; t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); dc->jmp_pc = imm; cris_prepare_jmp(dc, JMP_DIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ } else { if (dc->dst == 14) { LOG_DIS("break %d\n", dc->src); cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc + 2); t_gen_raise_exception(EXCP_BREAK); dc->is_jmp = DISAS_UPDATE; return insn_len; } LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size, dc->opcode, dc->src, dc->dst); t[0] = tcg_temp_new(); t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); crisv10_prepare_memaddr(dc, t[0], size); gen_load(dc, env_btarget, t[0], 4, 0); insn_len += crisv10_post_memaddr(dc, size); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ tcg_temp_free(t[0]); } break; case CRISV10_IND_MOVEM_R_M: LOG_DIS("movem_r_m pc=%x opcode=%d r%d r%d\n", dc->pc, dc->opcode, dc->dst, dc->src); dec10_movem_r_m(dc); break; case CRISV10_IND_MOVEM_M_R: LOG_DIS("movem_m_r pc=%x opcode=%d\n", dc->pc, dc->opcode); dec10_movem_m_r(dc); break; case CRISV10_IND_JUMP_R: LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n", dc->pc, dc->opcode, dc->dst, dc->src); tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ break; case CRISV10_IND_MOVX: insn_len = dec10_alux_m(dc, CC_OP_MOVE); break; case CRISV10_IND_ADDX: insn_len = dec10_alux_m(dc, CC_OP_ADD); break; case CRISV10_IND_SUBX: insn_len = dec10_alux_m(dc, CC_OP_SUB); break; case CRISV10_IND_CMPX: insn_len = dec10_alux_m(dc, CC_OP_CMP); break; case CRISV10_IND_DIP: insn_len = dec10_dip(dc); break; case CRISV10_IND_BCC_M: cris_cc_mask(dc, 0); imm = ldsw_code(dc->pc + 2); simm = (int16_t)imm; simm += 4; LOG_DIS("bcc_m: b%s %x\n", cc_name(dc->cond), dc->pc + simm); cris_prepare_cc_branch(dc, simm, dc->cond); insn_len = 4; break; default: LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); cpu_abort(dc->env, "Unhandled opcode"); break; } return insn_len; }
static unsigned int dec10_reg(DisasContext *dc) { TCGv t; unsigned int insn_len = 2; unsigned int size = dec10_size(dc->size); unsigned int tmp; if (dc->size != 3) { switch (dc->opcode) { case CRISV10_REG_MOVE_R: LOG_DIS("move.%d $r%d, $r%d\n", dc->size, dc->src, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_MOVE, size, 0); if (dc->dst == 15) { tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; } break; case CRISV10_REG_MOVX: cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_movs(dc); break; case CRISV10_REG_ADDX: cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alux(dc, CC_OP_ADD); break; case CRISV10_REG_SUBX: cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alux(dc, CC_OP_SUB); break; case CRISV10_REG_ADD: LOG_DIS("add $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_ADD, size, 0); break; case CRISV10_REG_SUB: LOG_DIS("sub $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_SUB, size, 0); break; case CRISV10_REG_CMP: LOG_DIS("cmp $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_CMP, size, 0); break; case CRISV10_REG_BOUND: LOG_DIS("bound $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_bound(dc, size); break; case CRISV10_REG_AND: LOG_DIS("and $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_AND, size, 0); break; case CRISV10_REG_ADDI: if (dc->src == 15) { /* nop. */ return 2; } t = tcg_temp_new(); LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size); tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3); tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t); tcg_temp_free(t); break; case CRISV10_REG_LSL: LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_LSL, size, 0); break; case CRISV10_REG_LSR: LOG_DIS("lsr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_LSR, size, 0); break; case CRISV10_REG_ASR: LOG_DIS("asr $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_ASR, size, 1); break; case CRISV10_REG_OR: LOG_DIS("or $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_OR, size, 0); break; case CRISV10_REG_NEG: LOG_DIS("neg $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_NEG, size, 0); break; case CRISV10_REG_BIAP: LOG_DIS("BIAP pc=%x reg %d r%d r%d size=%d\n", dc->pc, dc->opcode, dc->src, dc->dst, size); switch (size) { case 4: tmp = 2; break; case 2: tmp = 1; break; case 1: tmp = 0; break; default: cpu_abort(dc->env, "Unhandled BIAP"); break; } t = tcg_temp_new(); tcg_gen_shli_tl(t, cpu_R[dc->dst], tmp); if (dc->src == 15) { tcg_gen_addi_tl(cpu_PR[PR_PREFIX], t, ((dc->pc +2)| 1) + 1); } else { tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t); } tcg_temp_free(t); cris_set_prefix(dc); break; default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); cpu_abort(dc->env, "Unhandled opcode"); break; } } else { switch (dc->opcode) { case CRISV10_REG_MOVX: cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_movs(dc); break; case CRISV10_REG_ADDX: cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alux(dc, CC_OP_ADD); break; case CRISV10_REG_SUBX: cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alux(dc, CC_OP_SUB); break; case CRISV10_REG_MOVE_SPR_R: cris_evaluate_flags(dc); cris_cc_mask(dc, 0); dec10_reg_mov_pr(dc); break; case CRISV10_REG_MOVE_R_SPR: LOG_DIS("move r%d p%d\n", dc->src, dc->dst); cris_evaluate_flags(dc); if (dc->src != 11) /* fast for srp. */ dc->cpustate_changed = 1; t_gen_mov_preg_TN(dc, dc->dst, cpu_R[dc->src]); break; case CRISV10_REG_SETF: case CRISV10_REG_CLEARF: dec10_setclrf(dc); break; case CRISV10_REG_SWAP: dec10_reg_swap(dc); break; case CRISV10_REG_ABS: cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_abs(dc); break; case CRISV10_REG_LZ: LOG_DIS("lz $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_LZ, 4, 0); break; case CRISV10_REG_XOR: LOG_DIS("xor $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); dec10_reg_alu(dc, CC_OP_XOR, 4, 0); break; case CRISV10_REG_BTST: LOG_DIS("btst $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); cris_update_cc_op(dc, CC_OP_FLAGS, 4); gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->dst], cpu_R[dc->src], cpu_PR[PR_CCS]); break; case CRISV10_REG_DSTEP: LOG_DIS("dstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_DSTEP, cpu_R[dc->dst], cpu_R[dc->dst], cpu_R[dc->src], 4); break; case CRISV10_REG_MSTEP: LOG_DIS("mstep $r%d, $r%d sz=%d\n", dc->src, dc->dst, size); cris_evaluate_flags(dc); cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_MSTEP, cpu_R[dc->dst], cpu_R[dc->dst], cpu_R[dc->src], 4); break; case CRISV10_REG_SCC: dec10_reg_scc(dc); break; default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); cpu_abort(dc->env, "Unhandled opcode"); break; } } return insn_len; }