Пример #1
0
int __init roth_soctherm_init(void)
{
	tegra_add_vc_trips(roth_soctherm_data.therm[THERM_CPU].trips,
			&roth_soctherm_data.therm[THERM_CPU].num_trips);

	return tegra11_soctherm_init(&roth_soctherm_data);
}
int __init tegratab_soctherm_init(void)
{
	tegra_platform_edp_init(tegratab_soctherm_data.therm[THERM_CPU].trips,
			&tegratab_soctherm_data.therm[THERM_CPU].num_trips,
			8000); /* edp temperature margin */
	tegra_add_tj_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
			&tegratab_soctherm_data.therm[THERM_CPU].num_trips);
	tegra_add_vc_trips(tegratab_soctherm_data.therm[THERM_CPU].trips,
			&tegratab_soctherm_data.therm[THERM_CPU].num_trips);

	return tegra11_soctherm_init(&tegratab_soctherm_data);
}
int __init pismo_soctherm_init(void)
{
	tegra_platform_edp_init(pismo_soctherm_data.therm[THERM_CPU].trips,
			&pismo_soctherm_data.therm[THERM_CPU].num_trips,
			6000); /* edp temperature margin */
	tegra_add_cpu_vmax_trips(pismo_soctherm_data.therm[THERM_CPU].trips,
			&pismo_soctherm_data.therm[THERM_CPU].num_trips);
	tegra_add_core_edp_trips(pismo_soctherm_data.therm[THERM_CPU].trips,
			&pismo_soctherm_data.therm[THERM_CPU].num_trips);

	return tegra11_soctherm_init(&pismo_soctherm_data);
}
int __init dalmore_soctherm_init(void)
{
	struct board_info board_info;

	tegra_get_board_info(&board_info);
	if (!(board_info.board_id == BOARD_E1611 ||
		board_info.board_id == BOARD_P2454))
		dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;

	tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips,
			&dalmore_soctherm_data.therm[THERM_CPU].num_trips,
			8000); /* edp temperature margin */
	tegra_add_tj_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
			&dalmore_soctherm_data.therm[THERM_CPU].num_trips);

	return tegra11_soctherm_init(&dalmore_soctherm_data);
}
int __init macallan_soctherm_init(void)
{
	struct board_info board_info;
	tegra_get_board_info(&board_info);
	if (board_info.board_id == BOARD_E1545)
		tegra_add_cdev_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
				&macallan_soctherm_data.therm[THERM_CPU].num_trips);
	tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips,
			&macallan_soctherm_data.therm[THERM_CPU].num_trips,
			6000); /* edp temperature margin */
	tegra_add_tj_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
			&macallan_soctherm_data.therm[THERM_CPU].num_trips);
	tegra_add_vc_trips(macallan_soctherm_data.therm[THERM_CPU].trips,
			&macallan_soctherm_data.therm[THERM_CPU].num_trips);


	return tegra11_soctherm_init(&macallan_soctherm_data);
}
int __init atlantis_soctherm_init(void)
{
	struct board_info board_info;

	/* atlantis ERS and FFD */
	tegra_get_board_info(&board_info);
	if (!((board_info.board_id == BOARD_E1670) ||
		(board_info.board_id == BOARD_E1740)))
		return -EINVAL;

	tegra_platform_edp_init(atlantis_soctherm_data.therm[THERM_CPU].trips,
				&atlantis_soctherm_data.therm[THERM_CPU].num_trips,
				14000); /* edp temperature margin */
	tegra_add_tj_trips(atlantis_soctherm_data.therm[THERM_CPU].trips,
			   &atlantis_soctherm_data.therm[THERM_CPU].num_trips);

	return tegra11_soctherm_init(&atlantis_soctherm_data);
}
Пример #7
0
int __init laguna_soctherm_init(void)
{
	tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
			&laguna_soctherm_data.therm[THERM_CPU].num_trips,
			7000); /* edp temperature margin */
	tegra_platform_gpu_edp_init(
			laguna_soctherm_data.therm[THERM_GPU].trips,
			&laguna_soctherm_data.therm[THERM_GPU].num_trips,
			7000);
	tegra_add_cpu_vmax_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
			&laguna_soctherm_data.therm[THERM_CPU].num_trips);
	tegra_add_tgpu_trips(laguna_soctherm_data.therm[THERM_GPU].trips,
			&laguna_soctherm_data.therm[THERM_GPU].num_trips);
	tegra_add_vc_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
			&laguna_soctherm_data.therm[THERM_CPU].num_trips);
	tegra_add_core_vmax_trips(laguna_soctherm_data.therm[THERM_PLL].trips,
			&laguna_soctherm_data.therm[THERM_PLL].num_trips);

	return tegra11_soctherm_init(&laguna_soctherm_data);
}
Пример #8
0
int __init flounder_soctherm_init(void)
{
	const int t13x_cpu_edp_temp_margin = 5000,
		t13x_gpu_edp_temp_margin = 6000;
	int cpu_edp_temp_margin, gpu_edp_temp_margin;
	int cp_rev, ft_rev;
	enum soctherm_therm_id therm_cpu = THERM_CPU;

	cp_rev = tegra_fuse_calib_base_get_cp(NULL, NULL);
	ft_rev = tegra_fuse_calib_base_get_ft(NULL, NULL);

	/* TODO: remove this part once bootloader changes merged */
	tegra_gpio_disable(TEGRA_GPIO_PJ2);
	tegra_gpio_disable(TEGRA_GPIO_PS7);

	cpu_edp_temp_margin = t13x_cpu_edp_temp_margin;
	gpu_edp_temp_margin = t13x_gpu_edp_temp_margin;

	if (!cp_rev) {
		/* ATE rev is NEW: use v2 table */
		flounder_soctherm_data.therm[THERM_CPU] =
			t132ref_v2_soctherm_data.therm[THERM_CPU];
		flounder_soctherm_data.therm[THERM_GPU] =
			t132ref_v2_soctherm_data.therm[THERM_GPU];
	} else {
		/* ATE rev is Old or Mid: use PLLx sensor only */
		flounder_soctherm_data.therm[THERM_CPU] =
			t132ref_v1_soctherm_data.therm[THERM_CPU];
		flounder_soctherm_data.therm[THERM_PLL] =
			t132ref_v1_soctherm_data.therm[THERM_PLL];
		therm_cpu = THERM_PLL; /* override CPU with PLL zone */
	}

	/* do this only for supported CP,FT fuses */
	if ((cp_rev >= 0) && (ft_rev >= 0)) {
		tegra_platform_edp_init(
			flounder_soctherm_data.therm[therm_cpu].trips,
			&flounder_soctherm_data.therm[therm_cpu].num_trips,
			t13x_cpu_edp_temp_margin);
		tegra_platform_gpu_edp_init(
			flounder_soctherm_data.therm[THERM_GPU].trips,
			&flounder_soctherm_data.therm[THERM_GPU].num_trips,
			t13x_gpu_edp_temp_margin);
		tegra_add_cpu_vmax_trips(
			flounder_soctherm_data.therm[therm_cpu].trips,
			&flounder_soctherm_data.therm[therm_cpu].num_trips);
		tegra_add_tgpu_trips(
			flounder_soctherm_data.therm[THERM_GPU].trips,
			&flounder_soctherm_data.therm[THERM_GPU].num_trips);
		tegra_add_core_vmax_trips(
			flounder_soctherm_data.therm[THERM_PLL].trips,
			&flounder_soctherm_data.therm[THERM_PLL].num_trips);
	}

	tegra_add_cpu_vmin_trips(
		flounder_soctherm_data.therm[therm_cpu].trips,
		&flounder_soctherm_data.therm[therm_cpu].num_trips);
	tegra_add_gpu_vmin_trips(
		flounder_soctherm_data.therm[THERM_GPU].trips,
		&flounder_soctherm_data.therm[THERM_GPU].num_trips);
	tegra_add_core_vmin_trips(
		flounder_soctherm_data.therm[THERM_PLL].trips,
		&flounder_soctherm_data.therm[THERM_PLL].num_trips);

	flounder_soctherm_data.tshut_pmu_trip_data = &tpdata_palmas;
	/* Enable soc_therm OC throttling on selected platforms */
	memcpy(&flounder_soctherm_data.throttle[THROTTLE_OC4],
		       &battery_oc_throttle_t13x,
		       sizeof(battery_oc_throttle_t13x));
	return tegra11_soctherm_init(&flounder_soctherm_data);
}
int __init norrin_soctherm_init(void)
{
	const int t13x_cpu_edp_temp_margin = 5000,
		t13x_gpu_edp_temp_margin = 6000;
	int cp_rev, ft_rev;
	struct board_info pmu_board_info;
	struct board_info board_info;
	enum soctherm_therm_id therm_cpu = THERM_CPU;

	tegra_get_board_info(&board_info);

	cp_rev = tegra_fuse_calib_base_get_cp(NULL, NULL);
	ft_rev = tegra_fuse_calib_base_get_ft(NULL, NULL);

	if (cp_rev) {
		/* ATE rev is Old or Mid - use PLLx sensor only */
		norrin_soctherm_data.therm[THERM_CPU] =
			norrin_v1_soctherm_data.therm[THERM_CPU];
		norrin_soctherm_data.therm[THERM_PLL] =
			norrin_v1_soctherm_data.therm[THERM_PLL];
		therm_cpu = THERM_PLL; /* override CPU with PLL zone */
	}

	/* do this only for supported CP,FT fuses */
	if ((cp_rev >= 0) && (ft_rev >= 0)) {
		tegra_platform_edp_init(
			norrin_soctherm_data.therm[therm_cpu].trips,
			&norrin_soctherm_data.therm[therm_cpu].num_trips,
			t13x_cpu_edp_temp_margin);
		tegra_platform_gpu_edp_init(
			norrin_soctherm_data.therm[THERM_GPU].trips,
			&norrin_soctherm_data.therm[THERM_GPU].num_trips,
			t13x_gpu_edp_temp_margin);
		tegra_add_cpu_vmax_trips(
			norrin_soctherm_data.therm[therm_cpu].trips,
			&norrin_soctherm_data.therm[therm_cpu].num_trips);
		tegra_add_tgpu_trips(
			norrin_soctherm_data.therm[THERM_GPU].trips,
			&norrin_soctherm_data.therm[THERM_GPU].num_trips);
		tegra_add_core_vmax_trips(
			norrin_soctherm_data.therm[THERM_PLL].trips,
			&norrin_soctherm_data.therm[THERM_PLL].num_trips);
	}

	if (board_info.board_id == BOARD_PM374 ||
		board_info.board_id == BOARD_PM375 ||
		board_info.board_id == BOARD_E1971 ||
		board_info.board_id == BOARD_E1991) {
		tegra_add_cpu_vmin_trips(
			norrin_soctherm_data.therm[therm_cpu].trips,
			&norrin_soctherm_data.therm[therm_cpu].num_trips);
		tegra_add_gpu_vmin_trips(
			norrin_soctherm_data.therm[THERM_GPU].trips,
			&norrin_soctherm_data.therm[THERM_GPU].num_trips);
		tegra_add_core_vmin_trips(
			norrin_soctherm_data.therm[THERM_PLL].trips,
			&norrin_soctherm_data.therm[THERM_PLL].num_trips);
	}

	if (board_info.board_id == BOARD_PM375)
		tegra_add_cpu_clk_switch_trips(
			norrin_soctherm_data.therm[THERM_CPU].trips,
			&norrin_soctherm_data.therm[THERM_CPU].num_trips);
	tegra_get_pmu_board_info(&pmu_board_info);

	if ((pmu_board_info.board_id == BOARD_PM374) ||
		(pmu_board_info.board_id == BOARD_PM375))
		norrin_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
	else
		pr_warn("soctherm THERMTRIP not supported on PMU (BOARD_P%d)\n",
			pmu_board_info.board_id);

	return tegra11_soctherm_init(&norrin_soctherm_data);
}
int __init ardbeg_soctherm_init(void)
{
	s32 base_cp, shft_cp;
	u32 base_ft, shft_ft;
	struct board_info pmu_board_info;
	struct board_info board_info;

	tegra_get_board_info(&board_info);

	if (board_info.board_id == BOARD_E1923 ||
			board_info.board_id == BOARD_E1922) {
		memcpy(ardbeg_soctherm_data.therm,
				ardbeg_therm_pop, sizeof(ardbeg_therm_pop));
	}

	/* do this only for supported CP,FT fuses */
	if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
	    (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
		tegra_platform_edp_init(
			ardbeg_soctherm_data.therm[THERM_CPU].trips,
			&ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
			7000); /* edp temperature margin */
		tegra_platform_gpu_edp_init(
			ardbeg_soctherm_data.therm[THERM_GPU].trips,
			&ardbeg_soctherm_data.therm[THERM_GPU].num_trips,
			7000);
		tegra_add_cpu_vmax_trips(
			ardbeg_soctherm_data.therm[THERM_CPU].trips,
			&ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
		tegra_add_tgpu_trips(
			ardbeg_soctherm_data.therm[THERM_GPU].trips,
			&ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
		tegra_add_vc_trips(
			ardbeg_soctherm_data.therm[THERM_CPU].trips,
			&ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
		tegra_add_core_vmax_trips(
			ardbeg_soctherm_data.therm[THERM_PLL].trips,
			&ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
	}

	if (board_info.board_id == BOARD_P1761 ||
		board_info.board_id == BOARD_E1784 ||
		board_info.board_id == BOARD_E1971 ||
		board_info.board_id == BOARD_E1991 ||
		board_info.board_id == BOARD_E1922) {
		tegra_add_cpu_vmin_trips(
			ardbeg_soctherm_data.therm[THERM_CPU].trips,
			&ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
		tegra_add_gpu_vmin_trips(
			ardbeg_soctherm_data.therm[THERM_GPU].trips,
			&ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
		tegra_add_core_vmin_trips(
			ardbeg_soctherm_data.therm[THERM_PLL].trips,
			&ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
	}

	tegra_get_pmu_board_info(&pmu_board_info);

	if ((pmu_board_info.board_id == BOARD_E1733) ||
		(pmu_board_info.board_id == BOARD_E1734))
		ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
	else if (pmu_board_info.board_id == BOARD_E1735 ||
		 pmu_board_info.board_id == BOARD_E1736 ||
		 pmu_board_info.board_id == BOARD_E1769 ||
		 pmu_board_info.board_id == BOARD_P1761 ||
		 pmu_board_info.board_id == BOARD_E1936)
		ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_palmas;
	else
		pr_warn("soctherm THERMTRIP not supported on PMU (BOARD_E%d)\n",
			pmu_board_info.board_id);

	/* Enable soc_therm OC throttling on selected platforms */
	switch (pmu_board_info.board_id) {
	case BOARD_P1761:
		memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC4],
		       &battery_oc_throttle,
		       sizeof(battery_oc_throttle));
		memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC1],
		       &voltmon_throttle,
		       sizeof(voltmon_throttle));

		break;
	default:
		break;
	}

	return tegra11_soctherm_init(&ardbeg_soctherm_data);
}
Пример #11
0
int __init roth_soctherm_init(void)
{
	return tegra11_soctherm_init(&roth_soctherm_data);
}