void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
const struct tegra_dc_dp_link_config *link_cfg)
{
tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
link_cfg->drive_current);
tegra_sor_writel(sor, NV_SOR_PR(sor->portnum),
link_cfg->preemphasis);
tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum),
link_cfg->postcursor);
tegra_sor_writel(sor, NV_SOR_LVDS, 0);
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
NV_SOR_DP_PADCTL_TX_PU_ENABLE |
NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
NV_SOR_DP_PADCTL_TX_PU_ENABLE |
2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT);
/* Precharge */
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
0xf0, 0xf0);
udelay(20);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
0xf0, 0x0);
}
void tegra_dc_sor_set_lane_parm(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
link_cfg->drive_current);
tegra_sor_writel(sor, PR(sor->portnum),
link_cfg->preemphasis);
tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
link_cfg->postcursor);
tegra_sor_writel(sor, LVDS, 0);
tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_TX_PU_ENABLE |
DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
DP_PADCTL_TX_PU_ENABLE |
2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
/* Precharge */
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
udelay(20);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
}
static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
const struct tegra_dc_dp_link_config *link_cfg)
{
u32 reg_val;
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum));
reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK;
reg_val |= link_cfg->watermark;
reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK;
reg_val |= (link_cfg->active_count <<
NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK;
reg_val |= (link_cfg->active_frac <<
NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
if (link_cfg->activepolarity)
reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
else
reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE);
tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val);
/* program h/vblank sym */
tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS,
NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym);
tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS,
NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, link_cfg->vblank_sym);
}
/* 5 0 0 0 0 0 0 1 */
static void tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor,
int is_lvds)
{
if (sor->power_is_up)
return;
/* Set link bw */
tegra_dc_sor_set_link_bandwidth(sor,
is_lvds ? NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS :
NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62);
/* step 1 */
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE |
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
tegra_sor_write_field(sor, NV_SOR_PLL0,
NV_SOR_PLL0_PWR_MASK | /* PDPLL */
NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
NV_SOR_PLL0_PWR_OFF |
NV_SOR_PLL0_VCOPD_ASSERT);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN);
/* step 2 */
tegra_dc_sor_io_set_dpd(sor, 1);
udelay(15);
/* step 3 */
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
udelay(25);
/* step 4 */
tegra_sor_write_field(sor, NV_SOR_PLL0,
NV_SOR_PLL0_PWR_MASK | /* PDPLL */
NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */
NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND);
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
udelay(225);
/* step 5 */
tegra_sor_write_field(sor, NV_SOR_PLL2,
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */
NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE);
sor->power_is_up = 1;
}
/*
* The SOR power sequencer does not work for t124 so SW has to
* go through the power sequence manually
* Power up steps from spec:
* STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL
* 1 1 1 1 1 1 1 1
* 2 1 1 1 1 1 0 1
* 3 1 1 0 1 1 0 1
* 4 1 0 0 0 0 0 1
* 5 0 0 0 0 0 0 1
*/
static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg;
int ret;
if (sor->power_is_up)
return 0;
/*
* If for some reason it is already powered up, don't do it again.
* This can happen if U-Boot is the secondary boot loader.
*/
reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
if (reg & DP_PADCTL_PD_TXD_0_NO)
return 0;
/* Set link bw */
tegra_dc_sor_set_link_bandwidth(dev, is_lvds ?
CLK_CNTRL_DP_LINK_SPEED_LVDS :
CLK_CNTRL_DP_LINK_SPEED_G1_62);
/* step 1 */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
PLL2_AUX7_PORT_POWERDOWN_ENABLE |
PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
PLL0_VCOPD_MASK, /* PLLVCOPD */
PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
DP_PADCTL_PAD_CAL_PD_POWERDOWN);
/* step 2 */
ret = tegra_dc_sor_io_set_dpd(sor, 1);
if (ret)
return ret;
udelay(15);
/* step 3 */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
udelay(25);
/* step 4 */
tegra_sor_write_field(sor, PLL0,
PLL0_PWR_MASK | /* PDPLL */
PLL0_VCOPD_MASK, /* PLLVCOPD */
PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
/* PLLCAPD */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
udelay(225);
/* step 5 PDPORT */
tegra_sor_write_field(sor, PLL2,
PLL2_AUX7_PORT_POWERDOWN_MASK,
PLL2_AUX7_PORT_POWERDOWN_DISABLE);
sor->power_is_up = 1;
return 0;
}
