/******************************************************************************* * Initialize the gic, configure the SCR. ******************************************************************************/ void bl31_platform_setup(void) { uint32_t tmp_reg; /* * Initialize delay timer */ tegra_delay_timer_init(); /* * Setup secondary CPU POR infrastructure. */ plat_secondary_setup(); /* * Initial Memory Controller configuration. */ tegra_memctrl_setup(); /* * Do initial security configuration to allow DRAM/device access. */ tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, plat_bl31_params_from_bl2.tzdram_size); /* Set the next EL to be AArch64 */ tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; write_scr(tmp_reg); /* Initialize the gic cpu and distributor interfaces */ tegra_gic_setup(); }
/******************************************************************************* * Handler called when a power domain has just been powered on after * being turned off earlier. The target_state encodes the low power state that * each level has woken up from. ******************************************************************************/ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) { plat_params_from_bl2_t *plat_params; /* * Initialize the GIC cpu and distributor interfaces */ tegra_gic_setup(); /* * Check if we are exiting from deep sleep. */ if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == PSTATE_ID_SOC_POWERDN) { /* * Lock scratch registers which hold the CPU vectors. */ tegra_pmc_lock_cpu_vectors(); /* * SMMU configuration. */ tegra_memctrl_setup(); /* * Security configuration to allow DRAM/device access. */ plat_params = bl31_get_plat_params(); tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, plat_params->tzdram_size); } /* * Reset hardware settings. */ tegra_soc_pwr_domain_on_finish(target_state); }
/******************************************************************************* * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image * info. ******************************************************************************/ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; image_info_t bl32_img_info = { {0} }; uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; uint32_t console_clock; int32_t ret; /* * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so * there's no argument to relay from a previous bootloader. Platforms * might use custom ways to get arguments, so provide handlers which * they can override. */ if (arg_from_bl2 == NULL) { arg_from_bl2 = plat_get_bl31_params(); } if (plat_params == NULL) { plat_params = plat_get_bl31_plat_params(); } /* * Copy BL3-3, BL3-2 entry point information. * They are stored in Secure RAM, in BL2's address space. */ assert(arg_from_bl2 != NULL); assert(arg_from_bl2->bl33_ep_info != NULL); bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; if (arg_from_bl2->bl32_ep_info != NULL) { bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0; bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2; } /* * Parse platform specific parameters - TZDRAM aperture base and size */ assert(plat_params != NULL); plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; /* * It is very important that we run either from TZDRAM or TZSRAM base. * Add an explicit check here. */ if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && (TEGRA_TZRAM_BASE != BL31_BASE)) { panic(); } /* * Reference clock used by the FPGAs is a lot slower. */ if (tegra_platform_is_fpga()) { console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; } else { console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; } /* * Get the base address of the UART controller to be used for the * console */ tegra_console_base = plat_get_console_from_id(plat_params->uart_id); if (tegra_console_base != 0U) { /* * Configure the UART port to be used as the console */ (void)console_init(tegra_console_base, console_clock, TEGRA_CONSOLE_BAUDRATE); } /* * The previous bootloader passes the base address of the shared memory * location to store the boot profiler logs. Sanity check the * address and initilise the profiler library, if it looks ok. */ if (plat_params->boot_profiler_shmem_base != 0ULL) { ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, PROFILER_SIZE_BYTES); if (ret == (int32_t)0) { /* store the membase for the profiler lib */ plat_bl31_params_from_bl2.boot_profiler_shmem_base = plat_params->boot_profiler_shmem_base; /* initialise the profiler library */ boot_profiler_init(plat_params->boot_profiler_shmem_base, TEGRA_TMRUS_BASE); } } /* * Add timestamp for platform early setup entry. */ boot_profiler_add_record("[TF] early setup entry"); /* * Initialize delay timer */ tegra_delay_timer_init(); /* Early platform setup for Tegra SoCs */ plat_early_platform_setup(); /* * Do initial security configuration to allow DRAM/device access. */ tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, (uint32_t)plat_bl31_params_from_bl2.tzdram_size); /* * The previous bootloader might not have placed the BL32 image * inside the TZDRAM. We check the BL32 image info to find out * the base/PC values and relocate the image if necessary. */ if (arg_from_bl2->bl32_image_info != NULL) { bl32_img_info = *arg_from_bl2->bl32_image_info; /* Relocate BL32 if it resides outside of the TZDRAM */ tzdram_start = plat_bl31_params_from_bl2.tzdram_base; tzdram_end = plat_bl31_params_from_bl2.tzdram_base + plat_bl31_params_from_bl2.tzdram_size; bl32_start = bl32_img_info.image_base; bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; assert(tzdram_end > tzdram_start); assert(bl32_end > bl32_start); assert(bl32_image_ep_info.pc > tzdram_start); assert(bl32_image_ep_info.pc < tzdram_end); /* relocate BL32 */ if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) { INFO("Relocate BL32 to TZDRAM\n"); (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, (void *)(uintptr_t)bl32_start, bl32_img_info.image_size); /* clean up non-secure intermediate buffer */ zeromem((void *)(uintptr_t)bl32_start, bl32_img_info.image_size); } } /* * Add timestamp for platform early setup exit. */ boot_profiler_add_record("[TF] early setup exit"); INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); }