void nvhost_module_busy(struct nvhost_module *mod)
{
mutex_lock(&mod->lock);
cancel_delayed_work(&mod->powerdown);
if (mod->force_suspend) {
pr_warn("tegra_grhost: module_busy despite %s force_suspend!\n",
mod->name);
WARN_ON(1);
}
if ((atomic_inc_return(&mod->refcount) == 1) && !mod->powered) {
if (mod->parent)
nvhost_module_busy(mod->parent);
if (mod->powergate_id != -1) {
BUG_ON(mod->num_clks != 1);
tegra_powergate_sequence_power_up(
mod->powergate_id, mod->clk[0]);
} else {
int i;
for (i = 0; i < mod->num_clks; i++)
clk_enable(mod->clk[i]);
}
if (mod->func)
mod->func(mod, NVHOST_POWER_ACTION_ON);
mod->powered = true;
}
mutex_unlock(&mod->lock);
}
static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
tegra->supplies);
if (ret)
return ret;
ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
tegra->sata_clk,
tegra->sata_rst);
if (ret)
goto disable_regulators;
reset_control_assert(tegra->sata_oob_rst);
reset_control_assert(tegra->sata_cold_rst);
ret = ahci_platform_enable_resources(hpriv);
if (ret)
goto disable_power;
reset_control_deassert(tegra->sata_cold_rst);
reset_control_deassert(tegra->sata_oob_rst);
return 0;
disable_power:
clk_disable_unprepare(tegra->sata_clk);
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
disable_regulators:
regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
return ret;
}
int nvhost_module_init(struct nvhost_module *mod, const char *name,
nvhost_modulef func, struct nvhost_module *parent,
struct device *dev)
{
int i = 0;
mod->name = name;
while (i < NVHOST_MODULE_MAX_CLOCKS) {
long rate;
mod->clk[i] = clk_get(dev, get_module_clk_id(name, i));
if (IS_ERR_OR_NULL(mod->clk[i]))
break;
rate = clk_round_rate(mod->clk[i], UINT_MAX);
if (rate < 0) {
pr_err("%s: can't get maximum rate for %s\n",
__func__, name);
break;
}
if (rate != clk_get_rate(mod->clk[i])) {
clk_set_rate(mod->clk[i], rate);
}
i++;
}
mod->num_clks = i;
mod->func = func;
mod->parent = parent;
mod->powered = false;
mod->powergate_id = get_module_powergate_id(name);
mod->force_suspend = false;
#if CONFIG_DISABLE_3D_POWERGATING
/*
* It is possible for the 3d block to generate an invalid memory
* request during the power up sequence in some cases. Workaround
* is to disable 3d block power gating.
*/
if (mod->powergate_id == TEGRA_POWERGATE_3D) {
tegra_powergate_sequence_power_up(mod->powergate_id,
mod->clk[0]);
clk_disable(mod->clk[0]);
mod->powergate_id = -1;
}
#endif
#ifdef DISABLE_MPE_POWERGATING
/*
* Disable power gating for MPE as it seems to cause issues with
* camera record stress tests when run in loop.
*/
if (mod->powergate_id == TEGRA_POWERGATE_MPE) {
tegra_powergate_sequence_power_up(mod->powergate_id,
mod->clk[0]);
clk_disable(mod->clk[0]);
mod->powergate_id = -1;
}
#endif
mutex_init(&mod->lock);
init_waitqueue_head(&mod->idle);
INIT_DELAYED_WORK(&mod->powerdown, powerdown_handler);
return 0;
}
static int
enable_fdt_resources(struct tegra_ahci_sc *sc)
{
int rv;
rv = regulator_enable(sc->supply_hvdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'hvdd' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_vddio);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'vddio' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'avdd' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_target_5v);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'target-5v' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_target_12v);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'sc->target-12v' regulator\n");
return (rv);
}
/* Stop clocks */
clk_stop(sc->clk_sata);
clk_stop(sc->clk_sata_oob);
tegra_powergate_power_off(TEGRA_POWERGATE_SAX);
rv = hwreset_assert(sc->hwreset_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata oob' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata cold' reset\n");
return (rv);
}
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX,
sc->clk_sata, sc->hwreset_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'SAX' powergate\n");
return (rv);
}
rv = clk_enable(sc->clk_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'sata oob' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_cml);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'cml' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_pll_e);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'pll e' clock\n");
return (rv);
}
rv = hwreset_deassert(sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n");
return (rv);
}
rv = hwreset_deassert(sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n");
return (rv);
}
rv = phy_enable(sc->dev, sc->phy);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable SATA phy\n");
return (rv);
}
return (0);
}
static int
enable_fdt_resources(struct tegra_xhci_softc *sc)
{
int rv;
rv = hwreset_assert(sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n");
return (rv);
}
rv = regulator_enable(sc->supply_avddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_dvddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'dvddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_utmip);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_utmip-5v' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_erefe);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_erefe' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb_ss_pll);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb_ss_pll' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss_pll_e);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss_pll_e' regulator\n");
return (rv);
}
/* Power off XUSB host and XUSB SS domains. */
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n");
return (rv);
}
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n");
return (rv);
}
/* Setup XUSB ss_src clock first */
clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0);
if (rv != 0)
return (rv);
/* The XUSB gate clock must be enabled before XUSBA can be powered. */
rv = clk_enable(sc->clk_xusb_gate);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_gate' clock\n");
return (rv);
}
/* Power on XUSB host and XUSB SS domains. */
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
sc->clk_xusb_host, sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n");
return (rv);
}
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
sc->clk_xusb_ss, sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusba' domain\n");
return (rv);
}
/* Enable rest of clocks */
rv = clk_enable(sc->clk_xusb_falcon_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_falcon_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_fs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_fs_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_hs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_hs_src' clock\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_0 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_1);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_1 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_2);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_2 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb3_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB3_0 phy\n");
return (rv);
}
return (0);
}
