Пример #1
0
/*! \brief NVM Example Main
 *
 * The NVM example begins by initializing required board resources.  The
 * system clock and basic GPIO pin mapping are established.
 *
 * A memory location on the Non volatile memory is written with a fixed test
 * pattern which is then read back into a separate buffer. As a basic sanity
 * check, the original write-buffer values are compared with values read to
 * a separate buffer.  An LED on the development board is illuminated when there
 * is a match between the written and read data.
 *
 * \return Nothing.
 */
int main(void)
{
	mem_type_t mem;

	sysclk_init();
	board_init();

	/* Test internal flash */
	mem = INT_FLASH;
	if (test_mem(mem, (uint32_t)TEST_ADDRESS_INT) == STATUS_OK) {
		/* Turn on LED to indicate success */
		ioport_set_pin_level(NVM_EXAMPLE_LED0, false);
	}

#if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
	/* Test external dataflash */
	mem = AT45DBX;
	if (test_mem(mem, (uint32_t)TEST_ADDRESS_EXT) == STATUS_OK) {
		/* Turn on LED to indicate success */
		ioport_set_pin_level(NVM_EXAMPLE_LED1, false);
	}
#endif

	/* Turn on LED to indicate tests are complete */
	ioport_set_pin_level(NVM_EXAMPLE_LED2, false);

	while (1) {
	}
}
Пример #2
0
int main(int argc, char* argv[])
{
	bool use_mmap = false;
	int ch, max = 100000;

	while ((ch = getopt(argc, argv, "hmn:")) > 0)
	{
		switch (ch)
		{
		case 'h':
			usage(argv[0]);
			return 0;
		case 'm':
			use_mmap = true;
			break;
		case 'n':
			max = atoi(optarg);
			break;
		default:
			break;
		}
	}

	if (use_mmap)
		test_mmap(max);
	else
		test_mem(max);

	return (0);
}
Пример #3
0
/*===========================================================================*
 *			       sef_cb_init_fresh			     *
 *===========================================================================*/
static int sef_cb_init_fresh(int UNUSED(type), sef_init_info_t *UNUSED(info))
{
	/* Run all the tests. */
	test_u32();
	test_str();
	test_mem();
	test_map();
	test_label();

	return OK;
}
Пример #4
0
int
main(int argc, char *argv[])
{
    if (0) {
	test_signal();
    }

    if (1) {
	test_mem();
    }

    return 0;
}
Пример #5
0
/*===========================================================================*
 *				main					     *
 *===========================================================================*/
int main(void)
{
	/* SEF local startup. */
	sef_local_startup();

	/* Run all the tests. */
	test_u32();
	test_str();
	test_mem();
	test_map();
	test_label();

	return 0;
}
Пример #6
0
int main(int argc, char *argv[]) {
    srand(time(NULL));
    read_args(argc, argv);

    alc_init(amount);
    printf("\n");
    mem_dump();
    printf("\n");

    if (test) {
        test_mem();
    }

    if (stats) {
        get_stats();
    }
}
Пример #7
0
void start()
{
	while( 1 ) {
		led_with_enable(1, 3);

		test_mem(10, (uint32_t*)0x40000100, (uint32_t*)0x40003f00);	
		if( error > 0 )
			led_with_enable(3, 3);

		/*test_fixedpoint(0x7fffffff);*/
		test_fixedpoint(100000000);
		if( error > 0 )
			led_with_enable(3, 3);

		test_mult(1000);

		if( error > 0 )
			led_with_enable(1, 3);
		else
			led_with_enable(0, 3);
	}
}
Пример #8
0
int main(int argc, char **argv) {
	if (argc > 1) {
		if (!strcmp(argv[1], "v")) {
			Verbose = 1;
		}
		else if (!strcmp(argv[1], "test-stdout")) {
			test_stdout();
			return EXIT_SUCCESS;
		}
		if (!strcmp(argv[1], "test-atexit")) {
			test_atexit();
			return EXIT_SUCCESS;
		}
	}
	test_mem();
	test_str();
	test_sprintf();
	test_math();
	test_proc();
	test_stdio();
	test_file();
	test_exit();
	return EXIT_FAILURE;
}
Пример #9
0
void do_test()
{
    test_mem();
}
Пример #10
0
int main(int argc, char **argv)
{
	debug_init(stdout);
	save_fx(fx_orig);
	memcpy(&fx_orig[240], scratch_orig, 4*sizeof(long));
	memcpy(&fx_orig[256], taint_orig, 8*sizeof(long));
	offset = (long)taintmem_test - (long)mem_test;
	codeexec(NULL, 0, (long *)regs_orig);

	init_threads();

	test_reg2(taint_copy_reg32_to_reg32, ref_copy_reg32_to_reg32);
	test_reg2(taint_copy_reg16_to_reg16, ref_copy_reg16_to_reg16);
	test_reg2(taint_copy_reg8_to_reg8, ref_copy_reg8_to_reg8);

	test_mem(taint_copy_mem32_to_reg32, ref_copy_mem32_to_reg32);
	test_mem(taint_copy_mem16_to_reg16, ref_copy_mem16_to_reg16);
	test_mem(taint_copy_mem8_to_reg8, ref_copy_mem8_to_reg8);

	test_mem(taint_copy_reg32_to_mem32, ref_copy_reg32_to_mem32);
	test_mem(taint_copy_reg16_to_mem16, ref_copy_reg16_to_mem16);
	test_mem(taint_copy_reg8_to_mem8, ref_copy_reg8_to_mem8);

	test_stackop(taint_copy_push_reg32, ref_copy_push_reg32);
	test_stackop(taint_copy_push_reg16, ref_copy_push_reg16);

	test_mem(taint_copy_push_mem32, ref_copy_push_mem32);
	test_mem(taint_copy_push_mem16, ref_copy_push_mem16);

	test_stackop(taint_copy_pop_reg32, ref_copy_pop_reg32);
	test_stackop(taint_copy_pop_reg16, ref_copy_pop_reg16);

	test_mem(taint_copy_pop_mem32, ref_copy_pop_mem32);
	test_mem(taint_copy_pop_mem16, ref_copy_pop_mem16);

	test_addr(taint_copy_eax_to_addr32, ref_copy_eax_to_addr32);
	test_addr(taint_copy_ax_to_addr16, ref_copy_ax_to_addr16);
	test_addr(taint_copy_al_to_addr8, ref_copy_al_to_addr8);

	test_addr(taint_copy_addr32_to_eax, ref_copy_addr32_to_eax);
	test_addr(taint_copy_addr16_to_ax, ref_copy_addr16_to_ax);
	test_addr(taint_copy_addr8_to_al, ref_copy_addr8_to_al);

	test_impl(taint_copy_eax_to_str32, ref_copy_eax_to_str32);
	test_impl(taint_copy_ax_to_str16, ref_copy_ax_to_str16);
	test_impl(taint_copy_al_to_str8, ref_copy_al_to_str8);

	test_impl(taint_copy_str32_to_eax, ref_copy_str32_to_eax);
	test_impl(taint_copy_str16_to_ax, ref_copy_str16_to_ax);
	test_impl(taint_copy_str8_to_al, ref_copy_str8_to_al);

	test_impl(taint_copy_str32_to_str32, ref_copy_str32_to_str32);
	test_impl(taint_copy_str16_to_str16, ref_copy_str16_to_str16);
	test_impl(taint_copy_str8_to_str8, ref_copy_str8_to_str8);

	test_reg(taint_erase_reg32, ref_erase_reg32);
	test_reg(taint_erase_reg16, ref_erase_reg16);
	test_reg(taint_erase_reg8, ref_erase_reg8);

	test_mem(taint_erase_mem32, ref_erase_mem32);
	test_mem(taint_erase_mem16, ref_erase_mem16);
	test_mem(taint_erase_mem8, ref_erase_mem8);

	test_reg(taint_erase_hireg16, ref_erase_hireg16);

	test_impl(taint_erase_push32, ref_erase_push32);
	test_impl(taint_erase_push16, ref_erase_push16);

	test_reg2(taint_or_reg32_to_reg32, ref_or_reg32_to_reg32);
	test_reg2(taint_or_reg16_to_reg16, ref_or_reg16_to_reg16);
	test_reg2(taint_or_reg8_to_reg8, ref_or_reg8_to_reg8);

	test_mem(taint_or_reg32_to_mem32, ref_or_reg32_to_mem32);
	test_mem(taint_or_reg16_to_mem16, ref_or_reg16_to_mem16);
	test_mem(taint_or_reg8_to_mem8, ref_or_reg8_to_mem8);

	test_mem(taint_or_mem32_to_reg32, ref_or_mem32_to_reg32);
	test_mem(taint_or_mem16_to_reg16, ref_or_mem16_to_reg16);
	test_mem(taint_or_mem8_to_reg8, ref_or_mem8_to_reg8);

	test_mem(taint_xor_reg32_to_mem32, ref_xor_reg32_to_mem32);
	test_mem(taint_xor_reg16_to_mem16, ref_xor_reg16_to_mem16);
	test_mem(taint_xor_reg8_to_mem8, ref_xor_reg8_to_mem8);

	test_mem(taint_xor_mem32_to_reg32, ref_xor_mem32_to_reg32);
	test_mem(taint_xor_mem16_to_reg16, ref_xor_mem16_to_reg16);
	test_mem(taint_xor_mem8_to_reg8, ref_xor_mem8_to_reg8);

	test_reg2(taint_swap_reg32_reg32, ref_swap_reg32_reg32);
	test_reg2(taint_swap_reg16_reg16, ref_swap_reg16_reg16);
	test_reg2(taint_swap_reg8_reg8, ref_swap_reg8_reg8);

	test_mem(taint_swap_reg32_mem32, ref_swap_reg32_mem32);
	test_mem(taint_swap_reg16_mem16, ref_swap_reg16_mem16);
	test_mem(taint_swap_reg8_mem8, ref_swap_reg8_mem8);

	test_reg2(taint_copy_reg16_to_reg32, ref_copy_reg16_to_reg32);
	test_reg2(taint_copy_reg8_to_reg32, ref_copy_reg8_to_reg32);
	test_reg2(taint_copy_reg8_to_reg16, ref_copy_reg8_to_reg16);

	test_mem(taint_copy_mem16_to_reg32, ref_copy_mem16_to_reg32);
	test_mem(taint_copy_mem8_to_reg32, ref_copy_mem8_to_reg32);
	test_mem(taint_copy_mem8_to_reg16, ref_copy_mem8_to_reg16);

	test_impl2(taint_erase_eax_edx, ref_erase_eax_edx);
	test_impl2(taint_erase_ax_dx, ref_erase_ax_dx);
	test_impl2(taint_erase_eax, ref_erase_eax);
	test_impl2(taint_erase_ax, ref_erase_ax);
	test_impl2(taint_erase_al, ref_erase_al);

	test_pushpop(taint_copy_popa32, ref_copy_popa32, (long)mem_test);
	test_pushpop(taint_copy_popa16, ref_copy_popa16, (long)mem_test);

	test_pushpop(taint_copy_pusha32, ref_copy_pusha32, 32+(long)mem_test);
	test_pushpop(taint_copy_pusha16, ref_copy_pusha16, 32+(long)mem_test);

	test_impl(taint_leave32, ref_leave32);
	test_impl(taint_leave16, ref_leave16);

	test_cmpxchg(taint_cmpxchg8_pre, taint_cmpxchg8_post, ref_cmpxchg8);
	test_cmpxchg(taint_cmpxchg16_pre, taint_cmpxchg16_post, ref_cmpxchg16);
	test_cmpxchg(taint_cmpxchg32_pre, taint_cmpxchg32_post, ref_cmpxchg32);
	test_cmpxchg(taint_cmpxchg8b_pre, taint_cmpxchg8b_post, ref_cmpxchg8b);

	mrm_generator(test_lea);

	exit(err);
}
Пример #11
0
int main(void) {
  LPC_GPIO2->FIODIR = BV(4) | BV(5);
  LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
  BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
  LPC_GPIO0->FIODIR = BV(16);

 /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
  LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
                      | BV(3) | BV(5);                    /* SSP0 (FPGA) except SS */
  LPC_PINCON->PINSEL0 = BV(31);                            /* SSP0 */
/*                      | BV(13) | BV(15) | BV(17) | BV(19)  SSP1 (SD) */

 /* pull-down CIC data lines */
  LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3);

  clock_disconnect();
  snes_init();
  snes_reset(1);
  power_init();
  timer_init();
  uart_init();
  fpga_spi_init();
  spi_preinit();
  led_init();
 /* do this last because the peripheral init()s change PCLK dividers */
  clock_init();
  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
led_pwm();
  sdn_init();
  printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
  printf("PCONP=%lx\n", LPC_SC->PCONP);

  file_init();
  cic_init(0);
/* setup timer (fpga clk) */
  LPC_TIM3->CTCR=0;
  LPC_TIM3->EMR=EMC0TOGGLE;
  LPC_TIM3->MCR=MR0R;
  LPC_TIM3->MR0=1;
  LPC_TIM3->TCR=1;
  fpga_init();

  char *testnames[11] = { "SD      ", "USB     ", "RTC     ", "CIC     ",
                          "FPGA    ", "RAM     ", "CLK     ", "DAC     ",
                          "SNES IRQ", "SNES RAM", "SNES PA "};

  char *teststate_names [3] = { "no run", "\x1b[32;1mPassed\x1b[m", "\x1b[31;1mFAILED\x1b[m" };

  int testresults[11] = { NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN,
                          NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN,
                          NO_RUN };

  testresults[TEST_SD] = test_sd();
//testresults[TEST_USB] = test_usb();
  testresults[TEST_RTC] = test_rtc();
  delay_ms(209);
  testresults[TEST_CIC] = test_cic();
  testresults[TEST_FPGA] = test_fpga();
  testresults[TEST_RAM] = test_mem();
  printf("Loading SNES test ROM\n=====================\n");
  load_rom((uint8_t*)"/sd2snes/test.bin", 0, LOADROM_WITH_RESET);
  printf("\n\n\n");
  delay_ms(1000);
  testresults[TEST_CLK] = test_clk();
  fpga_set_bram_addr(0x1fff);
  fpga_write_bram_data(0x01); // tell SNES test program to continue
  uint8_t snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank;
  uint8_t snestest_irq_done = 0, snestest_pa_done = 0, snestest_mem_done = 0;
  uint8_t last_irq_state = 0x77, last_pa_state = 0x77, last_mem_state = 0x77, last_mem_bank = 0x77;
  uint32_t failed_addr = 0;
  while(!(snestest_irq_done & snestest_pa_done & snestest_mem_done)) {
    fpga_set_bram_addr(0);
    snestest_irq_state = fpga_read_bram_data();
    snestest_mem_state = fpga_read_bram_data();
    snestest_pa_state = fpga_read_bram_data();
    snestest_mem_bank = fpga_read_bram_data();
    if(snestest_irq_state != last_irq_state
       || snestest_mem_state != last_mem_state
       || snestest_pa_state != last_pa_state
       || snestest_mem_bank != last_mem_bank) {
      printf("SNES test status: IRQ: %02x   PA: %02x   MEM: %02x/%02x\r", snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank);
    }
    last_irq_state = snestest_irq_state;
    last_mem_state = snestest_mem_state;
    last_pa_state = snestest_pa_state;
    last_mem_bank = snestest_mem_bank;
    if(snestest_pa_state != 0x00) snestest_pa_done = 1;
    if(snestest_irq_state != 0x00) snestest_irq_done = 1;
    if(snestest_mem_state == 0xff || snestest_mem_state == 0x5a) snestest_mem_done = 1;
    cli_entrycheck();
  }
  printf("\n");
  if(snestest_pa_state == 0xff) testresults[TEST_SNES_PA] = FAILED;
  else testresults[TEST_SNES_PA] = PASSED;
  if(snestest_irq_state == 0xff) testresults[TEST_SNES_IRQ] = FAILED;
  else testresults[TEST_SNES_IRQ] = PASSED;
  if(snestest_mem_state == 0xff) {
    testresults[TEST_SNES_RAM] = FAILED;
    fpga_set_bram_addr(4);
    failed_addr = fpga_read_bram_data();
    failed_addr |= fpga_read_bram_data() << 8;
    failed_addr |= fpga_read_bram_data() << 16;
    printf("SNES MEM test FAILED (failed address: %06lx)\n", failed_addr);
  }
  else testresults[TEST_SNES_RAM] = PASSED;
  printf("\n\nTEST SUMMARY\n============\n\n");
  printf("Test      Result\n----------------\n");
  int testcount;
  for(testcount=0; testcount < 11; testcount++) {
    printf("%s  %s\n", testnames[testcount], teststate_names[testresults[testcount]]);
  }
  cli_loop();
  while(1);
}