int
main(void)
{
u2_init();
putstr("\nFactory Test, Board Rev 3.0\n");
bool ok = true;
unsigned char maj = HW_REV_MAJOR;
unsigned char min = HW_REV_MINOR;
ok = eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_MSB, &maj, 1);
ok &= eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_LSB, &min, 1);
putstr("\nset_hw_rev\n");
if (ok)
printf("OK: set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
else {
printf("FAILED to set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
hal_finish();
return 0;
}
if(test_sd())
puts("SD OK\n");
else {
puts("SD FAIL\n");
//hal_finish();
//return 0;
}
if(test_ram())
puts("RAM OK\n");
else {
puts("RAM FAIL\n");
hal_finish();
return 0;
}
print_mac_addr(ethernet_mac_addr()->addr);
newline();
clocks_mimo_config(MC_WE_LOCK_TO_SMA);
while (!clocks_lock_detect()) {
puts("No Lock");
mdelay(1000);
}
puts("Clock Locked\n");
}
int _start(int argc, char *argv[]) {
printf("-- TEST BEGIN\n");
test_lb();
test_lbu();
test_ld();
test_lh();
test_lhu();
test_lw();
test_lwl_lwr();
test_sb();
test_sd();
test_sh();
test_sw();
test_swl_swr();
printf("-- TEST END\n");
return 0;
}
int
main(void)
{
u2_init();
putstr("\nFactory Test\n");
print_mac_addr(ethernet_mac_addr()->addr);
newline();
if(test_sd())
puts("SD OK\n");
else {
puts("SD FAIL\n");
// hal_finish();
//return 0;
}
if(test_ram())
puts("RAM OK\n");
else {
puts("RAM FAIL\n");
hal_finish();
return 0;
}
print_mac_addr(ethernet_mac_addr()->addr);
newline();
output_regs->led_src = 0x7; // make bottom 3 controlled by HW
ethernet_register_link_changed_callback(link_changed_callback);
ethernet_init();
clocks_enable_tx_dboard(true,1);
clocks_mimo_config(MC_WE_LOCK_TO_SMA);
#if 0
// make bit 15 of Tx gpio's be a s/w output
hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000);
#endif
output_regs->debug_mux_ctrl = 1;
#if 0
hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff);
hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff);
#endif
// initialize double buffering state machine for ethernet -> DSP Tx
dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0,
&dsp_tx_recv_args, &dsp_tx_send_args,
eth_pkt_inspector);
// initialize double buffering state machine for DSP RX -> Ethernet
if (FW_SETS_SEQNO){
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
fw_sets_seqno_inspector);
}
else {
dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0,
&dsp_rx_recv_args, &dsp_rx_send_args,
dbsm_nop_inspector);
}
// tell app_common that this dbsm could be sending to the ethernet
ac_could_be_sending_to_eth = &dsp_rx_sm;
// program tx registers
setup_tx();
// kick off the state machine
dbsm_start(&dsp_tx_sm);
//int which = 0;
while(1){
// hal_gpio_write(GPIO_TX_BANK, which, 0x8000);
// which ^= 0x8000;
buffer_irq_handler(0);
int pending = pic_regs->pending; // poll for under or overrun
if (pending & PIC_UNDERRUN_INT){
dbsm_handle_tx_underrun(&dsp_tx_sm);
pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt
putchar('U');
}
if (pending & PIC_OVERRUN_INT){
dbsm_handle_rx_overrun(&dsp_rx_sm);
pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt
// FIXME Figure out how to handle this robustly.
// Any buffers that are emptying should be allowed to drain...
if (streaming_p){
// restart_streaming();
// FIXME report error
}
else {
// FIXME report error
}
putchar('O');
}
}
}
int main(void) {
LPC_GPIO2->FIODIR = BV(4) | BV(5);
LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
LPC_GPIO0->FIODIR = BV(16);
/* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
| BV(3) | BV(5); /* SSP0 (FPGA) except SS */
LPC_PINCON->PINSEL0 = BV(31); /* SSP0 */
/* | BV(13) | BV(15) | BV(17) | BV(19) SSP1 (SD) */
/* pull-down CIC data lines */
LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3);
clock_disconnect();
snes_init();
snes_reset(1);
power_init();
timer_init();
uart_init();
fpga_spi_init();
spi_preinit();
led_init();
/* do this last because the peripheral init()s change PCLK dividers */
clock_init();
LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */
led_pwm();
sdn_init();
printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
printf("PCONP=%lx\n", LPC_SC->PCONP);
file_init();
cic_init(0);
/* setup timer (fpga clk) */
LPC_TIM3->CTCR=0;
LPC_TIM3->EMR=EMC0TOGGLE;
LPC_TIM3->MCR=MR0R;
LPC_TIM3->MR0=1;
LPC_TIM3->TCR=1;
fpga_init();
char *testnames[11] = { "SD ", "USB ", "RTC ", "CIC ",
"FPGA ", "RAM ", "CLK ", "DAC ",
"SNES IRQ", "SNES RAM", "SNES PA "};
char *teststate_names [3] = { "no run", "\x1b[32;1mPassed\x1b[m", "\x1b[31;1mFAILED\x1b[m" };
int testresults[11] = { NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN,
NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN,
NO_RUN };
testresults[TEST_SD] = test_sd();
//testresults[TEST_USB] = test_usb();
testresults[TEST_RTC] = test_rtc();
delay_ms(209);
testresults[TEST_CIC] = test_cic();
testresults[TEST_FPGA] = test_fpga();
testresults[TEST_RAM] = test_mem();
printf("Loading SNES test ROM\n=====================\n");
load_rom((uint8_t*)"/sd2snes/test.bin", 0, LOADROM_WITH_RESET);
printf("\n\n\n");
delay_ms(1000);
testresults[TEST_CLK] = test_clk();
fpga_set_bram_addr(0x1fff);
fpga_write_bram_data(0x01); // tell SNES test program to continue
uint8_t snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank;
uint8_t snestest_irq_done = 0, snestest_pa_done = 0, snestest_mem_done = 0;
uint8_t last_irq_state = 0x77, last_pa_state = 0x77, last_mem_state = 0x77, last_mem_bank = 0x77;
uint32_t failed_addr = 0;
while(!(snestest_irq_done & snestest_pa_done & snestest_mem_done)) {
fpga_set_bram_addr(0);
snestest_irq_state = fpga_read_bram_data();
snestest_mem_state = fpga_read_bram_data();
snestest_pa_state = fpga_read_bram_data();
snestest_mem_bank = fpga_read_bram_data();
if(snestest_irq_state != last_irq_state
|| snestest_mem_state != last_mem_state
|| snestest_pa_state != last_pa_state
|| snestest_mem_bank != last_mem_bank) {
printf("SNES test status: IRQ: %02x PA: %02x MEM: %02x/%02x\r", snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank);
}
last_irq_state = snestest_irq_state;
last_mem_state = snestest_mem_state;
last_pa_state = snestest_pa_state;
last_mem_bank = snestest_mem_bank;
if(snestest_pa_state != 0x00) snestest_pa_done = 1;
if(snestest_irq_state != 0x00) snestest_irq_done = 1;
if(snestest_mem_state == 0xff || snestest_mem_state == 0x5a) snestest_mem_done = 1;
cli_entrycheck();
}
printf("\n");
if(snestest_pa_state == 0xff) testresults[TEST_SNES_PA] = FAILED;
else testresults[TEST_SNES_PA] = PASSED;
if(snestest_irq_state == 0xff) testresults[TEST_SNES_IRQ] = FAILED;
else testresults[TEST_SNES_IRQ] = PASSED;
if(snestest_mem_state == 0xff) {
testresults[TEST_SNES_RAM] = FAILED;
fpga_set_bram_addr(4);
failed_addr = fpga_read_bram_data();
failed_addr |= fpga_read_bram_data() << 8;
failed_addr |= fpga_read_bram_data() << 16;
printf("SNES MEM test FAILED (failed address: %06lx)\n", failed_addr);
}
else testresults[TEST_SNES_RAM] = PASSED;
printf("\n\nTEST SUMMARY\n============\n\n");
printf("Test Result\n----------------\n");
int testcount;
for(testcount=0; testcount < 11; testcount++) {
printf("%s %s\n", testnames[testcount], teststate_names[testresults[testcount]]);
}
cli_loop();
while(1);
}
