void m72_ym2151_irq_handler(running_device *device, int irq)
{
if (irq)
timer_call_after_resynch(device->machine, NULL, YM2151_ASSERT,setvector_callback);
else
timer_call_after_resynch(device->machine, NULL, YM2151_CLEAR,setvector_callback);
}
static void t5182_ym2151_irq_handler(int irq)
{
if (irq)
timer_call_after_resynch(NULL, YM2151_ASSERT,setirq_callback);
else
timer_call_after_resynch(NULL, YM2151_CLEAR,setirq_callback);
}
void cpunum_set_input_line_and_vector(int cpunum, int line, int state, int vector)
{
if (line >= 0 && line < MAX_INPUT_LINES)
{
INT32 input_event = (state & 0xff) | (vector << 8);
int event_index = input_event_index[cpunum][line]++;
LOG(("cpunum_set_input_line_and_vector(%d,%d,%d,%02x)\n", cpunum, line, state, vector));
/* if we're full of events, flush the queue and log a message */
if (event_index >= MAX_INPUT_EVENTS)
{
input_event_index[cpunum][line]--;
cpunum_empty_event_queue(Machine, NULL, cpunum | (line << 8));
event_index = input_event_index[cpunum][line]++;
logerror("Exceeded pending input line event queue on CPU %d!\n", cpunum);
}
/* enqueue the event */
if (event_index < MAX_INPUT_EVENTS)
{
input_event_queue[cpunum][line][event_index] = input_event;
/* if this is the first one, set the timer */
if (event_index == 0)
timer_call_after_resynch(NULL, cpunum | (line << 8), cpunum_empty_event_queue);
}
}
}
static WRITE32_HANDLER(latch32_w)
{
if(!offset)
latches[2]|=1;
COMBINE_DATA(&latches[offset]);
timer_call_after_resynch(NULL, 0, NULL);
}
static WRITE8_HANDLER(latch8_w)
{
if(!offset)
latches[2]|=2;
latches[offset]=data;
timer_call_after_resynch(NULL, 0, NULL);
}
static READ8_HANDLER( fromance_busycheck_main_r )
{
/* set a timer to force synchronization after the read */
timer_call_after_resynch(space->machine, NULL, 0, NULL);
if (!fromance_directionflag) return 0x00; // standby
else return 0xff; // busy
}
static READ8_HANDLER(beg_soundstate_r)
{
UINT8 ret = sound_state;
/* set a timer to force synchronization after the read */
timer_call_after_resynch(NULL, 0, NULL);
sound_state &= ~2; /* read from port 21 clears bit 1 in status */
return ret;
}
void cpu_interrupt_enable(int cpunum, int enabled)
{
assert_always(cpunum >= 0 && cpunum < cpu_gettotalcpu(), "cpu_interrupt_enable() called for invalid cpu num!");
/* set the new state */
interrupt_enable[cpunum] = enabled;
/* make sure there are no queued interrupts */
if (enabled == 0)
timer_call_after_resynch(NULL, cpunum, clear_all_lines);
}
static READ8_HANDLER( beg_status_r )
{
/* d0 = Q of 74ls74 IC13(partA)
d1 = Q of 74ls74 IC13(partB)
d2 =
d3 =
d4 =
d5 =
d6 = d7 = 10MHz/2
*/
/* set a timer to force synchronization after the read */
timer_call_after_resynch(NULL, 0, NULL);
return (beg13_ls74[0]<<0) | (beg13_ls74[1]<<1);
}
void namco_54xx_write(UINT8 data)
{
int cpunum = mame_find_cpu_index(Machine, CPUTAG_54XX);
if (cpunum == -1)
return;
timer_call_after_resynch(NULL, data, namco_54xx_latch_callback);
cpunum_set_input_line(Machine, cpunum, 0, ASSERT_LINE);
// The execution time of one instruction is ~4us, so we must make sure to
// give the cpu time to poll the /IRQ input before we clear it.
// The input clock to the 06XX interface chip is 64H, that is
// 18432000/6/64 = 48kHz, so it makes sense for the irq line to be
// asserted for one clock cycle ~= 21us.
timer_set(ATTOTIME_IN_USEC(21), NULL, cpunum, namco_54xx_irq_clear);
}
static WRITE8_HANDLER( mmc1_rom_switch_w )
{
/* basically, a MMC1 mapper from the nes */
static int size16k, switchlow, vrom4k;
if ( multigam_mmc1_reg_write_enable == 0 )
{
return;
}
else
{
multigam_mmc1_reg_write_enable = 0;
timer_call_after_resynch(space->machine, NULL, 0, mmc1_resync_callback);
}
int reg = (offset >> 13);
/* reset mapper */
if (data & 0x80)
{
mmc1_shiftreg = mmc1_shiftcount = 0;
size16k = 1;
switchlow = 1;
vrom4k = 0;
return;
}
/* see if we need to clock in data */
if (mmc1_shiftcount < 5)
{
mmc1_shiftreg >>= 1;
mmc1_shiftreg |= (data & 1) << 4;
mmc1_shiftcount++;
}
static WRITE8_HANDLER( fromance_commanddata_w )
{
/* do this on a timer to let the slave CPU synchronize */
timer_call_after_resynch(space->machine, NULL, data, deferred_commanddata_w);
}
void z80dma_device::rdy_w(int state)
{
if (LOG) logerror("Z80DMA '%s' RDY: %d Active High: %d\n", tag(), state, READY_ACTIVE_HIGH);
timer_call_after_resynch(&m_machine, (void *)this, state, static_rdy_write_callback);
}
static WRITE16_HANDLER( sound_command_w )
{
if (ACCESSING_BITS_0_7)
timer_call_after_resynch(space->machine, NULL, data & 0xff, sound_command_w_callback);
}
static WRITE16_HANDLER( sound_latch_w )
{
if (ACCESSING_BITS_0_7)
timer_call_after_resynch(space->machine, NULL, data & 0xff, sound_delayed_w);
}
static WRITE8_HANDLER( t5182_cpu_irq_ack_w )
{
timer_call_after_resynch(NULL, CPU_CLEAR,setirq_callback);
}
static WRITE8_HANDLER( sound_to_main_w )
{
timer_call_after_resynch(NULL, data, sound_to_main_callback);
}
void namco_50xx_read_request(const device_config *device)
{
timer_call_after_resynch(device->machine, (void *)device, 0, namco_50xx_readrequest_callback);
namco_50xx_irq_set(device);
}
static WRITE8_HANDLER (beg13B_set_w)
{
timer_call_after_resynch(NULL, (1<<8) | 1, deferred_ls74_w);
}
static WRITE8_HANDLER( bombjack_soundlatch_w )
{
/* make all the CPUs synchronize, and only AFTER that write the new command to the latch */
timer_call_after_resynch(NULL, data,soundlatch_callback);
}
static WRITE16_HANDLER( sound_latch_w )
{
if (ACCESSING_LSB)
timer_call_after_resynch(NULL, data & 0xff, sound_delayed_w);
}
INLINE void latch_w(const address_space *space, int which, UINT16 value)
{
timer_call_after_resynch(space->machine, NULL, which | (value << 8), latch_callback);
}
static WRITE16_HANDLER( main_sound_w )
{
if (ACCESSING_BITS_0_7)
timer_call_after_resynch(NULL, data & 0xff, delayed_sound_w);
}
/* 8741 update */
static void taito8741_update(const address_space *space, int num)
{
I8741 *st,*sst;
int next = num;
int data;
do{
num = next;
st = &taito8741[num];
if( st->connect != -1 )
sst = &taito8741[st->connect];
else sst = 0;
next = -1;
/* check pending command */
switch(st->phase)
{
case CMD_08: /* serial data latch */
if( st->serial_out)
{
st->status &= 0xfb; /* patch for gsword */
st->phase = CMD_IDLE;
next = num; /* continue this chip */
}
break;
case CMD_4a: /* wait for syncronus ? */
if(!st->pending4a)
{
taito8741_hostdata_w(st,0);
st->phase = CMD_IDLE;
next = num; /* continue this chip */
}
break;
case CMD_IDLE:
/* ----- data in port check ----- */
data = taito8741_hostdata_r(st);
if( data != -1 )
{
switch(st->mode)
{
case TAITO8741_MASTER:
case TAITO8741_SLAVE:
/* buffering transmit data */
if( st->txpoint < 8 )
{
//if (st->txpoint == 0 && num==1 && data&0x80) logerror("Coin Put\n");
st->txd[st->txpoint++] = data;
}
break;
case TAITO8741_PORT:
if( data & 0xf8)
{ /* ?? */
}
else
{ /* port select */
st->parallelselect = data & 0x07;
taito8741_hostdata_w(st,st->portHandler ? st->portHandler(space,st->parallelselect) : st->portName ? input_port_read(space->machine, st->portName) : 0);
}
}
}
/* ----- new command fetch ----- */
data = taito8741_hostcmd_r(st);
switch( data )
{
case -1: /* no command data */
break;
case 0x00: /* read from parallel port */
taito8741_hostdata_w(st,st->portHandler ? st->portHandler(space,0) : st->portName ? input_port_read(space->machine, st->portName) : 0 );
break;
case 0x01: /* read receive buffer 0 */
case 0x02: /* read receive buffer 1 */
case 0x03: /* read receive buffer 2 */
case 0x04: /* read receive buffer 3 */
case 0x05: /* read receive buffer 4 */
case 0x06: /* read receive buffer 5 */
case 0x07: /* read receive buffer 6 */
//if (data == 2 && num==0 && st->rxd[data-1]&0x80) logerror("Coin Get\n");
taito8741_hostdata_w(st,st->rxd[data-1]);
break;
case 0x08: /* latch received serial data */
st->txd[0] = st->portHandler ? st->portHandler(space,0) : st->portName ? input_port_read(space->machine, st->portName) : 0;
if( sst )
{
timer_call_after_resynch(space->machine, NULL, num, taito8741_serial_tx);
st->serial_out = 0;
st->status |= 0x04;
st->phase = CMD_08;
}
break;
case 0x0a: /* 8741-0 : set serial comminucation mode 'MASTER' */
//st->mode = TAITO8741_MASTER;
break;
case 0x0b: /* 8741-1 : set serial comminucation mode 'SLAVE' */
//st->mode = TAITO8741_SLAVE;
break;
case 0x1f: /* 8741-2,3 : ?? set parallelport mode ?? */
case 0x3f: /* 8741-2,3 : ?? set parallelport mode ?? */
case 0xe1: /* 8741-2,3 : ?? set parallelport mode ?? */
st->mode = TAITO8741_PORT;
st->parallelselect = 1; /* preset read number */
break;
case 0x62: /* 8741-3 : ? */
break;
case 0x4a: /* ?? syncronus with other cpu and return 00H */
if( sst )
{
if(sst->pending4a)
{
sst->pending4a = 0; /* syncronus */
taito8741_hostdata_w(st,0); /* return for host */
next = st->connect;
}
else st->phase = CMD_4a;
}
break;
case 0x80: /* 8741-3 : return check code */
taito8741_hostdata_w(st,0x66);
break;
case 0x81: /* 8741-2 : return check code */
taito8741_hostdata_w(st,0x48);
break;
case 0xf0: /* GSWORD 8741-1 : initialize ?? */
break;
case 0x82: /* GSWORD 8741-2 unknown */
break;
}
break;
}
}while(next>=0);
}
static WRITE8_HANDLER( main_to_sound_w )
{
timer_call_after_resynch(NULL, data, main_to_sound_callback);
}
static WRITE8_HANDLER(protection_w)
{
timer_call_after_resynch(NULL, data, protection_deferred_w);
cpu_boost_interleave(attotime_zero, ATTOTIME_IN_USEC(100));
}
static WRITE8_HANDLER( sound_command_w )
{
soundlatch_w(space, 0, data);
timer_call_after_resynch(space->machine, NULL, data, nmi_callback);
}
static WRITE8_HANDLER( t5182_ym2151_irq_ack_w )
{
timer_call_after_resynch(NULL, YM2151_ACK,setirq_callback);
}
static READ8_HANDLER( mcu_acknowledge_r )
{
timer_call_after_resynch(space->machine, NULL, 0, mcu_acknowledge_callback);
return 0;
}
static WRITE8_HANDLER( sound_command_w )
{
timer_call_after_resynch(NULL, data, delayed_command_w);
}
