int domain_vtimer_init(struct domain *d)
{
d->arch.phys_timer_base.offset = NOW();
d->arch.virt_timer_base.offset = READ_SYSREG64(CNTPCT_EL0);
/* At this stage vgic_reserve_virq can't fail */
if ( is_hardware_domain(d) )
{
if ( !vgic_reserve_virq(d, timer_get_irq(TIMER_PHYS_SECURE_PPI)) )
BUG();
if ( !vgic_reserve_virq(d, timer_get_irq(TIMER_PHYS_NONSECURE_PPI)) )
BUG();
if ( !vgic_reserve_virq(d, timer_get_irq(TIMER_VIRT_PPI)) )
BUG();
}
else
{
if ( !vgic_reserve_virq(d, GUEST_TIMER_PHYS_S_PPI) )
BUG();
if ( !vgic_reserve_virq(d, GUEST_TIMER_PHYS_NS_PPI) )
BUG();
if ( !vgic_reserve_virq(d, GUEST_TIMER_VIRT_PPI) )
BUG();
}
return 0;
}
int vcpu_vtimer_init(struct vcpu *v)
{
struct vtimer *t = &v->arch.phys_timer;
bool_t d0 = is_hardware_domain(v->domain);
/*
* Hardware domain uses the hardware interrupts, guests get the virtual
* platform.
*/
init_timer(&t->timer, phys_timer_expired, t, v->processor);
t->ctl = 0;
t->cval = NOW();
t->irq = d0
? timer_get_irq(TIMER_PHYS_NONSECURE_PPI)
: GUEST_TIMER_PHYS_NS_PPI;
t->v = v;
t = &v->arch.virt_timer;
init_timer(&t->timer, virt_timer_expired, t, v->processor);
t->ctl = 0;
t->irq = d0
? timer_get_irq(TIMER_VIRT_PPI)
: GUEST_TIMER_VIRT_PPI;
t->v = v;
v->arch.vtimer_initialized = 1;
return 0;
}
int domain_vtimer_init(struct domain *d, struct xen_arch_domainconfig *config)
{
d->arch.phys_timer_base.offset = NOW();
d->arch.virt_timer_base.offset = READ_SYSREG64(CNTPCT_EL0);
d->time_offset_seconds = ticks_to_ns(d->arch.virt_timer_base.offset - boot_count);
do_div(d->time_offset_seconds, 1000000000);
config->clock_frequency = timer_dt_clock_frequency;
/* At this stage vgic_reserve_virq can't fail */
if ( is_hardware_domain(d) )
{
if ( !vgic_reserve_virq(d, timer_get_irq(TIMER_PHYS_SECURE_PPI)) )
BUG();
if ( !vgic_reserve_virq(d, timer_get_irq(TIMER_PHYS_NONSECURE_PPI)) )
BUG();
if ( !vgic_reserve_virq(d, timer_get_irq(TIMER_VIRT_PPI)) )
BUG();
}
else
{
if ( !vgic_reserve_virq(d, GUEST_TIMER_PHYS_S_PPI) )
BUG();
if ( !vgic_reserve_virq(d, GUEST_TIMER_PHYS_NS_PPI) )
BUG();
if ( !vgic_reserve_virq(d, GUEST_TIMER_VIRT_PPI) )
BUG();
}
return 0;
}
