/** Configure and enable RCC for peripherals (ADC1, ADC2, Timer) */
static inline void adc_init_rcc( void )
{
#if USE_AD1 || USE_AD2 || USE_AD3
uint32_t timer;
volatile uint32_t *rcc_apbenr;
uint32_t rcc_apb;
#if defined(USE_AD_TIM4)
timer = TIM4;
rcc_apbenr = &RCC_APB1ENR;
rcc_apb = RCC_APB1ENR_TIM4EN;
#elif defined(USE_AD_TIM1)
timer = TIM1;
rcc_apbenr = &RCC_APB2ENR;
rcc_apb = RCC_APB2ENR_TIM1EN;
#else
timer = TIM2;
rcc_apbenr = &RCC_APB1ENR;
rcc_apb = RCC_APB1ENR_TIM2EN;
#endif
/* Timer peripheral clock enable. */
rcc_peripheral_enable_clock(rcc_apbenr, rcc_apb);
#if defined(STM32F4)
adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2);
#endif
/* Enable ADC peripheral clocks. */
#if USE_AD1
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
#endif
#if USE_AD2
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC2EN);
#endif
#if USE_AD3
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC3EN);
#endif
/* Time Base configuration */
timer_reset(timer);
timer_set_mode(timer, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
#if defined(STM32F1)
timer_set_period(timer, 0xFF);
timer_set_prescaler(timer, 0x8);
#elif defined(STM32F4)
timer_set_period(timer, 0xFFFF);
timer_set_prescaler(timer, 0x53);
#endif
//timer_set_clock_division(timer, 0x0);
/* Generate TRGO on every update. */
timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE);
timer_enable_counter(timer);
#endif // USE_AD1 || USE_AD2 || USE_AD3
}
static void pwm_timer_init(pwm_callback update_callback) {
/** timer config **/
rcc_periph_clock_enable(RCC_TIM2);
timer_reset(TIM2);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(TIM2, 0);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_mode(TIM2, TIM_OC2, TIM_OCM_PWM2);
timer_enable_oc_output(TIM2, TIM_OC1);
timer_enable_oc_output(TIM2, TIM_OC2);
timer_set_period(TIM2, 1024-1);
timer_set_oc_value(TIM2, TIM_OC1, 0);
timer_set_oc_value(TIM2, TIM_OC2, 0);
timer_enable_counter(TIM2);
if ( update_callback != 0 ) {
pwm_update_callback = update_callback;
nvic_enable_irq(NVIC_TIM2_IRQ);
timer_enable_irq(TIM2, TIM_DIER_UIE);
}
}
/**
* Setup stepper motors' timer Tim
* N == 0 for TIM3, == 1 for TIM4
*/
static void setup_timer(uint8_t N){
uint32_t Tim;
switch (N){
case 0:
Tim = TIM3;
nvic_enable_irq(NVIC_TIM3_IRQ);
break;
case 1:
Tim = TIM4;
nvic_enable_irq(NVIC_TIM4_IRQ);
break;
default:
return;
}
timer_reset(Tim);
// timers have frequency of 2MHz, 2 pulse == 1 microstep
// 36MHz of APB1
timer_set_mode(Tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
// 72MHz div 36 = 2MHz
timer_set_prescaler(Tim, 35); // prescaler is (div - 1), 2pulse == 1 step
timer_continuous_mode(Tim); // automatically reload
timer_disable_preload(Tim); // force changing period
timer_set_period(Tim, Motor_period[N] - 1);
timer_enable_update_event(Tim);
timer_enable_irq(Tim, TIM_DIER_UIE); // update IRQ enable
timer_enable_counter(Tim);
timers_activated[N] = 1;
#ifdef EBUG
if(mode == BYTE_MODE){
lastsendfun('3' + N);
P(" timer\n", lastsendfun);
}
#endif
}
static void tim_setup()
{
//Some explanation: HCLK=72MHz
//APB1-Prescaler is 2 -> 36MHz
//Timer clock source is ABP1*2 because APB1 prescaler > 1
//So clock source is 72MHz (again)
//We want the timer to run at 1MHz = 72MHz/72
//Prescaler is div-1 => 71
timer_set_prescaler(REV_CNT_TIMER, 71);
timer_set_period(REV_CNT_TIMER, MAX_CNT);
timer_update_on_overflow(REV_CNT_TIMER);
timer_direction_up(REV_CNT_TIMER);
/*timer_ic_enable(REV_CNT_TIMER, REV_CNT_IC);
timer_ic_set_filter(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_DTF_DIV_32_N_6);
timer_ic_set_prescaler(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_PSC_OFF);
timer_ic_set_input(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_IN_TI2);*/
/* Reset counter on input pulse. Filter constant must be larger than that of the capture input
So that the counter value is first saved, then reset */
TIM_SMCR(REV_CNT_TIMER) = TIM_SMCR_SMS_RM | TIM_SMCR_TS_ETRF | TIM_SMCR_ETP | TIM_SMCR_ETF_DTS_DIV_32_N_8;
/* Save timer value on input pulse with smaller filter constant */
TIM_CCMR2(REV_CNT_TIMER) = REV_CNT_CCMR2 | TIM_CCMR2_IC3F_DTF_DIV_32_N_6;
TIM_CCER(REV_CNT_TIMER) |= REV_CNT_CCER; //1 << (1 + 4 * REV_CNT_IC);
//timer_enable_irq(REV_CNT_TIMER, TIM_DIER_CC3IE);
//timer_set_dma_on_compare_event(REV_CNT_TIMER);
timer_generate_event(REV_CNT_TIMER, TIM_EGR_UG);
timer_enable_counter(REV_CNT_TIMER);
}
void funcgen_plat_timer_setup(int channel, int period_ns) {
uint32_t timer;
switch (channel) {
case 1: timer = TIM7;
break;
case 0:
default:
timer = TIM6;
break;
}
timer_reset(timer);
// APB is maxed at 42Mhz, so APB timers run at 84Mhz
// dac says 1msps max max, so at 1msps, we want a period of what, 1 Mhz _overflows_
// so at least 2 Mhz clock..., let's say 4 Mhz timer clock for max res stuff
// want to run the clock pretty quick, let's say 50ns steps or so at the bottom end,
// at ~24Mhz or similar,
// this is _F4_ specific!
/* two ranges is probably su*/
if (period_ns > 50) {
timer_set_prescaler(timer, 3); // 84 / 21 - 1 ticks at ~48ns
timer_set_period(timer, (period_ns / 48) - 1);
}
// if (period_ns * 50 > 0x6000) {
// /* don't even try and run that fast with this slow a wave */
// timer_set_prescaler(timer, 83); // 1Mhz (84/1 - 1) ticks at 1usecs
// timer_set_period(timer, (period_ns / 1000) - 1);
// }
timer_enable_irq(timer, TIM_DIER_UIE);
timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE);
timer_enable_counter(timer);
}
/******************************************************************************
Initializes the timer, turn on the interrupt and put the interrupt time to zero
INPUT void
OUTPUT void
The timer is set to roll over at 0.5 second from an 8us clock, and the output
compare 1 is used to trigger an alarm. This is set progressively by the
CanFestival stack.
******************************************************************************/
void initTimer(void)
{
/* Set alarm back to zero */
timerAlarm = 0;
/* Enable TIM3 clock. */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
/* Enable TIM3 interrupt. */
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_reset(TIM3);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Set prescaler to give 8us clock */
timer_set_prescaler(TIM3, 576);
/* Set the period as 0.5 second */
timer_set_period(TIM3, TIMEVAL_MAX);
/* Disable physical pin outputs. */
timer_disable_oc_output(TIM3, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4);
/* Configure global mode of output channel 1, disabling the output. */
timer_disable_oc_clear(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_FROZEN);
/* Set the initial compare value for OC1. */
timer_set_oc_value(TIM3, TIM_OC1, timerAlarm);
/* Continous counting mode. */
timer_continuous_mode(TIM3);
/* ARR reload disable. */
timer_disable_preload(TIM3);
/* Counter enable. */
timer_enable_counter(TIM3);
/* Enable compare match interrupt. */
timer_enable_irq(TIM3, TIM_DIER_CC1IE);
}
/*
* Free running ms timer.
*/
static void setup_button_press_timer(void)
{
rcc_periph_reset_pulse(TIMER_BUTTON_PRESS_RST);
timer_set_prescaler(TIMER_BUTTON_PRESS, 3999); /* 4Mhz/1000hz - 1 */
timer_set_period(TIMER_BUTTON_PRESS, 0xffff);
timer_enable_counter(TIMER_BUTTON_PRESS);
}
/*
* setup 10kHz timer
*/
static void tim6_setup(void)
{
timer_reset(TIM6);
timer_set_prescaler(TIM6, 8400 - 1); // 84Mhz/10kHz - 1
timer_set_period(TIM6, 65535); // Overflow in ~6.5 seconds
timer_enable_counter(TIM6);
}
/*
* Free running ms timer.
*/
static void setup_tim7(void)
{
timer_reset(TIM7);
timer_set_prescaler(TIM7, 23999); /* 24Mhz/1000hz - 1 */
timer_set_period(TIM7, 0xffff);
timer_enable_counter(TIM7);
}
//-----------------------------------------------------------------------------
int main(void)
{
uint32_t cnt = 0;
bool fast = false;
sys_init();
timer_init();
uart_init(115200);
uart_puts("\r\nHello, world!\r\n");
HAL_GPIO_LED_out();
HAL_GPIO_LED_clr();
HAL_GPIO_BUTTON_in();
HAL_GPIO_BUTTON_pullup();
while (1)
{
if (HAL_GPIO_BUTTON_read())
cnt = 0;
else if (cnt < 5001)
cnt++;
if (5000 == cnt)
{
fast = !fast;
timer_set_period(fast ? PERIOD_FAST : PERIOD_SLOW);
uart_putc('.');
}
}
return 0;
}
void enable_test_trigger(trigger_type trig, unsigned int rpm) {
if (trig != FORD_TFI) {
return;
}
timeval_t t = time_from_rpm_diff(rpm, 45);
/* Set up TIM5 as 32bit clock */
rcc_periph_clock_enable(RCC_TIM5);
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO0);
gpio_set_af(GPIOA, GPIO_AF2, GPIO0);
timer_reset(TIM5);
timer_disable_oc_output(TIM5, TIM_OC1);
timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(TIM5, (unsigned int)t);
timer_set_prescaler(TIM5, 0);
timer_disable_preload(TIM5);
timer_continuous_mode(TIM5);
/* Setup output compare registers */
timer_ic_set_input(TIM5, TIM_IC1, TIM_IC_OUT);
timer_disable_oc_clear(TIM5, TIM_OC1);
timer_disable_oc_preload(TIM5, TIM_OC1);
timer_set_oc_slow_mode(TIM5, TIM_OC1);
timer_set_oc_mode(TIM5, TIM_OC1, TIM_OCM_TOGGLE);
timer_set_oc_value(TIM5, TIM_OC1, t);
timer_set_oc_polarity_high(TIM5, TIM_OC1);
timer_enable_oc_output(TIM5, TIM_OC1);
timer_enable_counter(TIM5);
}
static void pwm_setup(void) {
/* Configure GPIOs: OUT=PA7 */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM3_CH2 );
timer_reset(TIM3);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_disable_oc_output(TIM3, TIM_OC2);
timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
timer_disable_oc_clear(TIM3, TIM_OC2);
timer_set_oc_value(TIM3, TIM_OC2, 0);
timer_enable_oc_preload(TIM3, TIM_OC2);
timer_set_oc_polarity_high(TIM3, TIM_OC2);
timer_enable_oc_output(TIM3, TIM_OC2);
timer_set_dma_on_update_event(TIM3);
timer_enable_irq(TIM3, TIM_DIER_UDE); // in fact, enable DMA on update
timer_enable_preload(TIM3);
timer_continuous_mode(TIM3);
timer_set_period(TIM3, WSP);
timer_enable_counter(TIM3);
}
__attribute__((constructor)) void timer()
{
char byte;
tty_printf("enter a command: a(enable), d(disable), q(quit) \n");
tty_getc_irq(&byte);
while (1) {
switch(byte){
case 'a':
timer_set_period(50000);
timer_set_mode(0x3);
break;
case 'd':
//timer_reset_irq();
timer_set_mode(0x0);
break;
case 'q' :
exit();
break;
default:
tty_printf("bad command line, choose between a, q, or q! \n");
break;
}
tty_getc_irq(&byte);
}
} // end main
void BeepInit(void)
{
rcc_peripheral_enable_clock(&RCC_APB1ENR, BEEP_RCC_APB1ENR_TIMEN);
gpio_set_mode(BEEP_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, BEEP_PIN);
timer_set_mode(BEEP_TIM, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Period */
timer_set_period(BEEP_TIM, 65535);
/* Prescaler */
timer_set_prescaler(BEEP_TIM, 5);
timer_generate_event(BEEP_TIM, TIM_EGR_UG);
/* ---- */
/* Output compare 1 mode and preload */
timer_set_oc_mode(BEEP_TIM, BEEP_TIM_OC, TIM_OCM_PWM1);
timer_enable_oc_preload(BEEP_TIM, BEEP_TIM_OC);
/* Polarity and state */
timer_set_oc_polarity_low(BEEP_TIM, BEEP_TIM_OC);
timer_enable_oc_output(BEEP_TIM, BEEP_TIM_OC);
/* Capture compare value */
timer_set_oc_value(BEEP_TIM, BEEP_TIM_OC, 0x8000);
/* ---- */
/* ARR reload enable */
timer_enable_preload(BEEP_TIM);
}
/** Configure and enable RCC for peripherals (ADC1, ADC2, Timer) */
static inline void adc_init_rcc( void )
{
#if USE_AD1 || USE_AD2 || USE_AD3
/* Timer peripheral clock enable. */
rcc_periph_clock_enable(RCC_TIM_ADC);
#if defined(STM32F4)
adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2);
#endif
/* Enable ADC peripheral clocks. */
#if USE_AD1
rcc_periph_clock_enable(RCC_ADC1);
#endif
#if USE_AD2
rcc_periph_clock_enable(RCC_ADC2);
#endif
#if USE_AD3
rcc_periph_clock_enable(RCC_ADC3);
#endif
/* Time Base configuration */
timer_reset(TIM_ADC);
timer_set_mode(TIM_ADC, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* timer counts with ADC_TIMER_FREQUENCY */
uint32_t timer_clk = timer_get_frequency(TIM_ADC);
timer_set_prescaler(TIM_ADC, (timer_clk / ADC_TIMER_FREQUENCY) - 1);
timer_set_period(TIM_ADC, ADC_TIMER_PERIOD);
/* Generate TRGO on every update (when counter reaches period reload value) */
timer_set_master_mode(TIM_ADC, TIM_CR2_MMS_UPDATE);
timer_enable_counter(TIM_ADC);
#endif // USE_AD1 || USE_AD2 || USE_AD3
}
int output_init(void) {
setup_ctrl_gpio(M0INa);
setup_ctrl_gpio(M0INb);
setup_ctrl_gpio(M0ENa);
setup_ctrl_gpio(M0ENb);
setup_ctrl_gpio(M1INa);
setup_ctrl_gpio(M1INb);
setup_ctrl_gpio(M1ENa);
setup_ctrl_gpio(M1ENb);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
setup_pwm_pin(M0PWM);
setup_pwm_pin(M1PWM);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(TIM2, 2000);
timer_set_prescaler(TIM2, 1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_mode(TIM2, TIM_OC2, TIM_OCM_PWM1);
timer_enable_oc_preload(TIM2, TIM_OC1);
timer_enable_oc_preload(TIM2, TIM_OC2);
timer_set_oc_polarity_high(TIM2, TIM_OC1);
timer_set_oc_polarity_high(TIM2, TIM_OC2);
timer_enable_oc_output(TIM2, TIM_OC1);
timer_enable_oc_output(TIM2, TIM_OC2);
output_speed(0, 0);
output_speed(1, 0);
timer_enable_preload(TIM2);
timer_enable_counter(TIM2);
return 0;
}
void torture_setup ( void ) {
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
timer_reset(TIM3);
// 24Mhz / 10khz -1.
timer_set_prescaler(TIM3, 20000); // 24Mhz/10000hz - 1
// 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts
timer_set_period(TIM3, 1);
/* Set timer start value. */
TIM_CNT(TIM3) = 1;
/* Set timer prescaler. */
TIM_PSC(TIM3) = 100; // 100 .. so about 840000 ticks per second
/* End timer value. If this is reached an interrupt is generated. */
TIM_ARR(TIM3) = 60; // 840000/14 -> 60,000/sec
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_enable_update_event(TIM3); // default at reset!
timer_enable_irq(TIM3, TIM_DIER_UIE);
timer_enable_counter(TIM3);
}
void PulseWidth::begin(uint16 period, bool microsecond_precision)
{
if(timer_peripheral == TIM2)
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
else if(timer_peripheral == TIM3)
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
else
return;
timer_reset(timer_peripheral);
/* Set the timers global mode to:
* - use no divider
* - alignment edge
* - count direction up
*/
timer_set_mode(timer_peripheral,
TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE,
TIM_CR1_DIR_UP);
if(microsecond_precision)
timer_set_prescaler(timer_peripheral, 64);
else
timer_set_prescaler(timer_peripheral, 64'000);
timer_set_repetition_counter(timer_peripheral, 0);
timer_enable_preload(timer_peripheral);
timer_continuous_mode(timer_peripheral);
timer_set_period(timer_peripheral, period);
}
/**
* Initialize the DSM timer
*/
static void timer_dsm_init(void) {
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
// Enable the timer NVIC
nvic_enable_irq(TIMER_DSM_NVIC);
nvic_set_priority(TIMER_DSM_NVIC, 1);
// Setup the timer
timer_disable_counter(TIMER_DSM);
timer_reset(TIMER_DSM);
timer_set_mode(TIMER_DSM, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_disable_preload(TIMER_DSM);
timer_continuous_mode(TIMER_DSM);
// Disable interrupts on Compare 1
timer_disable_irq(TIMER_DSM, TIM_DIER_CC1IE);
// Clear the Output Compare of OC1
timer_disable_oc_clear(TIMER_DSM, TIM_OC1);
timer_disable_oc_preload(TIMER_DSM, TIM_OC1);
timer_set_oc_slow_mode(TIMER_DSM, TIM_OC1);
timer_set_oc_mode(TIMER_DSM, TIM_OC1, TIM_OCM_FROZEN);
// Set timer updates each 10 microseconds
#if DEBUG && !DSM_RECEIVER && !DSM_MITM
timer_set_prescaler(TIMER_DSM, 720000 - 1);
#else
timer_set_prescaler(TIMER_DSM, 720 - 1);
#endif
timer_set_period(TIMER_DSM, 65535);
// Start the timer
timer_enable_counter(TIMER_DSM);
}
void set_dual_pwm_timer_s_period(uint32_t period)
{
#if DUAL_PWM_USE_TIM5
timer_set_period(TIM5, period);
#endif
}
/* Configure and enable RCC for peripherals (ADC1, ADC2, Timer) */
static inline void adc_init_rcc( void )
{
#if defined (USE_AD1) || defined (USE_AD2)
uint32_t timer;
volatile uint32_t *rcc_apbenr;
uint32_t rcc_apb;
#if defined(USE_AD_TIM4)
timer = TIM4;
rcc_apbenr = &RCC_APB1ENR;
rcc_apb = RCC_APB1ENR_TIM4EN;
#elif defined(USE_AD_TIM1)
timer = TIM1;
rcc_apbenr = &RCC_APB2ENR;
rcc_apb = RCC_APB2ENR_TIM1EN;
#else
timer = TIM2;
rcc_apbenr = &RCC_APB1ENR;
rcc_apb = RCC_APB1ENR_TIM2EN;
#endif
/*
* Historic Note:
* Previously in libstm32 we were setting the ADC clock here.
* It was being set to PCLK2 DIV2 resulting in 36MHz clock on the ADC. I am
* pretty sure that this is wrong as based on the datasheet the ADC clock
* must not exceed 14MHz! Now the clock is being set by the clock init
* routine in libopencm3 so we don't have to set up this clock ourselves any
* more. This comment is here just as a reminder and may be removed in the
* future when we know that everything is working properly.
* (by Esden the historian :D)
*/
/* Timer peripheral clock enable. */
rcc_peripheral_enable_clock(rcc_apbenr, rcc_apb);
/* GPIO peripheral clock enable. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN);
/* Enable ADC peripheral clocks. */
#ifdef USE_AD1
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
#endif
#ifdef USE_AD2
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC2EN);
#endif
/* Time Base configuration */
timer_reset(timer);
timer_set_mode(timer, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(timer, 0xFF);
timer_set_prescaler(timer, 0x8);
timer_set_clock_division(timer, 0x0);
/* Generate TRGO on every update. */
timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE);
timer_enable_counter(timer);
#endif // defined (USE_AD1) || defined (USE_AD2)
}
static void tim_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value. */
timer_set_prescaler(TIM2, 36000);
/* Enable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
}
static void platform_init_pwm() {
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO6);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO7);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9);
gpio_set_af(GPIOC, GPIO_AF2, GPIO6);
gpio_set_af(GPIOC, GPIO_AF2, GPIO7);
gpio_set_af(GPIOC, GPIO_AF2, GPIO8);
gpio_set_af(GPIOC, GPIO_AF2, GPIO9);
timer_reset(TIM3);
timer_disable_oc_output(TIM3, TIM_OC1);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* 72ish Hz, close to 60 */
timer_set_period(TIM3, 65535);
timer_set_prescaler(TIM3, 16);
timer_disable_preload(TIM3);
timer_continuous_mode(TIM3);
/* Setup output compare registers */
timer_ic_set_input(TIM3, TIM_IC1, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC1, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC1);
timer_enable_oc_output(TIM3, TIM_OC1);
timer_ic_set_input(TIM3, TIM_IC2, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC2);
timer_disable_oc_preload(TIM3, TIM_OC2);
timer_set_oc_slow_mode(TIM3, TIM_OC2);
timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC2, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC2);
timer_enable_oc_output(TIM3, TIM_OC2);
timer_ic_set_input(TIM3, TIM_IC3, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC3);
timer_disable_oc_preload(TIM3, TIM_OC3);
timer_set_oc_slow_mode(TIM3, TIM_OC3);
timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC3, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC3);
timer_enable_oc_output(TIM3, TIM_OC3);
timer_ic_set_input(TIM3, TIM_IC4, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC4);
timer_disable_oc_preload(TIM3, TIM_OC4);
timer_set_oc_slow_mode(TIM3, TIM_OC4);
timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC4, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC4);
timer_enable_oc_output(TIM3, TIM_OC4);
timer_enable_counter(TIM3);
}
/* Function to init a timer */
void timer_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value.
* Running the clock at 5kHz.
*/
/*
* On STM32F4 the timers are not running directly from pure APB1 or
* APB2 clock busses. The APB1 and APB2 clocks used for timers might
* be the double of the APB1 and APB2 clocks. This depends on the
* setting in DCKCFGR register. By default the behaviour is the
* following: If the Prescaler APBx is greater than 1 the derived timer
* APBx clocks will be double of the original APBx frequencies. Only if
* the APBx prescaler is set to 1 the derived timer APBx will equal the
* original APBx frequencies.
*
* In our case here the APB1 is devided by 4 system frequency and APB2
* divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will
* be 2 x APB2. So when we try to calculate the prescaler value we have
* to use rcc_apb1_freqency * 2!!!
*
* For additional information see reference manual for the stm32f4
* familiy of chips. Page 204 and 213
*/
timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000));
/* Disable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 100);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable update interrupt. */
timer_enable_irq(TIM2, TIM_DIER_UIE);
}
void ppm_arch_init ( void ) {
/* timer clock enable */
rcc_peripheral_enable_clock(PPM_RCC, PPM_PERIPHERAL);
/* GPIOA clock enable */
rcc_peripheral_enable_clock(&RCC_APB2ENR, PPM_GPIO_PERIPHERAL);
/* timer gpio configuration */
gpio_set_mode(PPM_GPIO_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, PPM_GPIO_PIN);
/* Time Base configuration */
timer_reset(PPM_TIMER);
timer_set_mode(PPM_TIMER, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(PPM_TIMER, 0xFFFF);
/* run ppm timer at cpu freq / 9 = 8MHz */
timer_set_prescaler(PPM_TIMER, 8);
/* TIM configuration: Input Capture mode ---------------------
The Rising edge is used as active edge,
Intput pin is either PA1 or PA10
------------------------------------------------------------ */
#if defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_POSITIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_RISING);
#elif defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_NEGATIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_FALLING);
#else
#error "Unknown PM_PULSE_TYPE"
#endif
timer_ic_set_input(PPM_TIMER, PPM_CHANNEL, PPM_TIMER_INPUT);
timer_ic_set_prescaler(PPM_TIMER, PPM_CHANNEL, TIM_IC_PSC_OFF);
timer_ic_set_filter(PPM_TIMER, PPM_CHANNEL, TIM_IC_OFF);
/* Enable timer Interrupt(s). */
nvic_set_priority(PPM_IRQ, 2);
nvic_enable_irq(PPM_IRQ);
#ifdef PPM_IRQ2
nvic_set_priority(PPM_IRQ2, 2);
nvic_enable_irq(PPM_IRQ2);
#endif
/* Enable the CC2 and Update interrupt requests. */
timer_enable_irq(PPM_TIMER, PPM_IRQ_FLAGS);
/* Enable capture channel. */
timer_ic_enable(PPM_TIMER, PPM_CHANNEL);
/* TIM enable counter */
timer_enable_counter(PPM_TIMER);
ppm_last_pulse_time = 0;
ppm_cur_pulse = RADIO_CONTROL_NB_CHANNEL;
timer_rollover_cnt = 0;
}
static inline void pwm_input_set_timer(uint32_t tim, uint32_t ticks_per_usec)
{
timer_reset(tim);
timer_set_mode(tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(tim, 0xFFFF);
uint32_t timer_clk = timer_get_frequency(tim);
timer_set_prescaler(tim, (timer_clk / (ticks_per_usec * ONE_MHZ_CLK)) - 1);
timer_enable_counter(tim);
}
void timer_setup() {
RCC_APB1ENR |= RCC_APB1ENR_TIM2EN;
timer_set_prescaler(TIM2, 1);
timer_set_period(TIM2, rcc_ppre1_frequency / 100);
timer_enable_irq(TIM2, TIM_DIER_UIE);
TIM2_CNT = 0;
timer_enable_counter(TIM2);
nvic_enable_irq(NVIC_TIM2_IRQ);
}
void ppm_arch_init ( void ) {
/* timer clock enable */
rcc_peripheral_enable_clock(PPM_RCC, PPM_PERIPHERAL);
/* GPIO clock enable */
gpio_enable_clock(PPM_GPIO_PORT);
/* timer gpio configuration */
gpio_setup_pin_af(PPM_GPIO_PORT, PPM_GPIO_PIN, PPM_GPIO_AF, FALSE);
/* Time Base configuration */
timer_reset(PPM_TIMER);
timer_set_mode(PPM_TIMER, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(PPM_TIMER, 0xFFFF);
timer_set_prescaler(PPM_TIMER, (PPM_TIMER_CLK / (RC_PPM_TICKS_PER_USEC*ONE_MHZ_CLK)) - 1);
/* TIM configuration: Input Capture mode ---------------------
The Rising edge is used as active edge
------------------------------------------------------------ */
#if defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_POSITIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_RISING);
#elif defined PPM_PULSE_TYPE && PPM_PULSE_TYPE == PPM_PULSE_TYPE_NEGATIVE
timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_FALLING);
#else
#error "Unknown PPM_PULSE_TYPE"
#endif
timer_ic_set_input(PPM_TIMER, PPM_CHANNEL, PPM_TIMER_INPUT);
timer_ic_set_prescaler(PPM_TIMER, PPM_CHANNEL, TIM_IC_PSC_OFF);
timer_ic_set_filter(PPM_TIMER, PPM_CHANNEL, TIM_IC_OFF);
/* Enable timer Interrupt(s). */
nvic_set_priority(PPM_IRQ, 2);
nvic_enable_irq(PPM_IRQ);
#ifdef PPM_IRQ2
nvic_set_priority(PPM_IRQ2, 2);
nvic_enable_irq(PPM_IRQ2);
#endif
/* Enable the Capture/Compare and Update interrupt requests. */
timer_enable_irq(PPM_TIMER, (PPM_CC_IE | TIM_DIER_UIE));
/* Enable capture channel. */
timer_ic_enable(PPM_TIMER, PPM_CHANNEL);
/* TIM enable counter */
timer_enable_counter(PPM_TIMER);
ppm_last_pulse_time = 0;
ppm_cur_pulse = RADIO_CONTROL_NB_CHANNEL;
timer_rollover_cnt = 0;
}
/**
* We set this timer to count uSecs.
* The interrupt is only to indicate that it timed out and to shut itself off.
*/
void setup_tim7(void)
{
timer_clear_flag(TIM7, TIM_SR_UIF);
TIM7_CNT = 1;
timer_set_prescaler(TIM7, 23); // 24Mhz/1Mhz - 1
timer_set_period(TIM7, RHT_INTER_BIT_TIMEOUT_USEC);
timer_enable_irq(TIM7, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM7_IRQ);
timer_enable_counter(TIM7);
}
/** Set Timer configuration
*/
static inline void set_servo_timer(uint32_t timer, uint32_t period, uint8_t channels_mask) {
timer_reset(timer);
/* Timer global mode:
* - No divider.
* - Alignement edge.
* - Direction up.
*/
timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(timer, (PCLK / ONE_MHZ_CLK) - 1); // 1uS
timer_disable_preload(timer);
timer_continuous_mode(timer);
timer_set_period(timer, (ONE_MHZ_CLK / period) - 1);
/* Disable outputs and configure channel if needed. */
if (bit_is_set(channels_mask, 0)) {
actuators_pwm_arch_channel_init(timer, TIM_OC1);
}
if (bit_is_set(channels_mask, 1)) {
actuators_pwm_arch_channel_init(timer, TIM_OC2);
}
if (bit_is_set(channels_mask, 2)) {
actuators_pwm_arch_channel_init(timer, TIM_OC3);
}
if (bit_is_set(channels_mask, 3)) {
actuators_pwm_arch_channel_init(timer, TIM_OC4);
}
/*
* Set initial output compare values.
* Note: Maybe we should preload the compare registers with some sensible
* values before we enable the timer?
*/
//timer_set_oc_value(timer, TIM_OC1, 1000);
//timer_set_oc_value(timer, TIM_OC2, 1000);
//timer_set_oc_value(timer, TIM_OC3, 1000);
//timer_set_oc_value(timer, TIM_OC4, 1000);
/* -- Enable timer -- */
/*
* ARR reload enable.
* Note: In our case it does not matter much if we do preload or not. As it
* is unlikely we will want to change the frequency of the timer during
* runtime anyways.
*/
timer_enable_preload(timer);
/* Counter enable. */
timer_enable_counter(timer);
}