static void tiva_adc_read(void *arg)
{
struct tiva_adc_s *priv;
struct tiva_adc_sse_s *sse = (struct tiva_adc_sse_s *)arg;
struct adc_dev_s *dev = 0;
int irq = tiva_adc_getirq(sse->adc, sse->num);
uint8_t i = 0;
uint8_t fifo_count = 0;
int32_t buf[8];
/* Get exclusive access to the driver data structure */
tiva_adc_lock(g_adcs[sse->adc], sse->num);
/* Get sampled data */
fifo_count = tiva_adc_sse_data(sse->adc, sse->num, buf);
/* Determine which adc_dev_s we need */
dev = g_devs[sse->adc];
if (dev == NULL)
{
/* This is a serious error: indicates invalid pointer indirection
* and should cause a full system stop.
*/
aerr("ERROR: Invalid ADC device number given %d\n", sse->adc);
DEBUGPANIC();
return;
}
priv = (struct tiva_adc_s *)dev->ad_priv;
/* Verify that the upper-half driver has bound its callback functions */
if (priv->cb != NULL)
{
DEBUGASSERT(priv->cb->au_receive != NULL);
for (i = 0; i < fifo_count; ++i)
{
/* Perform the data received callback */
priv->cb->au_receive(dev,
tiva_adc_get_ain(sse->adc, sse->num, i),
buf[i]);
ainfo("AIN%d = 0x%04x\n",
tiva_adc_get_ain(sse->adc, sse->num, i), buf[i]);
}
}
/* Exit, re-enabling ADC interrupts */
up_enable_irq(irq);
/* Release our lock on the ADC structure */
tiva_adc_unlock(g_adcs[sse->adc], sse->num);
}
static void tiva_adc_read(void *arg)
{
struct tiva_adc_sse_s *sse = (struct tiva_adc_sse_s *)arg;
struct adc_dev_s *dev = 0;
int irq = tiva_adc_getirq(sse->adc, sse->num);
uint8_t i = 0;
uint8_t fifo_count = 0;
int32_t buf[8];
/* Get exclusive access to the driver data structure */
tiva_adc_lock(g_adcs[sse->adc], sse->num);
/* Get sampled data */
fifo_count = tiva_adc_sse_data(sse->adc, sse->num, buf);
/* Determine which adc_dev_s we need */
dev = g_devs[sse->adc];
if (dev == NULL)
{
/* This is a serious error: indicates invalid pointer indirection
* and should cause a full system stop.
*/
alldbg("PANIC!!! Invalid ADC device number given %d\n", sse->adc);
PANIC();
return;
}
for (i = 0; i < fifo_count; ++i)
{
(void)adc_receive(dev,
tiva_adc_get_ain(sse->adc, sse->num, i),
buf[i]);
avdbg("AIN%d=0x%04x\n",
tiva_adc_get_ain(sse->adc, sse->num, i), buf[i]);
}
/* Exit, re-enabling ADC interrupts */
up_enable_irq(irq);
/* Release our lock on the ADC structure */
tiva_adc_unlock(g_adcs[sse->adc], sse->num);
}
static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
{
int ret = OK;
ainfo("cmd=%d arg=%ld\n", cmd, arg);
switch (cmd)
{
/* Software trigger */
case ANIOC_TRIGGER:
{
struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
uint8_t i = 0;
uint8_t fifo_count = 0;
uint8_t sse = (uint8_t) arg;
int32_t buf[8];
/* Get exclusive access to the driver data structure */
tiva_adc_lock(priv, sse);
/* Start conversion and wait for end of conversion */
tiva_adc_proc_trig(priv->devno, (uint8_t)SSE_PROC_TRIG(sse));
while (!tiva_adc_sse_int_status(priv->devno, sse))
{
nxsig_usleep(100);
}
tiva_adc_sse_clear_int(priv->devno, sse);
/* Pass sampled data to upper ADC driver */
fifo_count = tiva_adc_sse_data(priv->devno, sse, buf);
/* Verify that the upper-half driver has bound its callback functions */
if (priv->cb != NULL)
{
DEBUGASSERT(priv->cb->au_receive != NULL);
for (i = 0; i < fifo_count; ++i)
{
/* Perform the data received callback */
priv->cb->au_receive(dev,
tiva_adc_get_ain(priv->devno, sse, i),
buf[i]);
}
}
/* Release our lock on the ADC structure */
tiva_adc_unlock(priv, sse);
}
break;
/* PWM triggering */
#warning Missing Logic
/* TODO: Needs to be tested */
#ifdef CONFIG_EXPERIMENTAL
case TIVA_ADC_PWM_TRIG_IOCTL:
{
uint8_t sse = (uint8_t)(arg & 0x2);
uint8_t regval = tiva_adc_get_trigger(adc, sse);
/* Verify input SSE trigger is a PWM trigger */
if ((regval & TIVA_ADC_TRIG_PWM0) ||
(regval & TIVA_ADC_TRIG_PWM1) ||
(regval & TIVA_ADC_TRIG_PWM2) ||
(regval & TIVA_ADC_TRIG_PWM3))
{
tiva_adc_sse_pwm_trig(adc, sse, (uint32_t)(arg&0xFFFFFFFC));
}
}
break;
#endif
#warning Missing Logic
/* Unsupported or invalid command */
default:
ret = -ENOTTY;
break;
}
return ret;
}
