int starwars_m6532_r(int offset)
{
static int temp;
switch (offset)
{
case 0: /* 0x80 - Read Port A */
/* Note: bit 4 is always set to avoid sound self test */
return port_A|0x10|(!tms5220_ready_r()<<2);
case 1: /* 0x81 - Read Port A DDR */
return port_A_ddr;
case 2: /* 0x82 - Read Port B */
return port_B; /* speech data read? */
case 3: /* 0x83 - Read Port B DDR */
return port_B_ddr;
case 5: /* 0x85 - Read Interrupt Flag Register */
temp = irq_flag;
irq_flag = 0; /* Clear int flags */
return temp;
default:
return 0;
}
return 0; /* will never execute this */
}
static READ8_HANDLER( exidy_shriot_r )
{
/* I/O is done if A2 == 0 */
if ((offset & 0x04) == 0)
{
switch (offset & 0x03)
{
case 0x00: /* port A */
return riot_porta_data;
case 0x01: /* port A DDR */
return riot_porta_ddr;
case 0x02: /* port B */
if (has_tms5220)
{
riot_portb_data &= ~0x0c;
if (!tms5220_ready_r()) riot_portb_data |= 0x04;
if (!tms5220_int_r()) riot_portb_data |= 0x08;
}
return riot_portb_data;
case 0x03: /* port B DDR */
return riot_portb_ddr;
}
}
/* interrupt flags are read if A2 == 1 and A0 == 1 */
else if (offset & 0x01)
{
int temp = riot_irq_flag;
riot_irq_flag = 0;
riot_irq_state = 0;
update_irq_state(0);
return temp;
}
/* timer count is read if A2 == 1 and A0 == 0 */
else
{
/* set the enable from the offset */
riot_timer_irq_enable = offset & 0x08;
/* compute the timer based on the current state */
switch (riot_state)
{
case RIOT_IDLE:
return 0x00;
case RIOT_COUNT:
return attotime_to_double(timer_timeleft(riot_timer)) * SH6532_CLOCK / riot_clock_divisor;
case RIOT_POST_COUNT:
return attotime_to_double(timer_timeleft(riot_timer)) * SH6532_CLOCK;
}
}
logerror("Undeclared RIOT read: %x PC:%x\n",offset,activecpu_get_pc());
return 0xff;
}
static void speech_kludge_callback(int dummy)
{
if (! tms5220_ready_r())
{
/* Weirdly enough, we are always seeing some problems even though
everything is working fine. */
/*double time_to_ready = tms5220_time_to_ready();
logerror("ti99/4a speech says aaargh!\n");
logerror("(time to ready: %f -> %d)\n", time_to_ready, (int) ceil(3000000*time_to_ready));*/
}
}
int atarisys2_6502_switch_r (int offset)
{
int result = input_port_0_r (offset);
if (atarigen_cpu_to_sound_ready) result ^= 0x01;
if (atarigen_sound_to_cpu_ready) result ^= 0x02;
if (tms5220_ready_r ()) result ^= 0x04;
if (!(input_port_2_r (offset) & 0x80)) result ^= 0x10;
return result;
}
/*
TMS5200 speech chip write
*/
static WRITE8_HANDLER ( geneve_speech_w )
{
activecpu_adjust_icount(-32*4); /* this is just an approx. minimum, it can be much more */
#if 1
/* the stupid design of the tms5220 core means that ready is cleared when
there are 15 bytes in FIFO. It should be 16. Of course, if it were the
case, we would need to store the value on the bus, which would be more
complex. */
if (! tms5220_ready_r())
{
double time_to_ready = tms5220_time_to_ready();
int cycles_to_ready = ceil(TIME_TO_CYCLES(0, time_to_ready));
logerror("time to ready: %f -> %d\n", time_to_ready, (int) cycles_to_ready);
activecpu_adjust_icount(-cycles_to_ready);
timer_set(TIME_NOW, 0, /*speech_kludge_callback*/NULL);
}
#endif
tms5220_data_w(offset, data);
}
static READ_HANDLER(nuova_pia_ca2_r) {
return !tms5220_ready_r();
}
static UINT8 snd_ef3(void) {
sndlocals.ef[1] = !tms5220_ready_r();
return sndlocals.ef[1] | (sndlocals.ef[2] << 1) | (sndlocals.ef[3] << 2) | (sndlocals.ef[4] << 3);
}
