static int clk_pllv3_prepare(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long timeout; u32 val; val = readl_relaxed(pll->base); val &= ~BM_PLL_BYPASS; if (pll->powerup_set) val |= BM_PLL_POWER; else val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); timeout = jiffies + msecs_to_jiffies(10); /* Wait for PLL to lock */ do { if (readl_relaxed(pll->base) & BM_PLL_LOCK) break; if (time_after(jiffies, timeout)) break; } while (1); if (readl_relaxed(pll->base) & BM_PLL_LOCK) return 0; else return -ETIMEDOUT; }
static int clk_pllv3_power_up_down(struct clk_hw *hw, bool enable) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val, ret = 0; if (enable) { val = readl_relaxed(pll->base); val &= ~BM_PLL_BYPASS; if (pll->powerup_set) val |= BM_PLL_POWER; else val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); ret = clk_pllv3_wait_for_lock(pll, 10); } else { val = readl_relaxed(pll->base); val |= BM_PLL_BYPASS; if (pll->powerup_set) val &= ~BM_PLL_POWER; else val |= BM_PLL_POWER; writel_relaxed(val, pll->base); } pll->powered = enable; return ret; }
static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long min_rate = parent_rate * 27; unsigned long max_rate = parent_rate * 54; u32 val, div; u32 mfn, mfd = 1000000; s64 temp64; if (rate < min_rate || rate > max_rate) return -EINVAL; div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; do_div(temp64, parent_rate); mfn = temp64; val = readl_relaxed(pll->base); val &= ~pll->div_mask; val |= div; writel_relaxed(val, pll->base); writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); return 0; }
static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; int ret; val = readl_relaxed(pll->base); if (enable) { if (pll->powerup_set) val |= BM_PLL_POWER; else val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); ret = clk_pllv3_wait_lock(pll); if (ret) return ret; } else { if (pll->powerup_set) val &= ~BM_PLL_POWER; else val |= BM_PLL_POWER; writel_relaxed(val, pll->base); } return 0; }
static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 div = readl_relaxed(pll->base) & pll->div_mask; return parent_rate * div / 2; }
static void clk_pllv3_disable(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; val = readl_relaxed(pll->base); val &= ~BM_PLL_ENABLE; writel_relaxed(val, pll->base); }
static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long min_rate = parent_rate * 27; unsigned long max_rate = parent_rate * 54; u32 val, div; u32 mfn, mfd = 1000000; s64 temp64; if (rate != BYPASS_RATE && (rate < min_rate || rate > max_rate)) return -EINVAL; pll->rate_req = rate; val = readl_relaxed(pll->base); if (rate == BYPASS_RATE) { /* * Set the PLL in bypass mode if rate requested is * BYPASS_RATE. */ /* Bypass the PLL */ val |= BM_PLL_BYPASS; /* Power down the PLL. */ if (pll->powerup_set) val &= ~BM_PLL_POWER; else val |= BM_PLL_POWER; writel_relaxed(val, pll->base); return 0; } /* Else clear the bypass bit. */ val &= ~BM_PLL_BYPASS; writel_relaxed(val, pll->base); if (pll->powered) { pr_err("%s: cannot configure divider when PLL is powered on\n", __func__); return -EBUSY; } div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; do_div(temp64, parent_rate); mfn = temp64; val = readl_relaxed(pll->base); val &= ~pll->div_mask; val |= div; writel_relaxed(val, pll->base); writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); return clk_pllv3_wait_for_lock(pll, 10); }
static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); u32 div = readl_relaxed(pll->base) & pll->div_mask; return (parent_rate * div) + ((parent_rate / mfd) * mfn); }
static int clk_pllv3_enable(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; val = readl_relaxed(pll->base); val |= BM_PLL_ENABLE; writel_relaxed(val, pll->base); return 0; }
static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 div = readl_relaxed(pll->base) & pll->div_mask; u32 bypass = readl_relaxed(pll->base) & BYPASS_MASK; if (pll->rate_req == BYPASS_RATE && bypass) return BYPASS_RATE; return parent_rate * div / 2; }
static void clk_pllv3_unprepare(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; val = readl_relaxed(pll->base); val |= BM_PLL_BYPASS; if (pll->powerup_set) val &= ~BM_PLL_POWER; else val |= BM_PLL_POWER; writel_relaxed(val, pll->base); }
static void clk_pllv3_disable(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; val = readl_relaxed(pll->base); if (!pll->always_on) val &= ~BM_PLL_ENABLE; writel_relaxed(val, pll->base); if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, false); }
static int clk_pllv3_enable(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, true); val = readl_relaxed(pll->base); val |= BM_PLL_ENABLE; writel_relaxed(val, pll->base); return 0; }
static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); u32 div = readl_relaxed(pll->base) & pll->div_mask; u32 bypass = readl_relaxed(pll->base) & BYPASS_MASK; if (pll->rate_req == BYPASS_RATE && bypass) return BYPASS_RATE; return (parent_rate * div) + ((parent_rate / mfd) * mfn); }
static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 div = readl_relaxed(pll->base) & pll->div_mask; u32 bypass = readl_relaxed(pll->base) & BYPASS_MASK; u32 rate; if (bypass) rate = BYPASS_RATE; else rate = (div == 1) ? parent_rate * 22 : parent_rate * 20; return rate; }
static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long min_rate = parent_rate * 54 / 2; unsigned long max_rate = parent_rate * 108 / 2; u32 val, div; if (rate < min_rate || rate > max_rate) return -EINVAL; div = rate * 2 / parent_rate; val = readl_relaxed(pll->base); val &= ~pll->div_mask; val |= div; writel_relaxed(val, pll->base); return 0; }
static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long min_rate = parent_rate * 54 / 2; unsigned long max_rate = parent_rate * 108 / 2; u32 val, div; if (rate != BYPASS_RATE && (rate < min_rate || rate > max_rate)) return -EINVAL; pll->rate_req = rate; val = readl_relaxed(pll->base); if (rate == BYPASS_RATE) { /* * Set the PLL in bypass mode if rate requested is * BYPASS_RATE. */ val |= BM_PLL_BYPASS; /* Power down the PLL. */ if (pll->powerup_set) val &= ~BM_PLL_POWER; else val |= BM_PLL_POWER; writel_relaxed(val, pll->base); return 0; } if (pll->powered) { pr_err("%s: cannot configure divider when PLL is powered on\n", __func__); return -EBUSY; } div = rate * 2 / parent_rate; val = readl_relaxed(pll->base); val &= ~pll->div_mask; val |= div; writel_relaxed(val, pll->base); return clk_pllv3_wait_for_lock(pll, 10); }
static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val, div; pll->rate_req = rate; val = readl_relaxed(pll->base); /* If the PLL is bypassed, its rate is 24MHz. */ if (rate == BYPASS_RATE) { /* Set the bypass bit. */ val |= BM_PLL_BYPASS; /* Power down the PLL. */ if (pll->powerup_set) val &= ~BM_PLL_POWER; else val |= BM_PLL_POWER; writel_relaxed(val, pll->base); return 0; } if (rate == parent_rate * 22) div = 1; else if (rate == parent_rate * 20) div = 0; else return -EINVAL; if (pll->powered) { pr_err("%s: cannot configure divider when PLL is powered on\n", __func__); return -EBUSY; } val = readl_relaxed(pll->base); val &= ~pll->div_mask; val |= div; writel_relaxed(val, pll->base); return clk_pllv3_wait_for_lock(pll, 10); }
static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val, div; if (rate == parent_rate * 22) div = 1; else if (rate == parent_rate * 20) div = 0; else return -EINVAL; val = readl_relaxed(pll->base); val &= ~pll->div_mask; val |= div; writel_relaxed(val, pll->base); return 0; }
static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; if (enable) { if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, true); val = readl_relaxed(pll->base); val |= BM_PLL_ENABLE; writel_relaxed(val, pll->base); } else { val = readl_relaxed(pll->base); if (!pll->always_on) val &= ~BM_PLL_ENABLE; writel_relaxed(val, pll->base); if (pll->rate_req != BYPASS_RATE) clk_pllv3_power_up_down(hw, false); } return 0; }
static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pllv3 *pll = to_clk_pllv3(hw); unsigned long min_rate = parent_rate * 27; unsigned long max_rate = parent_rate * 54; u32 val, newval, div; u32 mfn, mfd = 1000000; s64 temp64; int ret; if (rate != BYPASS_RATE && (rate < min_rate || rate > max_rate)) return -EINVAL; pll->rate_req = rate; val = readl_relaxed(pll->base); if (rate == BYPASS_RATE) { /* * Set the PLL in bypass mode if rate requested is * BYPASS_RATE. */ /* Bypass the PLL */ val |= BM_PLL_BYPASS; /* Power down the PLL. */ if (pll->powerup_set) val &= ~BM_PLL_POWER; else val |= BM_PLL_POWER; writel_relaxed(val, pll->base); return 0; } /* Else clear the bypass bit. */ val &= ~BM_PLL_BYPASS; writel_relaxed(val, pll->base); div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; do_div(temp64, parent_rate); mfn = temp64; val = readl_relaxed(pll->base); /* set the PLL into bypass mode */ newval = val | BM_PLL_BYPASS; writel_relaxed(newval, pll->base); /* configure the new frequency */ newval &= ~pll->div_mask; newval |= div; writel_relaxed(newval, pll->base); writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); writel(mfd, pll->base + PLL_DENOM_OFFSET); ret = clk_pllv3_wait_lock(pll); if (ret == 0 && val & BM_PLL_POWER) { /* only if it locked can we switch back to the PLL */ newval &= ~BM_PLL_BYPASS; newval |= val & BM_PLL_BYPASS; writel(newval, pll->base); } return ret; }