static int clk_rcg2_is_enabled(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cmd; int ret; ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); if (ret) return ret; return (cmd & CMD_ROOT_OFF) == 0; }
static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); int ret; ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, CFG_SRC_SEL_MASK, rcg->parent_map[index] << CFG_SRC_SEL_SHIFT); if (ret) return ret; return update_config(rcg); }
static unsigned long clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); if (rcg->mnd_width) { mask = BIT(rcg->mnd_width) - 1; regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m); m &= mask; regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n); n = ~n; n &= mask; n += m; mode = cfg & CFG_MODE_MASK; mode >>= CFG_MODE_SHIFT; }
static u8 clk_rcg2_get_parent(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); int num_parents = __clk_get_num_parents(hw->clk); u32 cfg; int i, ret; ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); if (ret) return ret; cfg &= CFG_SRC_SEL_MASK; cfg >>= CFG_SRC_SEL_SHIFT; for (i = 0; i < num_parents; i++) if (cfg == rcg->parent_map[i]) return i; return -EINVAL; }
static u8 clk_rcg2_get_parent(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); int num_parents = clk_hw_get_num_parents(hw); u32 cfg; int i, ret; ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); if (ret) goto err; cfg &= CFG_SRC_SEL_MASK; cfg >>= CFG_SRC_SEL_SHIFT; for (i = 0; i < num_parents; i++) if (cfg == rcg->parent_map[i].cfg) return i; err: pr_debug("%s: Clock %s has invalid parent, using default.\n", __func__, clk_hw_get_name(hw)); return 0; }