static void ipipeif_print_status(struct iss_ipipeif_device *ipipeif)
{
struct iss_device *iss = to_iss_device(ipipeif);
dev_dbg(iss->dev, "-------------IPIPEIF Register dump-------------\n");
IPIPEIF_PRINT_REGISTER(iss, CFG1);
IPIPEIF_PRINT_REGISTER(iss, CFG2);
ISIF_PRINT_REGISTER(iss, SYNCEN);
ISIF_PRINT_REGISTER(iss, CADU);
ISIF_PRINT_REGISTER(iss, CADL);
ISIF_PRINT_REGISTER(iss, MODESET);
ISIF_PRINT_REGISTER(iss, CCOLP);
ISIF_PRINT_REGISTER(iss, SPH);
ISIF_PRINT_REGISTER(iss, LNH);
ISIF_PRINT_REGISTER(iss, LNV);
ISIF_PRINT_REGISTER(iss, VDINT(0));
ISIF_PRINT_REGISTER(iss, HSIZE);
ISP5_PRINT_REGISTER(iss, SYSCONFIG);
ISP5_PRINT_REGISTER(iss, CTRL);
ISP5_PRINT_REGISTER(iss, IRQSTATUS(0));
ISP5_PRINT_REGISTER(iss, IRQENABLE_SET(0));
ISP5_PRINT_REGISTER(iss, IRQENABLE_CLR(0));
dev_dbg(iss->dev, "-----------------------------------------------\n");
}
/*
* ipipeif_enable - Enable/Disable IPIPEIF.
* @enable: enable flag
*
*/
static void ipipeif_enable(struct iss_ipipeif_device *ipipeif, u8 enable)
{
struct iss_device *iss = to_iss_device(ipipeif);
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_SYNCEN,
ISIF_SYNCEN_SYEN, enable ? ISIF_SYNCEN_SYEN : 0);
}
/*
* ipipe_enable - Enable/Disable IPIPE.
* @enable: enable flag
*
*/
static void ipipe_enable(struct iss_ipipe_device *ipipe, u8 enable)
{
struct iss_device *iss = to_iss_device(ipipe);
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_EN,
IPIPE_SRC_EN_EN, enable ? IPIPE_SRC_EN_EN : 0);
}
/*
* ipipeif_set_outaddr - Set memory address to save output image
* @ipipeif: Pointer to ISP IPIPEIF device.
* @addr: 32-bit memory address aligned on 32 byte boundary.
*
* Sets the memory address where the output will be saved.
*/
static void ipipeif_set_outaddr(struct iss_ipipeif_device *ipipeif, u32 addr)
{
struct iss_device *iss = to_iss_device(ipipeif);
/* Save address splitted in Base Address H & L */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CADU,
(addr >> (16 + 5)) & ISIF_CADU_MASK);
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CADL,
(addr >> 5) & ISIF_CADL_MASK);
}
/*
* ipipeif_set_stream - Enable/Disable streaming on the IPIPEIF module
* @sd: ISP IPIPEIF V4L2 subdevice
* @enable: Enable/disable stream
*/
static int ipipeif_set_stream(struct v4l2_subdev *sd, int enable)
{
struct iss_ipipeif_device *ipipeif = v4l2_get_subdevdata(sd);
struct iss_device *iss = to_iss_device(ipipeif);
struct iss_video *video_out = &ipipeif->video_out;
int ret = 0;
if (ipipeif->state == ISS_PIPELINE_STREAM_STOPPED) {
if (enable == ISS_PIPELINE_STREAM_STOPPED)
return 0;
omap4iss_isp_subclk_enable(iss, IPIPEIF_DRV_SUBCLK_MASK);
}
switch (enable) {
case ISS_PIPELINE_STREAM_CONTINUOUS:
ipipeif_configure(ipipeif);
ipipeif_print_status(ipipeif);
/*
* When outputting to memory with no buffer available, let the
* buffer queue handler start the hardware. A DMA queue flag
* ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
* a buffer available.
*/
if (ipipeif->output & IPIPEIF_OUTPUT_MEMORY &&
!(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED))
break;
atomic_set(&ipipeif->stopping, 0);
if (ipipeif->output & IPIPEIF_OUTPUT_MEMORY)
ipipeif_write_enable(ipipeif, 1);
ipipeif_enable(ipipeif, 1);
iss_video_dmaqueue_flags_clr(video_out);
break;
case ISS_PIPELINE_STREAM_STOPPED:
if (ipipeif->state == ISS_PIPELINE_STREAM_STOPPED)
return 0;
if (omap4iss_module_sync_idle(&sd->entity, &ipipeif->wait,
&ipipeif->stopping))
ret = -ETIMEDOUT;
if (ipipeif->output & IPIPEIF_OUTPUT_MEMORY)
ipipeif_write_enable(ipipeif, 0);
ipipeif_enable(ipipeif, 0);
omap4iss_isp_subclk_disable(iss, IPIPEIF_DRV_SUBCLK_MASK);
iss_video_dmaqueue_flags_clr(video_out);
break;
}
ipipeif->state = enable;
return ret;
}
/*
* ipipeif_link_setup - Setup IPIPEIF connections
* @entity: IPIPEIF media entity
* @local: Pad at the local end of the link
* @remote: Pad at the remote end of the link
* @flags: Link flags
*
* return -EINVAL or zero on success
*/
static int ipipeif_link_setup(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags)
{
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
struct iss_ipipeif_device *ipipeif = v4l2_get_subdevdata(sd);
struct iss_device *iss = to_iss_device(ipipeif);
switch (local->index | media_entity_type(remote->entity)) {
case IPIPEIF_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
/* Read from the sensor CSI2a or CSI2b. */
if (!(flags & MEDIA_LNK_FL_ENABLED)) {
ipipeif->input = IPIPEIF_INPUT_NONE;
break;
}
if (ipipeif->input != IPIPEIF_INPUT_NONE)
return -EBUSY;
if (remote->entity == &iss->csi2a.subdev.entity)
ipipeif->input = IPIPEIF_INPUT_CSI2A;
else if (remote->entity == &iss->csi2b.subdev.entity)
ipipeif->input = IPIPEIF_INPUT_CSI2B;
break;
case IPIPEIF_PAD_SOURCE_ISIF_SF | MEDIA_ENT_T_DEVNODE:
/* Write to memory */
if (flags & MEDIA_LNK_FL_ENABLED) {
if (ipipeif->output & ~IPIPEIF_OUTPUT_MEMORY)
return -EBUSY;
ipipeif->output |= IPIPEIF_OUTPUT_MEMORY;
} else {
ipipeif->output &= ~IPIPEIF_OUTPUT_MEMORY;
}
break;
case IPIPEIF_PAD_SOURCE_VP | MEDIA_ENT_T_V4L2_SUBDEV:
/* Send to IPIPE/RESIZER */
if (flags & MEDIA_LNK_FL_ENABLED) {
if (ipipeif->output & ~IPIPEIF_OUTPUT_VP)
return -EBUSY;
ipipeif->output |= IPIPEIF_OUTPUT_VP;
} else {
ipipeif->output &= ~IPIPEIF_OUTPUT_VP;
}
break;
default:
return -EINVAL;
}
return 0;
}
/*
* ipipeif_init_entities - Initialize V4L2 subdev and media entity
* @ipipeif: ISS ISP IPIPEIF module
*
* Return 0 on success and a negative error code on failure.
*/
static int ipipeif_init_entities(struct iss_ipipeif_device *ipipeif)
{
struct v4l2_subdev *sd = &ipipeif->subdev;
struct media_pad *pads = ipipeif->pads;
struct media_entity *me = &sd->entity;
int ret;
ipipeif->input = IPIPEIF_INPUT_NONE;
v4l2_subdev_init(sd, &ipipeif_v4l2_ops);
sd->internal_ops = &ipipeif_v4l2_internal_ops;
strlcpy(sd->name, "OMAP4 ISS ISP IPIPEIF", sizeof(sd->name));
sd->grp_id = 1 << 16; /* group ID for iss subdevs */
v4l2_set_subdevdata(sd, ipipeif);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
pads[IPIPEIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
pads[IPIPEIF_PAD_SOURCE_ISIF_SF].flags = MEDIA_PAD_FL_SOURCE;
pads[IPIPEIF_PAD_SOURCE_VP].flags = MEDIA_PAD_FL_SOURCE;
me->ops = &ipipeif_media_ops;
ret = media_entity_init(me, IPIPEIF_PADS_NUM, pads, 0);
if (ret < 0)
return ret;
ipipeif_init_formats(sd, NULL);
ipipeif->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
ipipeif->video_out.ops = &ipipeif_video_ops;
ipipeif->video_out.iss = to_iss_device(ipipeif);
ipipeif->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
ipipeif->video_out.bpl_alignment = 32;
ipipeif->video_out.bpl_zero_padding = 1;
ipipeif->video_out.bpl_max = 0x1ffe0;
ret = omap4iss_video_init(&ipipeif->video_out, "ISP IPIPEIF");
if (ret < 0)
return ret;
/* Connect the IPIPEIF subdev to the video node. */
ret = media_entity_create_link(&ipipeif->subdev.entity,
IPIPEIF_PAD_SOURCE_ISIF_SF,
&ipipeif->video_out.video.entity, 0, 0);
if (ret < 0)
return ret;
return 0;
}
/*
* ipipe_set_stream - Enable/Disable streaming on the IPIPE module
* @sd: ISP IPIPE V4L2 subdevice
* @enable: Enable/disable stream
*/
static int ipipe_set_stream(struct v4l2_subdev *sd, int enable)
{
struct iss_ipipe_device *ipipe = v4l2_get_subdevdata(sd);
struct iss_device *iss = to_iss_device(ipipe);
int ret = 0;
if (ipipe->state == ISS_PIPELINE_STREAM_STOPPED) {
if (enable == ISS_PIPELINE_STREAM_STOPPED)
return 0;
omap4iss_isp_subclk_enable(iss, OMAP4_ISS_ISP_SUBCLK_IPIPE);
/* Enable clk_arm_g0 */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_GCK_MMR,
IPIPE_GCK_MMR_REG);
/* Enable clk_pix_g[3:0] */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_GCK_PIX,
IPIPE_GCK_PIX_G3 | IPIPE_GCK_PIX_G2 |
IPIPE_GCK_PIX_G1 | IPIPE_GCK_PIX_G0);
}
switch (enable) {
case ISS_PIPELINE_STREAM_CONTINUOUS:
ipipe_configure(ipipe);
ipipe_print_status(ipipe);
atomic_set(&ipipe->stopping, 0);
ipipe_enable(ipipe, 1);
break;
case ISS_PIPELINE_STREAM_STOPPED:
if (ipipe->state == ISS_PIPELINE_STREAM_STOPPED)
return 0;
if (omap4iss_module_sync_idle(&sd->entity, &ipipe->wait,
&ipipe->stopping))
ret = -ETIMEDOUT;
ipipe_enable(ipipe, 0);
omap4iss_isp_subclk_disable(iss, OMAP4_ISS_ISP_SUBCLK_IPIPE);
break;
}
ipipe->state = enable;
return ret;
}
/*
* ipipe_link_setup - Setup IPIPE connections
* @entity: IPIPE media entity
* @local: Pad at the local end of the link
* @remote: Pad at the remote end of the link
* @flags: Link flags
*
* return -EINVAL or zero on success
*/
static int ipipe_link_setup(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags)
{
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
struct iss_ipipe_device *ipipe = v4l2_get_subdevdata(sd);
struct iss_device *iss = to_iss_device(ipipe);
if (!is_media_entity_v4l2_subdev(remote->entity))
return -EINVAL;
switch (local->index) {
case IPIPE_PAD_SINK:
/* Read from IPIPEIF. */
if (!(flags & MEDIA_LNK_FL_ENABLED)) {
ipipe->input = IPIPE_INPUT_NONE;
break;
}
if (ipipe->input != IPIPE_INPUT_NONE)
return -EBUSY;
if (remote->entity == &iss->ipipeif.subdev.entity)
ipipe->input = IPIPE_INPUT_IPIPEIF;
break;
case IPIPE_PAD_SOURCE_VP:
/* Send to RESIZER */
if (flags & MEDIA_LNK_FL_ENABLED) {
if (ipipe->output & ~IPIPE_OUTPUT_VP)
return -EBUSY;
ipipe->output |= IPIPE_OUTPUT_VP;
} else {
ipipe->output &= ~IPIPE_OUTPUT_VP;
}
break;
default:
return -EINVAL;
}
return 0;
}
static void ipipe_print_status(struct iss_ipipe_device *ipipe)
{
struct iss_device *iss = to_iss_device(ipipe);
dev_dbg(iss->dev, "-------------IPIPE Register dump-------------\n");
IPIPE_PRINT_REGISTER(iss, SRC_EN);
IPIPE_PRINT_REGISTER(iss, SRC_MODE);
IPIPE_PRINT_REGISTER(iss, SRC_FMT);
IPIPE_PRINT_REGISTER(iss, SRC_COL);
IPIPE_PRINT_REGISTER(iss, SRC_VPS);
IPIPE_PRINT_REGISTER(iss, SRC_VSZ);
IPIPE_PRINT_REGISTER(iss, SRC_HPS);
IPIPE_PRINT_REGISTER(iss, SRC_HSZ);
IPIPE_PRINT_REGISTER(iss, GCK_MMR);
IPIPE_PRINT_REGISTER(iss, YUV_PHS);
dev_dbg(iss->dev, "-----------------------------------------------\n");
}
static void ipipe_configure(struct iss_ipipe_device *ipipe)
{
struct iss_device *iss = to_iss_device(ipipe);
struct v4l2_mbus_framefmt *format;
/* IPIPE_PAD_SINK */
format = &ipipe->formats[IPIPE_PAD_SINK];
/* NOTE: Currently just supporting pipeline IN: RGB, OUT: YUV422 */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_FMT,
IPIPE_SRC_FMT_RAW2YUV);
/* Enable YUV444 -> YUV422 conversion */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_YUV_PHS,
IPIPE_YUV_PHS_LPF);
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_VPS, 0);
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_HPS, 0);
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_VSZ,
(format->height - 2) & IPIPE_SRC_VSZ_MASK);
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_HSZ,
(format->width - 1) & IPIPE_SRC_HSZ_MASK);
/* Ignore ipipeif_wrt signal, and operate on-the-fly. */
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_MODE,
IPIPE_SRC_MODE_WRT | IPIPE_SRC_MODE_OST);
/* HACK: Values tuned for Ducati SW (OV) */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_IPIPE, IPIPE_SRC_COL,
IPIPE_SRC_COL_EE_B | IPIPE_SRC_COL_EO_GB |
IPIPE_SRC_COL_OE_GR | IPIPE_SRC_COL_OO_R);
/* IPIPE_PAD_SOURCE_VP */
format = &ipipe->formats[IPIPE_PAD_SOURCE_VP];
/* Do nothing? */
}
static void ipipeif_configure(struct iss_ipipeif_device *ipipeif)
{
struct iss_device *iss = to_iss_device(ipipeif);
const struct iss_format_info *info;
struct v4l2_mbus_framefmt *format;
u32 isif_ccolp = 0;
omap4iss_configure_bridge(iss, ipipeif->input);
/* IPIPEIF_PAD_SINK */
format = &ipipeif->formats[IPIPEIF_PAD_SINK];
/* IPIPEIF with YUV422 input from ISIF */
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_IPIPEIF, IPIPEIF_CFG1,
IPIPEIF_CFG1_INPSRC1_MASK | IPIPEIF_CFG1_INPSRC2_MASK);
/* Select ISIF/IPIPEIF input format */
switch (format->code) {
case V4L2_MBUS_FMT_UYVY8_1X16:
case V4L2_MBUS_FMT_YUYV8_1X16:
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_MODESET,
ISIF_MODESET_CCDMD | ISIF_MODESET_INPMOD_MASK |
ISIF_MODESET_CCDW_MASK,
ISIF_MODESET_INPMOD_YCBCR16);
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_IPIPEIF, IPIPEIF_CFG2,
IPIPEIF_CFG2_YUV8, IPIPEIF_CFG2_YUV16);
break;
case V4L2_MBUS_FMT_SGRBG10_1X10:
isif_ccolp = ISIF_CCOLP_CP0_F0_GR |
ISIF_CCOLP_CP1_F0_R |
ISIF_CCOLP_CP2_F0_B |
ISIF_CCOLP_CP3_F0_GB;
goto cont_raw;
case V4L2_MBUS_FMT_SRGGB10_1X10:
isif_ccolp = ISIF_CCOLP_CP0_F0_R |
ISIF_CCOLP_CP1_F0_GR |
ISIF_CCOLP_CP2_F0_GB |
ISIF_CCOLP_CP3_F0_B;
goto cont_raw;
case V4L2_MBUS_FMT_SBGGR10_1X10:
isif_ccolp = ISIF_CCOLP_CP0_F0_B |
ISIF_CCOLP_CP1_F0_GB |
ISIF_CCOLP_CP2_F0_GR |
ISIF_CCOLP_CP3_F0_R;
goto cont_raw;
case V4L2_MBUS_FMT_SGBRG10_1X10:
isif_ccolp = ISIF_CCOLP_CP0_F0_GB |
ISIF_CCOLP_CP1_F0_B |
ISIF_CCOLP_CP2_F0_R |
ISIF_CCOLP_CP3_F0_GR;
cont_raw:
iss_reg_clr(iss, OMAP4_ISS_MEM_ISP_IPIPEIF, IPIPEIF_CFG2,
IPIPEIF_CFG2_YUV16);
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_MODESET,
ISIF_MODESET_CCDMD | ISIF_MODESET_INPMOD_MASK |
ISIF_MODESET_CCDW_MASK, ISIF_MODESET_INPMOD_RAW |
ISIF_MODESET_CCDW_2BIT);
info = omap4iss_video_format_info(format->code);
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CGAMMAWD,
ISIF_CGAMMAWD_GWDI_MASK,
ISIF_CGAMMAWD_GWDI(info->bpp));
/* Set RAW Bayer pattern */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CCOLP,
isif_ccolp);
break;
}
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_SPH, 0 & ISIF_SPH_MASK);
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_LNH,
(format->width - 1) & ISIF_LNH_MASK);
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_LNV,
(format->height - 1) & ISIF_LNV_MASK);
/* Generate ISIF0 on the last line of the image */
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_VDINT(0),
format->height - 1);
/* IPIPEIF_PAD_SOURCE_ISIF_SF */
format = &ipipeif->formats[IPIPEIF_PAD_SOURCE_ISIF_SF];
iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_HSIZE,
(ipipeif->video_out.bpl_value >> 5) &
ISIF_HSIZE_HSIZE_MASK);
/* IPIPEIF_PAD_SOURCE_VP */
/* Do nothing? */
}
