static irqreturn_t s5p_cec_irq_handler(int irq, void *dev_id)
{
u32 status = 0;
status = s5p_cec_get_status();
if (status & CEC_STATUS_TX_DONE) {
if (status & CEC_STATUS_TX_ERROR) {
tvout_dbg(" CEC_STATUS_TX_ERROR!\n");
s5p_cec_set_tx_state(STATE_ERROR);
} else {
tvout_dbg(" CEC_STATUS_TX_DONE!\n");
s5p_cec_set_tx_state(STATE_DONE);
}
s5p_clr_pending_tx();
wake_up_interruptible(&cec_tx_struct.waitq);
}
if (status & CEC_STATUS_RX_DONE) {
if (status & CEC_STATUS_RX_ERROR) {
tvout_dbg(" CEC_STATUS_RX_ERROR!\n");
s5p_cec_rx_reset();
} else {
u32 size;
tvout_dbg(" CEC_STATUS_RX_DONE!\n");
/* copy data from internal buffer */
size = status >> 24;
spin_lock(&cec_rx_struct.lock);
s5p_cec_get_rx_buf(size, cec_rx_struct.buffer);
cec_rx_struct.size = size;
s5p_cec_set_rx_state(STATE_DONE);
spin_unlock(&cec_rx_struct.lock);
s5p_cec_enable_rx();
}
/* clear interrupt pending bit */
s5p_clr_pending_rx();
wake_up_interruptible(&cec_rx_struct.waitq);
}
return IRQ_HANDLED;
}
int s5p_mixer_set_alpha(enum s5p_mixer_layer layer, u32 alpha)
{
u32 temp_reg;
tvout_dbg("%d, %d\n", layer, alpha);
switch (layer) {
case MIXER_VIDEO_LAYER:
temp_reg = readl(mixer_base + S5P_MXR_VIDEO_CFG)
& (~S5P_MXR_VIDEO_CFG_ALPHA_MASK) ;
temp_reg |= S5P_MXR_VIDEO_CFG_ALPHA_VALUE(alpha);
writel(temp_reg, mixer_base + S5P_MXR_VIDEO_CFG);
break;
case MIXER_GPR0_LAYER:
temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG)
& (~S5P_MXR_VIDEO_CFG_ALPHA_MASK) ;
temp_reg |= S5P_MXR_GRP_ALPHA_VALUE(alpha);
writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
break;
case MIXER_GPR1_LAYER:
temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG)
& (~S5P_MXR_VIDEO_CFG_ALPHA_MASK) ;
temp_reg |= S5P_MXR_GRP_ALPHA_VALUE(alpha);
writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
break;
default:
tvout_err("invalid layer parameter = %d\n", layer);
return -1;
}
return 0;
}
int s5p_mixer_set_grp_base_address(enum s5p_mixer_layer layer, u32 base_addr)
{
tvout_dbg("%d, 0x%x\n", layer, base_addr);
if (S5P_MXR_GRP_ADDR_ILLEGAL(base_addr)) {
tvout_err("address is not word align = %d\n", base_addr);
return -1;
}
switch (layer) {
case MIXER_GPR0_LAYER:
writel(S5P_MXR_GPR_BASE(base_addr),
mixer_base + S5P_MXR_GRAPHIC0_BASE);
break;
case MIXER_GPR1_LAYER:
writel(S5P_MXR_GPR_BASE(base_addr),
mixer_base + S5P_MXR_GRAPHIC1_BASE);
break;
default:
tvout_err("invalid layer parameter = %d\n", layer);
return -1;
}
return 0;
}
int s5p_mixer_set_grp_layer_dst_pos(enum s5p_mixer_layer layer,
u32 dst_offs_x, u32 dst_offs_y)
{
tvout_dbg("%d, %d, %d\n", layer, dst_offs_x, dst_offs_y);
switch (layer) {
case MIXER_GPR0_LAYER:
writel(S5P_MXR_GRP_DESTX(dst_offs_x) |
S5P_MXR_GRP_DESTY(dst_offs_y),
mixer_base + S5P_MXR_GRAPHIC0_DXY);
break;
case MIXER_GPR1_LAYER:
writel(S5P_MXR_GRP_DESTX(dst_offs_x) |
S5P_MXR_GRP_DESTY(dst_offs_y),
mixer_base + S5P_MXR_GRAPHIC1_DXY);
break;
default:
tvout_err("invalid layer parameter = %d\n", layer);
return -1;
}
return 0;
}
int s5p_mixer_set_grp_layer_src_pos(enum s5p_mixer_layer layer,
u32 src_offs_x, u32 src_offs_y, u32 span,
u32 width, u32 height)
{
tvout_dbg("%d, %d, %d, %d, %d, %d\n", layer, span, width, height, \
src_offs_x, src_offs_y);
switch (layer) {
case MIXER_GPR0_LAYER:
writel(S5P_MXR_GRP_SPAN(span),
mixer_base + S5P_MXR_GRAPHIC0_SPAN);
writel(S5P_MXR_GRP_WIDTH(width) | S5P_MXR_GRP_HEIGHT(height),
mixer_base + S5P_MXR_GRAPHIC0_WH);
writel(S5P_MXR_GRP_STARTX(src_offs_x) |
S5P_MXR_GRP_STARTY(src_offs_y),
mixer_base + S5P_MXR_GRAPHIC0_SXY);
break;
case MIXER_GPR1_LAYER:
writel(S5P_MXR_GRP_SPAN(span),
mixer_base + S5P_MXR_GRAPHIC1_SPAN);
writel(S5P_MXR_GRP_WIDTH(width) | S5P_MXR_GRP_HEIGHT(height),
mixer_base + S5P_MXR_GRAPHIC1_WH);
writel(S5P_MXR_GRP_STARTX(src_offs_x) |
S5P_MXR_GRP_STARTY(src_offs_y),
mixer_base + S5P_MXR_GRAPHIC1_SXY);
break;
default:
tvout_err(" invalid layer parameter = %d\n", layer);
return -1;
}
return 0;
}
int s5p_mixer_set_priority(enum s5p_mixer_layer layer, u32 priority)
{
u32 layer_cfg;
tvout_dbg("%d, %d\n", layer, priority);
switch (layer) {
case MIXER_VIDEO_LAYER:
layer_cfg = S5P_MXR_LAYER_CFG_VID_PRIORITY_CLR(
readl(mixer_base + S5P_MXR_LAYER_CFG)) |
S5P_MXR_LAYER_CFG_VID_PRIORITY(priority);
break;
case MIXER_GPR0_LAYER:
layer_cfg = S5P_MXR_LAYER_CFG_GRP0_PRIORITY_CLR(
readl(mixer_base + S5P_MXR_LAYER_CFG)) |
S5P_MXR_LAYER_CFG_GRP0_PRIORITY(priority);
break;
case MIXER_GPR1_LAYER:
layer_cfg = S5P_MXR_LAYER_CFG_GRP1_PRIORITY_CLR(
readl(mixer_base + S5P_MXR_LAYER_CFG)) |
S5P_MXR_LAYER_CFG_GRP1_PRIORITY(priority);
break;
default:
tvout_err("invalid layer parameter = %d\n", layer);
return -1;
}
writel(layer_cfg, mixer_base + S5P_MXR_LAYER_CFG);
return 0;
}
static int s5p_cec_open(struct inode *inode, struct file *file)
{
int ret = 0;
mutex_lock(&cec_lock);
clk_enable(hdmi_cec_clk);
if (atomic_read(&hdmi_on)) {
tvout_dbg("do not allow multiple open for tvout cec\n");
ret = -EBUSY;
goto err_multi_open;
} else
atomic_inc(&hdmi_on);
s5p_cec_reset();
s5p_cec_set_divider();
s5p_cec_threshold();
s5p_cec_unmask_tx_interrupts();
s5p_cec_set_rx_state(STATE_RX);
s5p_cec_unmask_rx_interrupts();
s5p_cec_enable_rx();
err_multi_open:
mutex_unlock(&cec_lock);
return ret;
}
void s5p_sdo_set_cvbs_color_compensation(struct s5p_sdo_cvbs_compensation \
cvbs_comp)
{
u32 temp_reg = 0;
tvout_dbg("%d, %d, %d, %d, %d, %d\n",
cvbs_comp.cvbs_color_compen, cvbs_comp.y_lower_mid,
cvbs_comp.y_bottom, cvbs_comp.y_top,
cvbs_comp.y_upper_mid, cvbs_comp.radius);
temp_reg = readl(sdo_base + S5P_SDO_CCCON);
if (cvbs_comp.cvbs_color_compen)
temp_reg &= ~S5P_SDO_COMPENSATION_CVBS_COMP_OFF;
else
temp_reg |= S5P_SDO_COMPENSATION_CVBS_COMP_OFF;
writel(temp_reg, sdo_base + S5P_SDO_CCCON);
writel(S5P_SDO_Y_LOWER_MID_CVBS_CORN(cvbs_comp.y_lower_mid) |
S5P_SDO_Y_BOTTOM_CVBS_CORN(cvbs_comp.y_bottom),
sdo_base + S5P_SDO_CVBS_CC_Y1);
writel(S5P_SDO_Y_TOP_CVBS_CORN(cvbs_comp.y_top) |
S5P_SDO_Y_UPPER_MID_CVBS_CORN(cvbs_comp.y_upper_mid),
sdo_base + S5P_SDO_CVBS_CC_Y2);
writel(S5P_SDO_RADIUS_CVBS_CORN(cvbs_comp.radius),
sdo_base + S5P_SDO_CVBS_CC_C);
}
static int s5p_hdp_irq_eint(int irq)
{
if (hpd_struct.read_gpio()) {
irq_set_irq_type(hpd_struct.irq_n, IRQ_TYPE_LEVEL_LOW);
if (atomic_read(&hpd_struct.state) == HPD_HI)
return IRQ_HANDLED;
atomic_set(&hpd_struct.state, HPD_HI);
atomic_set(&poll_state, 1);
last_hpd_state = HPD_HI;
wake_up_interruptible(&hpd_struct.waitq);
} else {
irq_set_irq_type(hpd_struct.irq_n, IRQ_TYPE_LEVEL_HIGH);
if (atomic_read(&hpd_struct.state) == HPD_LO)
return IRQ_HANDLED;
atomic_set(&hpd_struct.state, HPD_LO);
atomic_set(&poll_state, 1);
last_hpd_state = HPD_LO;
wake_up_interruptible(&hpd_struct.waitq);
}
schedule_work(&hpd_work);
tvout_dbg("%s\n", atomic_read(&hpd_struct.state) == HPD_HI ?
"HPD HI" : "HPD LO");
return IRQ_HANDLED;
}
void s5p_sdo_set_offset_gain(u32 offset, u32 gain)
{
tvout_dbg("%d, %d\n", offset, gain);
writel(S5P_SDO_SCALE_CONV_OFFSET(offset) |
S5P_SDO_SCALE_CONV_GAIN(gain),
sdo_base + S5P_SDO_SCALE_CH0);
}
void s5p_sdo_set_closed_caption(u32 display_cc, u32 non_display_cc)
{
tvout_dbg("%d, %d\n", display_cc, non_display_cc);
writel(S5P_SDO_DISPLAY_CC_CAPTION(display_cc) |
S5P_SDO_NON_DISPLAY_CC_CAPTION(non_display_cc),
sdo_base + S5P_SDO_ARMCC);
}
void s5p_sdo_set_ch_xtalk_cancel_coef(u32 coeff2, u32 coeff1)
{
tvout_dbg("%d, %d\n", coeff2, coeff1);
writel(S5P_SDO_XTALK_COEF02(coeff2) |
S5P_SDO_XTALK_COEF01(coeff1),
sdo_base + S5P_SDO_XTALK0);
}
void s5p_sdo_clock_on(bool on)
{
tvout_dbg("%d\n", on);
if (on)
writel(S5P_SDO_TVOUT_CLOCK_ON, sdo_base + S5P_SDO_CLKCON);
else
writel(S5P_SDO_TVOUT_CLOCK_OFF, sdo_base + S5P_SDO_CLKCON);
}
/*
* HPD interrupt handler
*
* Handles interrupt requests from HPD hardware.
* Handler changes value of internal variable and notifies waiting thread.
*/
static irqreturn_t s5p_hpd_irq_handler(int irq, void *dev_id)
{
irqreturn_t ret = IRQ_HANDLED;
/* check HDMI status */
if (atomic_read(&hdmi_status)) {
/* HDMI on */
ret = s5p_hpd_irq_hdmi(irq);
tvout_dbg("HDMI HPD interrupt\n");
} else {
/* HDMI off */
ret = s5p_hdp_irq_eint(irq);
tvout_dbg("EINT HPD interrupt\n");
}
return ret;
}
void s5p_sdo_sw_reset(bool active)
{
tvout_dbg("%d\n", active);
if (active)
writel(readl(sdo_base + S5P_SDO_CLKCON) |
S5P_SDO_TVOUT_SW_RESET, sdo_base + S5P_SDO_CLKCON);
else
writel(readl(sdo_base + S5P_SDO_CLKCON) &
~S5P_SDO_TVOUT_SW_RESET, sdo_base + S5P_SDO_CLKCON);
}
void s5p_sdo_set_delay(u32 delay_y, u32 offset_video_start,
u32 offset_video_end)
{
tvout_dbg("%d, %d, %d\n", delay_y, offset_video_start,
offset_video_end);
writel(S5P_SDO_DELAY_YTOC(delay_y) |
S5P_SDO_ACTIVE_START_OFFSET(offset_video_start) |
S5P_SDO_ACTIVE_END_OFFSET(offset_video_end),
sdo_base + S5P_SDO_YCDELAY);
}
void s5p_sdo_set_schlock(bool color_sucarrier_pha_adj)
{
tvout_dbg("%d\n", color_sucarrier_pha_adj);
if (color_sucarrier_pha_adj)
writel(S5P_SDO_COLOR_SC_PHASE_ADJ,
sdo_base + S5P_SDO_SCHLOCK);
else
writel(S5P_SDO_COLOR_SC_PHASE_NOADJ,
sdo_base + S5P_SDO_SCHLOCK);
}
void s5p_sdo_set_interrupt_enable(bool vsync_intc_en)
{
tvout_dbg("%d\n", vsync_intc_en);
if (vsync_intc_en)
writel(readl(sdo_base + S5P_SDO_IRQMASK) &
~S5P_SDO_VSYNC_IRQ_DISABLE, sdo_base + S5P_SDO_IRQMASK);
else
writel(readl(sdo_base + S5P_SDO_IRQMASK) |
S5P_SDO_VSYNC_IRQ_DISABLE, sdo_base + S5P_SDO_IRQMASK);
}
void s5p_sdo_dac_on(bool on)
{
tvout_dbg("%d\n", on);
if (on) {
writel(S5P_SDO_POWER_ON_DAC, sdo_base + S5P_SDO_DAC);
writel(S5P_DAC_ENABLE, S5P_DAC_CONTROL);
} else {
writel(S5P_DAC_DISABLE, S5P_DAC_CONTROL);
writel(S5P_SDO_POWER_DOWN_DAC, sdo_base + S5P_SDO_DAC);
}
}
void s5p_sdo_set_component_porch(u32 back_525, u32 front_525, \
u32 back_625, u32 front_625)
{
tvout_dbg("%d, %d, %d, %d\n",
back_525, front_525, back_625, front_625);
writel(S5P_SDO_COMPONENT_525_BP(back_525) |
S5P_SDO_COMPONENT_525_FP(front_525),
sdo_base + S5P_SDO_CSC_525_PORCH);
writel(S5P_SDO_COMPONENT_625_BP(back_625) |
S5P_SDO_COMPONENT_625_FP(front_625),
sdo_base + S5P_SDO_CSC_625_PORCH);
}
u32 s5p_cec_get_status(void)
{
u32 status = 0;
status = readb(cec_base + S5P_CES_STATUS_0);
status |= readb(cec_base + S5P_CES_STATUS_1) << 8;
status |= readb(cec_base + S5P_CES_STATUS_2) << 16;
status |= readb(cec_base + S5P_CES_STATUS_3) << 24;
tvout_dbg("status = 0x%x!\n", status);
return status;
}
int s5p_mixer_set_layer_blend(enum s5p_mixer_layer layer, bool enable)
{
u32 temp_reg;
tvout_dbg("%d, %d\n", layer, enable);
switch (layer) {
case MIXER_VIDEO_LAYER:
temp_reg = readl(mixer_base + S5P_MXR_VIDEO_CFG)
& (~S5P_MXR_VIDEO_CFG_BLEND_EN) ;
if (enable)
temp_reg |= S5P_MXR_VIDEO_CFG_BLEND_EN;
else
temp_reg |= S5P_MXR_VIDEO_CFG_BLEND_DIS;
writel(temp_reg, mixer_base + S5P_MXR_VIDEO_CFG);
break;
case MIXER_GPR0_LAYER:
temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC0_CFG)
& (~S5P_MXR_WIN_BLEND_ENABLE) ;
if (enable)
temp_reg |= S5P_MXR_WIN_BLEND_ENABLE;
else
temp_reg |= S5P_MXR_WIN_BLEND_DISABLE;
writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC0_CFG);
break;
case MIXER_GPR1_LAYER:
temp_reg = readl(mixer_base + S5P_MXR_GRAPHIC1_CFG)
& (~S5P_MXR_WIN_BLEND_ENABLE) ;
if (enable)
temp_reg |= S5P_MXR_WIN_BLEND_ENABLE;
else
temp_reg |= S5P_MXR_WIN_BLEND_DISABLE;
writel(temp_reg, mixer_base + S5P_MXR_GRAPHIC1_CFG);
break;
default:
tvout_err("invalid layer parameter = %d\n", layer);
return -1;
}
return 0;
}
void s5p_mixer_set_vsync_interrupt(bool en)
{
if (en) {
writel(S5P_MXR_INT_STATUS_VSYNC_CLEARED, mixer_base +
S5P_MXR_INT_STATUS);
writel((readl(mixer_base + S5P_MXR_INT_EN) |
S5P_MXR_INT_EN_VSYNC_ENABLE),
mixer_base + S5P_MXR_INT_EN);
} else {
writel((readl(mixer_base + S5P_MXR_INT_EN) &
~S5P_MXR_INT_EN_VSYNC_ENABLE),
mixer_base + S5P_MXR_INT_EN);
}
tvout_dbg("%s mixer VSYNC interrupt.\n", en ? "Enable" : "Disable");
}
void s5p_mixer_init_csc_coef_default(enum s5p_mixer_csc_type csc_type)
{
tvout_dbg("%d\n", csc_type);
switch (csc_type) {
case MIXER_CSC_601_LR:
writel((0 << 30) | (153 << 20) | (300 << 10) | (58 << 0),
mixer_base + S5P_MXR_CM_COEFF_Y);
writel((936 << 20) | (851 << 10) | (262 << 0),
mixer_base + S5P_MXR_CM_COEFF_CB);
writel((262 << 20) | (805 << 10) | (982 << 0),
mixer_base + S5P_MXR_CM_COEFF_CR);
break;
case MIXER_CSC_601_FR:
writel((1 << 30) | (132 << 20) | (258 << 10) | (50 << 0),
mixer_base + S5P_MXR_CM_COEFF_Y);
writel((948 << 20) | (875 << 10) | (225 << 0),
mixer_base + S5P_MXR_CM_COEFF_CB);
writel((225 << 20) | (836 << 10) | (988 << 0),
mixer_base + S5P_MXR_CM_COEFF_CR);
break;
case MIXER_CSC_709_LR:
writel((0 << 30) | (109 << 20) | (366 << 10) | (36 << 0),
mixer_base + S5P_MXR_CM_COEFF_Y);
writel((964 << 20) | (822 << 10) | (216 << 0),
mixer_base + S5P_MXR_CM_COEFF_CB);
writel((262 << 20) | (787 << 10) | (1000 << 0),
mixer_base + S5P_MXR_CM_COEFF_CR);
break;
case MIXER_CSC_709_FR:
writel((1 << 30) | (94 << 20) | (314 << 10) | (32 << 0),
mixer_base + S5P_MXR_CM_COEFF_Y);
writel((972 << 20) | (851 << 10) | (225 << 0),
mixer_base + S5P_MXR_CM_COEFF_CB);
writel((225 << 20) | (820 << 10) | (1004 << 0),
mixer_base + S5P_MXR_CM_COEFF_CR);
break;
default:
tvout_err("invalid csc_type parameter = %d\n", csc_type);
break;
}
}
int s5p_sdo_set_video_scale_cfg(enum s5p_sdo_level composite_level,
enum s5p_sdo_vsync_ratio composite_ratio)
{
u32 temp_reg = 0;
tvout_dbg("%d, %d\n", composite_level, composite_ratio);
switch (composite_level) {
case SDO_LEVEL_0IRE:
temp_reg |= S5P_SDO_COMPOSITE_LEVEL_SEL_0IRE;
break;
case SDO_LEVEL_75IRE:
temp_reg |= S5P_SDO_COMPOSITE_LEVEL_SEL_75IRE;
break;
default:
tvout_err("invalid composite_level parameter(%d)\n", \
composite_ratio);
return -1;
}
switch (composite_ratio) {
case SDO_VTOS_RATIO_10_4:
temp_reg |= S5P_SDO_COMPOSITE_VTOS_RATIO_10_4;
break;
case SDO_VTOS_RATIO_7_3:
temp_reg |= S5P_SDO_COMPOSITE_VTOS_RATIO_7_3;
break;
default:
tvout_err("invalid composite_ratio parameter(%d)\n", \
composite_ratio);
return -1;
}
writel(temp_reg, sdo_base + S5P_SDO_SCALE);
return 0;
}
int s5p_sdo_set_vbi(bool wss_cvbs,
enum s5p_sdo_closed_caption_type caption_cvbs)
{
u32 temp_reg = 0;
tvout_dbg("%d, %d\n", wss_cvbs, caption_cvbs);
if (wss_cvbs)
temp_reg = S5P_SDO_CVBS_WSS_INS;
else
temp_reg = S5P_SDO_CVBS_NO_WSS;
switch (caption_cvbs) {
case SDO_NO_INS:
temp_reg |= S5P_SDO_CVBS_NO_CLOSED_CAPTION;
break;
case SDO_INS_1:
temp_reg |= S5P_SDO_CVBS_21H_CLOSED_CAPTION;
break;
case SDO_INS_2:
temp_reg |= S5P_SDO_CVBS_21H_284H_CLOSED_CAPTION;
break;
case SDO_INS_OTHERS:
temp_reg |= S5P_SDO_CVBS_USE_OTHERS;
break;
default:
tvout_err("invalid caption_cvbs parameter(%d)\n",
caption_cvbs);
return -1;
}
writel(temp_reg, sdo_base + S5P_SDO_VBI);
return 0;
}
int s5p_mixer_set_show(enum s5p_mixer_layer layer, bool show)
{
u32 mxr_config;
tvout_dbg("%d, %d\n", layer, show);
switch (layer) {
case MIXER_VIDEO_LAYER:
mxr_config = (show) ?
(readl(mixer_base + S5P_MXR_CFG) |
S5P_MXR_CFG_VIDEO_ENABLE) :
(readl(mixer_base + S5P_MXR_CFG) &
~S5P_MXR_CFG_VIDEO_ENABLE);
break;
case MIXER_GPR0_LAYER:
mxr_config = (show) ?
(readl(mixer_base + S5P_MXR_CFG) |
S5P_MXR_CFG_GRAPHIC0_ENABLE) :
(readl(mixer_base + S5P_MXR_CFG) &
~S5P_MXR_CFG_GRAPHIC0_ENABLE);
break;
case MIXER_GPR1_LAYER:
mxr_config = (show) ?
(readl(mixer_base + S5P_MXR_CFG) |
S5P_MXR_CFG_GRAPHIC1_ENABLE) :
(readl(mixer_base + S5P_MXR_CFG) &
~S5P_MXR_CFG_GRAPHIC1_ENABLE);
break;
default:
tvout_err("invalid layer parameter = %d\n", layer);
return -1;
}
writel(mxr_config, mixer_base + S5P_MXR_CFG);
return 0;
}
static long s5p_cec_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
#endif
{
u32 laddr;
switch (cmd) {
case CEC_IOC_SETLADDR:
if (get_user(laddr, (u32 __user *) arg))
return -EFAULT;
tvout_dbg("logical address = 0x%02x\n", laddr);
s5p_cec_set_addr(laddr);
break;
default:
return -EINVAL;
}
return 0;
}
void s5p_mixer_init_bg_dither_enable(bool cr_dither_enable,
bool cb_dither_enable,
bool y_dither_enable)
{
u32 temp_reg = 0;
tvout_dbg("%d, %d, %d\n", cr_dither_enable, cb_dither_enable,
y_dither_enable);
temp_reg = (cr_dither_enable) ?
(temp_reg | S5P_MXR_BG_CR_DIHER_EN) :
(temp_reg & ~S5P_MXR_BG_CR_DIHER_EN);
temp_reg = (cb_dither_enable) ?
(temp_reg | S5P_MXR_BG_CB_DIHER_EN) :
(temp_reg & ~S5P_MXR_BG_CB_DIHER_EN);
temp_reg = (y_dither_enable) ?
(temp_reg | S5P_MXR_BG_Y_DIHER_EN) :
(temp_reg & ~S5P_MXR_BG_Y_DIHER_EN);
writel(temp_reg, mixer_base + S5P_MXR_BG_CFG);
}
void s5p_sdo_set_brightness_hue_saturation(struct \
s5p_sdo_bright_hue_saturation bri_hue_sat)
{
u32 temp_reg = 0;
tvout_dbg("%d, %d, %d, %d, %d, %d, %d, %d, %d\n",
bri_hue_sat.bright_hue_sat_adj, bri_hue_sat.gain_brightness,
bri_hue_sat.offset_brightness, bri_hue_sat.gain0_cb_hue_sat,
bri_hue_sat.gain1_cb_hue_sat, bri_hue_sat.gain0_cr_hue_sat,
bri_hue_sat.gain1_cr_hue_sat, bri_hue_sat.offset_cb_hue_sat,
bri_hue_sat.offset_cr_hue_sat);
temp_reg = readl(sdo_base + S5P_SDO_CCCON);
if (bri_hue_sat.bright_hue_sat_adj)
temp_reg &= ~S5P_SDO_COMPENSATION_BHS_ADJ_OFF;
else
temp_reg |= S5P_SDO_COMPENSATION_BHS_ADJ_OFF;
writel(temp_reg, sdo_base + S5P_SDO_CCCON);
writel(S5P_SDO_BRIGHTNESS_GAIN(bri_hue_sat.gain_brightness) |
S5P_SDO_BRIGHTNESS_OFFSET(bri_hue_sat.offset_brightness),
sdo_base + S5P_SDO_YSCALE);
writel(S5P_SDO_HS_CB_GAIN0(bri_hue_sat.gain0_cb_hue_sat) |
S5P_SDO_HS_CB_GAIN1(bri_hue_sat.gain1_cb_hue_sat),
sdo_base + S5P_SDO_CBSCALE);
writel(S5P_SDO_HS_CR_GAIN0(bri_hue_sat.gain0_cr_hue_sat) |
S5P_SDO_HS_CR_GAIN1(bri_hue_sat.gain1_cr_hue_sat),
sdo_base + S5P_SDO_CRSCALE);
writel(S5P_SDO_HS_CR_OFFSET(bri_hue_sat.offset_cr_hue_sat) |
S5P_SDO_HS_CB_OFFSET(bri_hue_sat.offset_cb_hue_sat),
sdo_base + S5P_SDO_CB_CR_OFFSET);
}