int tv_out_open(int mode)
{
const reg_t *s;
if (TVOUT_VALID(mode))
{
tvmode = mode;
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
chip_version_init();
tvoutc_setclk(mode);
enable_vsync_interrupt();
WRITE_MPEG_REG(VPP_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
change_vdac_setting(0x120120, mode);
set_disp_mode_auto(mode );
return 0;
}
return -1;
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
printk(KERN_DEBUG "TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
tvoutc_setclk(mode);
enable_vsync_interrupt();
WRITE_MPEG_REG(VPP_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
return 0;
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
const tvinfo_t * tvinfo;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
static int uboot_display_flag = 1;
#else
static int uboot_display_flag = 0;
#endif
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
mutex_lock(&setmode_mutex);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
//TODO
// switch_mod_gate_by_name("venc", 1);
#endif
tvinfo = tvinfo_mode(mode);
if(!tvinfo) {
printk(KERN_ERR "tvinfo %d not find\n", mode);
mutex_unlock(&setmode_mutex);
return 0;
}
printk("TV mode %s selected.\n", tvinfo->id);
#ifdef CONFIG_ARCH_MESON8B
if( (mode!=TVMODE_480CVBS) && (mode!=TVMODE_576CVBS) )
{
CLK_GATE_OFF(CTS_VDAC);
CLK_GATE_OFF(DAC_CLK);
}
if( (mode!=TVMODE_480I) && (mode!=TVMODE_480CVBS) &&
(mode!=TVMODE_576I) && (mode!=TVMODE_576CVBS) )
{
CLK_GATE_OFF(CTS_ENCI);
CLK_GATE_OFF(VCLK2_ENCI);
CLK_GATE_OFF(VCLK2_VENCI1);
}
#endif
s = tvregs_setting_mode(mode);
if(!s) {
printk("display mode %d regs setting failed\n", mode);
mutex_lock(&setmode_mutex);
return 0;
}
//s = tvregsTab[mode];
if(uboot_display_flag) {
uboot_display_flag = 0;
if(uboot_display_already(mode)) {
printk("already display in uboot\n");
mutex_unlock(&setmode_mutex);
return 0;
}
}
#if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
// for hdmi mode, disable HPLL as soon as possible
if( (mode==TVMODE_480I) || (mode==TVMODE_480P) ||
(mode==TVMODE_576I) || (mode==TVMODE_576P) ||
(mode==TVMODE_720P) || (mode==TVMODE_720P_50HZ) ||
(mode==TVMODE_1080I) || (mode==TVMODE_1080I_50HZ) ||
(mode==TVMODE_1080P) || (mode==TVMODE_1080P_50HZ) ||
(mode==TVMODE_1080P_24HZ) || (mode==TVMODE_4K2K_24HZ) ||
(mode==TVMODE_4K2K_25HZ) || (mode==TVMODE_4K2K_30HZ) || (mode==TVMODE_4K2K_FAKE_5G) ||
(mode==TVMODE_4K2K_SMPTE) || (mode==TVMODE_4K2K_60HZ) )
{
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV
// NOTE: for G9TV, DO NOT TURN OFF HPLL
#else
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 0x0, 30, 1);
#endif
}
cvbs_cntl_output(0);
#endif
while (MREG_END_MARKER != s->reg)
setreg(s++);
printk("%s[%d]\n", __func__, __LINE__);
#ifdef CONFIG_CVBS_PERFORMANCE_COMPATIBLITY_SUPPORT
cvbs_performance_enhancement(mode);
#endif
if(mode >= TVMODE_VGA && mode <= TVMODE_FHDVGA){ //set VGA pinmux
aml_write_reg32(P_PERIPHS_PIN_MUX_0, (aml_read_reg32(P_PERIPHS_PIN_MUX_0)|(3<<20)));
}else{
aml_write_reg32(P_PERIPHS_PIN_MUX_0, (aml_read_reg32(P_PERIPHS_PIN_MUX_0)&(~(3<<20))));
}
printk("%s[%d] mode is %d\n", __func__, __LINE__, mode);
#if ((defined CONFIG_ARCH_MESON8) || (defined CONFIG_ARCH_MESON8B))
// for hdmi mode, leave the hpll setting to be done by hdmi module.
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
set_tvmode_misc(mode);
#else
set_tvmode_misc(mode);
#endif
#ifdef CONFIG_ARCH_MESON1
tvoutc_setclk(mode);
printk("%s[%d]\n", __func__, __LINE__);
enable_vsync_interrupt();
#endif
#ifdef CONFIG_AM_TV_OUTPUT2
switch(mode)
{
case TVMODE_480I:
case TVMODE_480I_RPT:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576I_RPT:
case TVMODE_576CVBS:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 0, 2); //reg0x271a, select ENCI to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 4, 4); //reg0x271a, Select encI clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 8, 4); //reg0x271a,Enable VIU of ENC_I domain to VDIN;
break;
case TVMODE_480P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_480P_59HZ:
#endif
case TVMODE_480P_RPT:
case TVMODE_576P:
case TVMODE_576P_RPT:
case TVMODE_720P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_720P_59HZ:
#endif
case TVMODE_720P_50HZ:
case TVMODE_1080I: //??
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080I_59HZ:
#endif
case TVMODE_1080I_50HZ: //??
case TVMODE_1080P:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080P_59HZ:
#endif
case TVMODE_1080P_50HZ:
case TVMODE_1080P_24HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_1080P_23HZ:
#endif
case TVMODE_4K2K_30HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_4K2K_29HZ:
#endif
case TVMODE_4K2K_25HZ:
case TVMODE_4K2K_24HZ:
#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
case TVMODE_4K2K_23HZ:
#endif
case TVMODE_4K2K_SMPTE:
case TVMODE_4K2K_FAKE_5G:
case TVMODE_4K2K_60HZ:
case TVMODE_VGA:
case TVMODE_SVGA:
case TVMODE_XGA:
case TVMODE_SXGA:
case TVMODE_WSXGA:
case TVMODE_FHDVGA:
default:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 0, 2); //reg0x271a, select ENCP to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 4, 4); //reg0x271a, Select encP clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 8, 4); //reg0x271a,Enable VIU of ENC_P domain to VDIN;
break;
}
#endif
aml_write_reg32(P_VPP_POSTBLEND_H_SIZE, tvinfo->xres);
#ifdef CONFIG_ARCH_MESON3
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
#ifdef CONFIG_ARCH_MESON6
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
if(get_power_level() == 0) {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x5);
} else {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x7);
}
} else {
if(get_power_level() == 0) {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x0);
} else {
aml_write_reg32(P_VENC_VDAC_SETTING, 0x7);
}
}
#endif
#if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8)
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
CLK_GATE_ON(VCLK2_ENCI);
CLK_GATE_ON(VCLK2_VENCI1);
CLK_GATE_ON(CTS_ENCI);
CLK_GATE_ON(CTS_VDAC);
CLK_GATE_ON(DAC_CLK);
cvbs_cntl_output(1);
}
#endif
//while(1);
mutex_unlock(&setmode_mutex);
return 0;
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_name("venc", 1);
#endif
printk(KERN_DEBUG "TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
printk("%s[%d]\n", __func__, __LINE__);
// if (mode < TVMODE_VGA)
set_tvmode_misc(mode);
#ifdef CONFIG_ARCH_MESON1
tvoutc_setclk(mode);
printk("%s[%d]\n", __func__, __LINE__);
enable_vsync_interrupt();
#endif
#ifdef CONFIG_AM_TV_OUTPUT2
switch(mode)
{
case TVMODE_480I:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576CVBS:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 1, 0, 2); //reg0x271a, select ENCI to VIU1
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 1, 4, 4); //reg0x271a, Select encI clock to VDIN
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 1, 8, 4); //reg0x271a,Enable VIU of ENC_I domain to VDIN;
break;
case TVMODE_480P:
case TVMODE_576P:
case TVMODE_720P:
case TVMODE_720P_50HZ:
case TVMODE_1080I: //??
case TVMODE_1080I_50HZ: //??
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 0, 2); //reg0x271a, select ENCP to VIU1
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 4, 4); //reg0x271a, Select encP clock to VDIN
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 2, 8, 4); //reg0x271a,Enable VIU of ENC_P domain to VDIN;
break;
default:
printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
}
#endif
WRITE_MPEG_REG(VPP_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
#ifdef CONFIG_ARCH_MESON3
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
//while(1);
return 0;
}
int tvoutc_setmode(tvmode_t mode)
{
const reg_t *s;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
static int uboot_display_flag = 1;
#else
static int uboot_display_flag = 0;
#endif
if (mode >= TVMODE_MAX) {
printk(KERN_ERR "Invalid video output modes.\n");
return -ENODEV;
}
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
//TODO
// switch_mod_gate_by_name("venc", 1);
#endif
printk("TV mode %s selected.\n", tvinfoTab[mode].id);
s = tvregsTab[mode];
if(uboot_display_flag) {
uboot_display_flag = 0;
if(uboot_display_already(mode)) {
printk("already display in uboot\n");
return 0;
}
}
while (MREG_END_MARKER != s->reg)
setreg(s++);
printk("%s[%d]\n", __func__, __LINE__);
if(mode >= TVMODE_VGA || mode <= TVMODE_SXGA){
aml_write_reg32(P_PERIPHS_PIN_MUX_0,aml_read_reg32(P_PERIPHS_PIN_MUX_0)|(3<<20));
}else{
aml_write_reg32(P_PERIPHS_PIN_MUX_0,aml_read_reg32(P_PERIPHS_PIN_MUX_0)&(~(3<<20)));
}
set_tvmode_misc(mode);
#ifdef CONFIG_ARCH_MESON1
tvoutc_setclk(mode);
printk("%s[%d]\n", __func__, __LINE__);
enable_vsync_interrupt();
#endif
#ifdef CONFIG_AM_TV_OUTPUT2
switch(mode)
{
case TVMODE_480I:
case TVMODE_480CVBS:
case TVMODE_576I:
case TVMODE_576CVBS:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 0, 2); //reg0x271a, select ENCI to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 4, 4); //reg0x271a, Select encI clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 1, 8, 4); //reg0x271a,Enable VIU of ENC_I domain to VDIN;
break;
case TVMODE_480P:
case TVMODE_576P:
case TVMODE_720P:
case TVMODE_720P_50HZ:
case TVMODE_1080I: //??
case TVMODE_1080I_50HZ: //??
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
case TVMODE_1080P_24HZ:
case TVMODE_4K2K_30HZ:
case TVMODE_4K2K_25HZ:
case TVMODE_4K2K_24HZ:
case TVMODE_4K2K_SMPTE:
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 0, 2); //reg0x271a, select ENCP to VIU1
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 4, 4); //reg0x271a, Select encP clock to VDIN
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, 2, 8, 4); //reg0x271a,Enable VIU of ENC_P domain to VDIN;
break;
default:
printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
}
#endif
aml_write_reg32(P_VPP_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
#ifdef CONFIG_ARCH_MESON3
printk(" clk_util_clk_msr 6 = %d\n", clk_util_clk_msr(6));
printk(" clk_util_clk_msr 7 = %d\n", clk_util_clk_msr(7));
printk(" clk_util_clk_msr 8 = %d\n", clk_util_clk_msr(8));
printk(" clk_util_clk_msr 9 = %d\n", clk_util_clk_msr(9));
printk(" clk_util_clk_msr 10 = %d\n", clk_util_clk_msr(10));
printk(" clk_util_clk_msr 27 = %d\n", clk_util_clk_msr(27));
printk(" clk_util_clk_msr 29 = %d\n", clk_util_clk_msr(29));
#endif
#ifdef CONFIG_ARCH_MESON8
if( (mode==TVMODE_480CVBS) || (mode==TVMODE_576CVBS) )
{
msleep(1000);
aml_write_reg32(P_HHI_VDAC_CNTL0,0x650001);
aml_write_reg32(P_HHI_VDAC_CNTL1,0x1);
}
#endif
//while(1);
return 0;
}
