//*****************************************************************************
//
// The interrupt handler for the periodic timer interrupt. When the uDMA
// channel is used, interrupts from the periodic timer are used as DMA
// requests, and this interrupt handler is invoked only at the end of all of
// the DMA transfers.
//
//*****************************************************************************
void
Timer0IntHandler(void)
{
unsigned long ulStatus;
//
// Clear the timer interrupt.
//
ROM_TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
//
// Read the uDMA channel status to verify it is done
//
ulStatus = uDMAChannelModeGet(UDMA_CHANNEL_TMR0A);
if(ulStatus == UDMA_MODE_STOP)
{
//
// Disable the periodic timer and set the done flag
//
ROM_TimerDisable(TIMER0_BASE, TIMER_A);
g_bDoneFlag = 1;
}
//
// Increment a counter to indicate the number of times this handler
// was invoked
//
g_ulTimer0AIntCount++;
}
void EthernetISR() {
unsigned long temp = ROM_EthernetIntStatus(ETH_BASE, 0);
ROM_EthernetIntClear(ETH_BASE, temp);
if (temp & ETH_INT_RX) {
ROM_EthernetIntDisable(ETH_BASE, ETH_INT_RX);
ethRxFlag = 1;
}
if (temp & ETH_INT_RXOF) {
/* Receive FIFO-Overflow, clear the FIFO */
eth_rx_fifo_clear();
}
/*
* Check to see if the Ethernet TX uDMA channel was pending.
*/
if (dma_running) {
/*
* Verify the channel transfer is done
*/
if (uDMAChannelModeGet(UDMA_CHANNEL_ETH0TX) == UDMA_MODE_STOP) {
/*
* Trigger the transmission of the data.
*/
HWREG(ETH_BASE + MAC_O_TR) = MAC_TR_NEWTX;
/*
* Indicate that a packet has been sent.
*/
dma_running = 0;
}
}
}
void UART1IntHandler(void)
{
const uint32_t dma_rx_primary = UDMA_CHANNEL_UART1RX | UDMA_PRI_SELECT;
uint32_t int_status;
uint32_t mode;
int_status = UARTIntStatus(UART1_BASE, 1);
UARTIntClear(UART1_BASE, int_status);
mode = uDMAChannelModeGet(dma_rx_primary);
// Receive buffer is done.
if(mode == UDMA_MODE_STOP)
{
// Configure the next receive transfer
uart_rx_write_index += UART_RX_BLOCK_SIZE;
if (uart_rx_write_index == UART_RX_BLOCKS_COUNT * UART_RX_BLOCK_SIZE)
{
uart_rx_write_index = 0;
}
uDMAChannelTransferSet(dma_rx_primary, UDMA_MODE_BASIC, (void *)(UART1_BASE + UART_O_DR), &uart_rx_buf[uart_rx_write_index], UART_RX_BLOCK_SIZE);
uDMAChannelEnable(UDMA_CHANNEL_UART1RX);
}
// Check the DMA control table to see if the ping-pong "B" transfer is
// complete. The "B" transfer uses receive buffer "B", and the alternate
// control structure.
//ui32Mode = uDMAChannelModeGet(UDMA_CHANNEL_UART1RX | UDMA_ALT_SELECT);
// If the UART1 DMA TX channel is disabled, that means the TX DMA transfer
// is done.
// if(!uDMAChannelIsEnabled(UDMA_CHANNEL_UART1TX))
// {
// // Start another DMA transfer to UART1 TX.
// uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT,
// UDMA_MODE_BASIC, g_ui8TxBuf,
// (void *)(UART1_BASE + UART_O_DR),
// sizeof(g_ui8TxBuf));
//
// // The uDMA TX channel must be re-enabled.
// uDMAChannelEnable(UDMA_CHANNEL_UART1TX);
// }
}
//*****************************************************************************
//
//! Handles the I2S sound interrupt.
//!
//! This function services the I2S interrupt and will call the callback function
//! provided with the buffer that was given to the SoundBufferPlay() or
//! SoundBufferRead() functions to handle emptying or filling the buffers and
//! starting up DMA transfers again. It is solely the responsibility of the
//! callback functions to continuing sending or receiving data to or from the
//! audio codec.
//!
//! \return None.
//
//*****************************************************************************
void
SoundIntHandler(void)
{
unsigned long ulStatus;
unsigned long *pulTemp;
//
// Get the interrupt status and clear any pending interrupts.
//
ulStatus = I2SIntStatus(I2S0_BASE, 1);
//
// Clear out any interrupts.
//
I2SIntClear(I2S0_BASE, ulStatus);
//
// Handle the RX channel interrupt
//
if(HWREGBITW(&g_ulDMAFlags, FLAG_RX_PENDING))
{
//
// If the RX DMA is done, then start another one using the same
// RX buffer. This keeps the RX running continuously.
//
if(uDMAChannelModeGet(UDMA_CHANNEL_I2S0RX | UDMA_PRI_SELECT) ==
UDMA_MODE_STOP)
{
//
// Save a temp pointer so that the current pointer can be set to
// zero before calling the callback.
//
pulTemp = g_sInBuffers[0].pulData;
//
// If at the mid point the refill the first half of the buffer.
//
if(g_sInBuffers[0].pfnBufferCallback)
{
g_sInBuffers[0].pulData = 0;
g_sInBuffers[0].pfnBufferCallback(pulTemp, BUFFER_EVENT_FULL);
}
}
else if(uDMAChannelModeGet(UDMA_CHANNEL_I2S0RX | UDMA_ALT_SELECT) ==
UDMA_MODE_STOP)
{
//
// Save a temp pointer so that the current pointer can be set to
// zero before calling the callback.
//
pulTemp = g_sInBuffers[1].pulData;
//
// If at the mid point the refill the first half of the buffer.
//
if(g_sInBuffers[1].pfnBufferCallback)
{
g_sInBuffers[1].pulData = 0;
g_sInBuffers[1].pfnBufferCallback(pulTemp, BUFFER_EVENT_FULL);
}
}
//
// If there are no more scheduled buffers then there are no more
// pending DMA transfers.
//
if((g_sInBuffers[0].pulData == 0) && (g_sInBuffers[1].pulData == 0))
{
HWREGBITW(&g_ulDMAFlags, FLAG_RX_PENDING) = 0;
}
}
//
// Handle the TX channel interrupt
//
if(HWREGBITW(&g_ulDMAFlags, FLAG_TX_PENDING))
{
//
// If the TX DMA is done, then call the callback if present.
//
if(uDMAChannelModeGet(UDMA_CHANNEL_I2S0TX | UDMA_PRI_SELECT) ==
UDMA_MODE_STOP)
{
//
// Save a temp pointer so that the current pointer can be set to
// zero before calling the callback.
//
pulTemp = g_sOutBuffers[0].pulData;
//
// If at the mid point then refill the first half of the buffer.
//
if((g_sOutBuffers[0].pfnBufferCallback) &&
(g_sOutBuffers[0].pulData != 0))
{
g_sOutBuffers[0].pulData = 0;
g_sOutBuffers[0].pfnBufferCallback(pulTemp, BUFFER_EVENT_FREE);
}
}
//
// If the TX DMA is done, then call the callback if present.
//
if(uDMAChannelModeGet(UDMA_CHANNEL_I2S0TX | UDMA_ALT_SELECT) ==
UDMA_MODE_STOP)
{
//
// Save a temporary pointer so that the current pointer can be set
// to zero before calling the callback.
//
pulTemp = g_sOutBuffers[1].pulData;
//
// If at the mid point then refill the first half of the buffer.
//
if((g_sOutBuffers[1].pfnBufferCallback) &&
(g_sOutBuffers[1].pulData != 0))
{
g_sOutBuffers[1].pulData = 0;
g_sOutBuffers[1].pfnBufferCallback(pulTemp, BUFFER_EVENT_FREE);
}
}
//
// If no more buffers are pending then clear the flag.
//
if((g_sOutBuffers[0].pulData == 0) && (g_sOutBuffers[1].pulData == 0))
{
HWREGBITW(&g_ulDMAFlags, FLAG_TX_PENDING) = 0;
}
}
}
