static void sbd_transmit_chars(struct sbd_port *sport)
{
struct uart_port *uport = &sport->port;
struct circ_buf *xmit = &sport->port.info->xmit;
unsigned int mask;
int stop_tx;
/* XON/XOFF chars. */
if (sport->port.x_char) {
write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
sport->port.icount.tx++;
sport->port.x_char = 0;
return;
}
/* If nothing to do or stopped or hardware stopped. */
stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
/* Send char. */
if (!stop_tx) {
write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
sport->port.icount.tx++;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&sport->port);
}
/* Are we are done? */
if (stop_tx || uart_circ_empty(xmit)) {
/* Disable tx interrupts. */
mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
mask &= ~M_DUART_IMR_TX;
write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
}
}
static irqreturn_t ks8695uart_tx_chars(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct circ_buf *xmit = &port->state->xmit;
unsigned int count;
if (port->x_char) {
KS8695_CLR_TX_INT();
UART_PUT_CHAR(port, port->x_char);
port->icount.tx++;
port->x_char = 0;
return IRQ_HANDLED;
}
if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
ks8695uart_stop_tx(port);
return IRQ_HANDLED;
}
count = 16; /* fifo size */
while (!uart_circ_empty(xmit) && (count-- > 0)) {
KS8695_CLR_TX_INT();
UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit))
ks8695uart_stop_tx(port);
return IRQ_HANDLED;
}
static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
{
struct circ_buf *xmit = &up->port.state->xmit;
int count;
if (!(lsr & UART_LSR_THRE))
return;
if (up->port.x_char) {
serial_out(up, UART_TX, up->port.x_char);
up->port.icount.tx++;
up->port.x_char = 0;
return;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
serial_omap_stop_tx(&up->port);
return;
}
count = up->port.fifosize / 4;
do {
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
up->port.icount.tx++;
if (uart_circ_empty(xmit))
break;
} while (--count > 0);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
spin_unlock(&up->port.lock);
uart_write_wakeup(&up->port);
spin_lock(&up->port.lock);
}
if (uart_circ_empty(xmit))
serial_omap_stop_tx(&up->port);
}
static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct circ_buf *xmit = &port->state->xmit;
int count;
if (port->x_char) {
clps_writel(port->x_char, UARTDR(port));
port->icount.tx++;
port->x_char = 0;
return IRQ_HANDLED;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
goto disable_tx_irq;
count = port->fifosize >> 1;
do {
clps_writel(xmit->buf[xmit->tail], UARTDR(port));
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
if (uart_circ_empty(xmit))
break;
} while (--count > 0);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
disable_tx_irq:
disable_irq_nosync(TX_IRQ(port));
tx_enabled(port) = 0;
}
return IRQ_HANDLED;
}
static void transmit_chars(struct uart_omap_port *up)
{
struct circ_buf *xmit = &up->port.state->xmit;
int count;
if (up->port.x_char) {
serial_out(up, UART_TX, up->port.x_char);
up->port.icount.tx++;
up->port.x_char = 0;
return;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
serial_omap_stop_tx(&up->port);
return;
}
count = up->port.fifosize / 4;
do {
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
up->port.icount.tx++;
if (uart_circ_empty(xmit)) {
/* This wake lock has to moved out to use case drivers
* which require these.
*/
if (up->plat_hold_wakelock)
(up->plat_hold_wakelock(up, WAKELK_TX));
break;
}
} while (--count > 0);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
if (uart_circ_empty(xmit))
serial_omap_stop_tx(&up->port);
}
static void lh7a40xuart_tx_chars (struct uart_port* port)
{
struct circ_buf* xmit = &port->info->xmit;
int cbTxMax = port->fifosize;
if (port->x_char) {
UR (port, UART_R_DATA) = port->x_char;
++port->icount.tx;
port->x_char = 0;
return;
}
if (uart_circ_empty (xmit) || uart_tx_stopped (port)) {
lh7a40xuart_stop_tx (port, 0);
return;
}
/* Unlike the AMBA UART, the lh7a40x UART does not guarantee
that at least half of the FIFO is empty. Instead, we check
status for every character. Using the AMBA method causes
the transmitter to drop characters. */
do {
UR (port, UART_R_DATA) = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++port->icount.tx;
if (uart_circ_empty(xmit))
break;
} while (!(UR (port, UART_R_STATUS) & nTxRdy)
&& cbTxMax--);
if (uart_circ_chars_pending (xmit) < WAKEUP_CHARS)
uart_write_wakeup (port);
if (uart_circ_empty (xmit))
lh7a40xuart_stop_tx (port, 0);
}
static void sbd_transmit_chars(struct sbd_port *sport)
{
struct uart_port *uport = &sport->port;
struct circ_buf *xmit = &sport->port.state->xmit;
unsigned int mask;
int stop_tx;
if (sport->port.x_char) {
write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
sport->port.icount.tx++;
sport->port.x_char = 0;
return;
}
stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
if (!stop_tx) {
write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
sport->port.icount.tx++;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&sport->port);
}
if (stop_tx || uart_circ_empty(xmit)) {
mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
mask &= ~M_DUART_IMR_TX;
write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
}
}
static void fm3_transmit(struct uart_port *port)
{
struct circ_buf *xmit;
volatile struct fm3_uart_regs *uart_regs = uart_regs_by_port(port);
if (port->x_char) {
fm3_tx_char(uart_regs, port->x_char);
port->x_char = 0;
port->icount.tx++;
return;
}
xmit = &port->state->xmit;
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
fm3_port_stop_tx(port);
return;
}
fm3_tx_char(uart_regs, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
return;
}
static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
{
struct uart_port *port = &sirfport->port;
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
struct circ_buf *xmit = &port->state->xmit;
unsigned long tran_size;
unsigned long tran_start;
unsigned long pio_tx_size;
tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
tran_start = (unsigned long)(xmit->buf + xmit->tail);
if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
!tran_size)
return;
if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
dmaengine_resume(sirfport->tx_dma_chan);
return;
}
if (sirfport->tx_dma_state == TX_DMA_RUNNING)
return;
if (!sirfport->is_atlas7)
wr_regl(port, ureg->sirfsoc_int_en_reg,
rd_regl(port, ureg->sirfsoc_int_en_reg)&
~(uint_en->sirfsoc_txfifo_empty_en));
else
wr_regl(port, SIRFUART_INT_EN_CLR,
uint_en->sirfsoc_txfifo_empty_en);
/*
* DMA requires buffer address and buffer length are both aligned with
* 4 bytes, so we use PIO for
* 1. if address is not aligned with 4bytes, use PIO for the first 1~3
* bytes, and move to DMA for the left part aligned with 4bytes
* 2. if buffer length is not aligned with 4bytes, use DMA for aligned
* part first, move to PIO for the left 1~3 bytes
*/
if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
SIRFUART_IO_MODE);
if (BYTES_TO_ALIGN(tran_start)) {
pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
BYTES_TO_ALIGN(tran_start));
tran_size -= pio_tx_size;
}
if (tran_size < 4)
sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
if (!sirfport->is_atlas7)
wr_regl(port, ureg->sirfsoc_int_en_reg,
rd_regl(port, ureg->sirfsoc_int_en_reg)|
uint_en->sirfsoc_txfifo_empty_en);
else
wr_regl(port, ureg->sirfsoc_int_en_reg,
uint_en->sirfsoc_txfifo_empty_en);
wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
} else {
/* tx transfer mode switch into dma mode */
wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
~SIRFUART_IO_MODE);
wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
tran_size &= ~(0x3);
sirfport->tx_dma_addr = dma_map_single(port->dev,
xmit->buf + xmit->tail,
tran_size, DMA_TO_DEVICE);
sirfport->tx_dma_desc = dmaengine_prep_slave_single(
sirfport->tx_dma_chan, sirfport->tx_dma_addr,
tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
if (!sirfport->tx_dma_desc) {
dev_err(port->dev, "DMA prep slave single fail\n");
return;
}
sirfport->tx_dma_desc->callback =
sirfsoc_uart_tx_dma_complete_callback;
sirfport->tx_dma_desc->callback_param = (void *)sirfport;
sirfport->transfer_size = tran_size;
dmaengine_submit(sirfport->tx_dma_desc);
dma_async_issue_pending(sirfport->tx_dma_chan);
sirfport->tx_dma_state = TX_DMA_RUNNING;
}
}
static void sci_transmit_chars(struct uart_port *port)
{
struct circ_buf *xmit = &port->info->xmit;
unsigned int stopped = uart_tx_stopped(port);
unsigned short status;
unsigned short ctrl;
int count;
status = sci_in(port, SCxSR);
if (!(status & SCxSR_TDxE(port))) {
ctrl = sci_in(port, SCSCR);
if (uart_circ_empty(xmit)) {
ctrl &= ~SCI_CTRL_FLAGS_TIE;
} else {
ctrl |= SCI_CTRL_FLAGS_TIE;
}
sci_out(port, SCSCR, ctrl);
return;
}
if (port->type == PORT_SCIF)
count = scif_txroom(port);
else
count = sci_txroom(port);
do {
unsigned char c;
if (port->x_char) {
c = port->x_char;
port->x_char = 0;
} else if (!uart_circ_empty(xmit) && !stopped) {
c = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
} else {
break;
}
sci_out(port, SCxTDR, c);
port->icount.tx++;
} while (--count > 0);
sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
sci_stop_tx(port);
} else {
ctrl = sci_in(port, SCSCR);
if (port->type == PORT_SCIF) {
sci_in(port, SCxSR); /* Dummy read */
sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
}
ctrl |= SCI_CTRL_FLAGS_TIE;
sci_out(port, SCSCR, ctrl);
}
}
/* Handle data sending */
static void max3107_handletx(struct max3107_port *s)
{
struct circ_buf *xmit = &s->port.state->xmit;
int i;
unsigned long flags;
int len; /* SPI transfer buffer length */
u16 *buf;
if (!s->tx_fifo_empty)
/* Don't send more data before previous data is sent */
return;
if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
/* No data to send or TX is stopped */
return;
if (!s->txbuf) {
dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
return;
}
buf = s->txbuf;
/* Get length of data pending in circular buffer */
len = uart_circ_chars_pending(xmit);
if (len) {
/* Limit to size of TX FIFO */
if (len > MAX3107_TX_FIFO_SIZE)
len = MAX3107_TX_FIFO_SIZE;
pr_debug("txlen %d\n", len);
/* Update TX counter */
s->port.icount.tx += len;
/* TX FIFO will no longer be empty */
s->tx_fifo_empty = 0;
i = 0;
if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
/* First disable TX empty interrupt */
pr_debug("Disabling TE INT\n");
buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
buf[i] |= s->irqen_reg;
i++;
len++;
}
/* Add data to send */
spin_lock_irqsave(&s->port.lock, flags);
for ( ; i < len ; i++) {
buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
buf[i] |= ((u16)xmit->buf[xmit->tail] &
MAX3107_SPI_TX_DATA_MASK);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
}
spin_unlock_irqrestore(&s->port.lock, flags);
if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
/* Enable TX empty interrupt */
pr_debug("Enabling TE INT\n");
buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
buf[i] |= s->irqen_reg;
i++;
len++;
}
if (!s->tx_enabled) {
/* Enable TX */
pr_debug("Enable TX\n");
buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
spin_lock_irqsave(&s->data_lock, flags);
s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
buf[i] |= s->mode1_reg;
spin_unlock_irqrestore(&s->data_lock, flags);
s->tx_enabled = 1;
i++;
len++;
}
/* Perform the SPI transfer */
if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
dev_err(&s->spi->dev,
"SPI transfer TX handling failed\n");
return;
}
}
/* Indicate wake up if circular buffer is getting low on data */
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&s->port);
}
static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
{
unsigned long intr_status;
unsigned long cts_status;
unsigned long flag = TTY_NORMAL;
struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
struct uart_port *port = &sirfport->port;
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
struct uart_state *state = port->state;
struct circ_buf *xmit = &port->state->xmit;
spin_lock(&port->lock);
intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(uint_st,
sirfport->uart_reg->uart_type)))) {
if (intr_status & uint_st->sirfsoc_rxd_brk) {
port->icount.brk++;
if (uart_handle_break(port))
goto recv_char;
}
if (intr_status & uint_st->sirfsoc_rx_oflow) {
port->icount.overrun++;
flag = TTY_OVERRUN;
}
if (intr_status & uint_st->sirfsoc_frm_err) {
port->icount.frame++;
flag = TTY_FRAME;
}
if (intr_status & uint_st->sirfsoc_parity_err) {
port->icount.parity++;
flag = TTY_PARITY;
}
wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
intr_status &= port->read_status_mask;
uart_insert_char(port, intr_status,
uint_en->sirfsoc_rx_oflow_en, 0, flag);
}
recv_char:
if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
(intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
!sirfport->tx_dma_state) {
cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
SIRFUART_AFC_CTS_STATUS;
if (cts_status != 0)
cts_status = 0;
else
cts_status = 1;
uart_handle_cts_change(port, cts_status);
wake_up_interruptible(&state->port.delta_msr_wait);
}
if (!sirfport->rx_dma_chan &&
(intr_status & SIRFUART_RX_IO_INT_ST(uint_st))) {
/*
* chip will trigger continuous RX_TIMEOUT interrupt
* in RXFIFO empty and not trigger if RXFIFO recevice
* data in limit time, original method use RX_TIMEOUT
* will trigger lots of useless interrupt in RXFIFO
* empty.RXFIFO received one byte will trigger RX_DONE
* interrupt.use RX_DONE to wait for data received
* into RXFIFO, use RX_THD/RX_FULL for lots data receive
* and use RX_TIMEOUT for the last left data.
*/
if (intr_status & uint_st->sirfsoc_rx_done) {
if (!sirfport->is_atlas7) {
wr_regl(port, ureg->sirfsoc_int_en_reg,
rd_regl(port, ureg->sirfsoc_int_en_reg)
& ~(uint_en->sirfsoc_rx_done_en));
wr_regl(port, ureg->sirfsoc_int_en_reg,
rd_regl(port, ureg->sirfsoc_int_en_reg)
| (uint_en->sirfsoc_rx_timeout_en));
} else {
wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
uint_en->sirfsoc_rx_done_en);
wr_regl(port, ureg->sirfsoc_int_en_reg,
uint_en->sirfsoc_rx_timeout_en);
}
} else {
if (intr_status & uint_st->sirfsoc_rx_timeout) {
if (!sirfport->is_atlas7) {
wr_regl(port, ureg->sirfsoc_int_en_reg,
rd_regl(port, ureg->sirfsoc_int_en_reg)
& ~(uint_en->sirfsoc_rx_timeout_en));
wr_regl(port, ureg->sirfsoc_int_en_reg,
rd_regl(port, ureg->sirfsoc_int_en_reg)
| (uint_en->sirfsoc_rx_done_en));
} else {
wr_regl(port,
ureg->sirfsoc_int_en_clr_reg,
uint_en->sirfsoc_rx_timeout_en);
wr_regl(port, ureg->sirfsoc_int_en_reg,
uint_en->sirfsoc_rx_done_en);
}
}
sirfsoc_uart_pio_rx_chars(port, port->fifosize);
}
}
spin_unlock(&port->lock);
tty_flip_buffer_push(&state->port);
spin_lock(&port->lock);
if (intr_status & uint_st->sirfsoc_txfifo_empty) {
if (sirfport->tx_dma_chan)
sirfsoc_uart_tx_with_dma(sirfport);
else {
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
spin_unlock(&port->lock);
return IRQ_HANDLED;
} else {
sirfsoc_uart_pio_tx_chars(sirfport,
port->fifosize);
if ((uart_circ_empty(xmit)) &&
(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
ufifo_st->ff_empty(port)))
sirfsoc_uart_stop_tx(port);
}
}
}
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
{
struct s3c24xx_uart_port *ourport = id;
struct uart_port *port = &ourport->port;
struct circ_buf *xmit = &port->state->xmit;
unsigned long flags;
int count, dma_count = 0;
spin_lock_irqsave(&port->lock, flags);
count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
if (ourport->dma && ourport->dma->tx_chan &&
count >= ourport->min_dma_size) {
int align = dma_get_cache_alignment() -
(xmit->tail & (dma_get_cache_alignment() - 1));
if (count-align >= ourport->min_dma_size) {
dma_count = count-align;
count = align;
}
}
if (port->x_char) {
wr_regb(port, S3C2410_UTXH, port->x_char);
port->icount.tx++;
port->x_char = 0;
goto out;
}
/* if there isn't anything more to transmit, or the uart is now
* stopped, disable the uart and exit
*/
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
s3c24xx_serial_stop_tx(port);
goto out;
}
/* try and drain the buffer... */
if (count > port->fifosize) {
count = port->fifosize;
dma_count = 0;
}
while (!uart_circ_empty(xmit) && count > 0) {
if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
break;
wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
count--;
}
if (!count && dma_count) {
s3c24xx_serial_start_tx_dma(ourport, dma_count);
goto out;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
spin_unlock(&port->lock);
uart_write_wakeup(port);
spin_lock(&port->lock);
}
if (uart_circ_empty(xmit))
s3c24xx_serial_stop_tx(port);
out:
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
/*
* ------------------------------------------------------------
* receive_char ()
*
* This routine deals with inputs from any lines.
* ------------------------------------------------------------
*/
static inline void dz_receive_chars(struct dz_port *dport)
{
struct tty_struct *tty = NULL;
struct uart_icount *icount;
int ignore = 0;
unsigned short status, tmp;
unsigned char ch, flag;
/* this code is going to be a problem...
the call to tty_flip_buffer is going to need
to be rethought...
*/
do {
status = dz_in(dport, DZ_RBUF);
/* punt so we don't get duplicate characters */
if (!(status & DZ_DVAL))
goto ignore_char;
ch = UCHAR(status); /* grab the char */
flag = TTY_NORMAL;
#if 0
if (info->is_console) {
if (ch == 0)
return; /* it's a break ... */
}
#endif
tty = dport->port.info->tty;/* now tty points to the proper dev */
icount = &dport->port.icount;
if (!tty)
break;
if (tty->flip.count >= TTY_FLIPBUF_SIZE)
break;
icount->rx++;
/* keep track of the statistics */
if (status & (DZ_OERR | DZ_FERR | DZ_PERR)) {
if (status & DZ_PERR) /* parity error */
icount->parity++;
else if (status & DZ_FERR) /* frame error */
icount->frame++;
if (status & DZ_OERR) /* overrun error */
icount->overrun++;
/* check to see if we should ignore the character
and mask off conditions that should be ignored
*/
if (status & dport->port.ignore_status_mask) {
if (++ignore > 100)
break;
goto ignore_char;
}
/* mask off the error conditions we want to ignore */
tmp = status & dport->port.read_status_mask;
if (tmp & DZ_PERR) {
flag = TTY_PARITY;
#ifdef DEBUG_DZ
debug_console("PERR\n", 5);
#endif
} else if (tmp & DZ_FERR) {
flag = TTY_FRAME;
#ifdef DEBUG_DZ
debug_console("FERR\n", 5);
#endif
}
if (tmp & DZ_OERR) {
#ifdef DEBUG_DZ
debug_console("OERR\n", 5);
#endif
tty_insert_flip_char(tty, ch, flag);
ch = 0;
flag = TTY_OVERRUN;
}
}
tty_insert_flip_char(tty, ch, flag);
ignore_char:
} while (status & DZ_DVAL);
if (tty)
tty_flip_buffer_push(tty);
}
/*
* ------------------------------------------------------------
* transmit_char ()
*
* This routine deals with outputs to any lines.
* ------------------------------------------------------------
*/
static inline void dz_transmit_chars(struct dz_port *dport)
{
struct circ_buf *xmit = &dport->port.info->xmit;
unsigned char tmp;
if (dport->port.x_char) { /* XON/XOFF chars */
dz_out(dport, DZ_TDR, dport->port.x_char);
dport->port.icount.tx++;
dport->port.x_char = 0;
return;
}
/* if nothing to do or stopped or hardware stopped */
if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) {
dz_stop_tx(&dport->port, 0);
return;
}
/*
* if something to do ... (rember the dz has no output fifo so we go
* one char at a time :-<
*/
tmp = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1);
dz_out(dport, DZ_TDR, tmp);
dport->port.icount.tx++;
if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS)
uart_write_wakeup(&dport->port);
/* Are we done */
if (uart_circ_empty(xmit))
dz_stop_tx(&dport->port, 0);
}
/*
* ------------------------------------------------------------
* check_modem_status ()
*
* Only valid for the MODEM line duh !
* ------------------------------------------------------------
*/
static inline void check_modem_status(struct dz_port *dport)
{
unsigned short status;
/* if not ne modem line just return */
if (dport->port.line != DZ_MODEM)
return;
status = dz_in(dport, DZ_MSR);
/* it's easy, since DSR2 is the only bit in the register */
if (status)
dport->port.icount.dsr++;
}
static void pmz_transmit_chars(struct uart_pmac_port *uap)
{
struct circ_buf *xmit;
if (ZS_IS_ASLEEP(uap))
return;
if (ZS_IS_CONS(uap)) {
unsigned char status = read_zsreg(uap, R0);
/* TX still busy? Just wait for the next TX done interrupt.
*
* It can occur because of how we do serial console writes. It would
* be nice to transmit console writes just like we normally would for
* a TTY line. (ie. buffered and TX interrupt driven). That is not
* easy because console writes cannot sleep. One solution might be
* to poll on enough port->xmit space becomming free. -DaveM
*/
if (!(status & Tx_BUF_EMP))
return;
}
uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
if (ZS_REGS_HELD(uap)) {
pmz_load_zsregs(uap, uap->curregs);
uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
}
if (ZS_TX_STOPPED(uap)) {
uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
goto ack_tx_int;
}
if (uap->port.x_char) {
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
write_zsdata(uap, uap->port.x_char);
zssync(uap);
uap->port.icount.tx++;
uap->port.x_char = 0;
return;
}
if (uap->port.info == NULL)
goto ack_tx_int;
xmit = &uap->port.info->xmit;
if (uart_circ_empty(xmit)) {
uart_write_wakeup(&uap->port);
goto ack_tx_int;
}
if (uart_tx_stopped(&uap->port))
goto ack_tx_int;
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
write_zsdata(uap, xmit->buf[xmit->tail]);
zssync(uap);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
uap->port.icount.tx++;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uap->port);
return;
ack_tx_int:
write_zsreg(uap, R0, RES_Tx_P);
zssync(uap);
}
static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
{
unsigned long intr_status;
unsigned long cts_status;
unsigned long flag = TTY_NORMAL;
struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
struct uart_port *port = &sirfport->port;
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
struct uart_state *state = port->state;
struct circ_buf *xmit = &port->state->xmit;
spin_lock(&port->lock);
intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(port, uint_st)))) {
if (intr_status & uint_st->sirfsoc_rxd_brk) {
port->icount.brk++;
if (uart_handle_break(port))
goto recv_char;
}
if (intr_status & uint_st->sirfsoc_rx_oflow)
port->icount.overrun++;
if (intr_status & uint_st->sirfsoc_frm_err) {
port->icount.frame++;
flag = TTY_FRAME;
}
if (intr_status & uint_st->sirfsoc_parity_err)
flag = TTY_PARITY;
wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
intr_status &= port->read_status_mask;
uart_insert_char(port, intr_status,
uint_en->sirfsoc_rx_oflow_en, 0, flag);
}
recv_char:
if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
(intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
!sirfport->tx_dma_state) {
cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
SIRFUART_AFC_CTS_STATUS;
if (cts_status != 0)
cts_status = 0;
else
cts_status = 1;
uart_handle_cts_change(port, cts_status);
wake_up_interruptible(&state->port.delta_msr_wait);
}
if (sirfport->rx_dma_chan) {
if (intr_status & uint_st->sirfsoc_rx_timeout)
sirfsoc_uart_handle_rx_tmo(sirfport);
if (intr_status & uint_st->sirfsoc_rx_done)
sirfsoc_uart_handle_rx_done(sirfport);
} else {
if (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))
sirfsoc_uart_pio_rx_chars(port,
SIRFSOC_UART_IO_RX_MAX_CNT);
}
spin_unlock(&port->lock);
tty_flip_buffer_push(&state->port);
spin_lock(&port->lock);
if (intr_status & uint_st->sirfsoc_txfifo_empty) {
if (sirfport->tx_dma_chan)
sirfsoc_uart_tx_with_dma(sirfport);
else {
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
spin_unlock(&port->lock);
return IRQ_HANDLED;
} else {
sirfsoc_uart_pio_tx_chars(sirfport,
SIRFSOC_UART_IO_TX_REASONABLE_CNT);
if ((uart_circ_empty(xmit)) &&
(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
ufifo_st->ff_empty(port->line)))
sirfsoc_uart_stop_tx(port);
}
}
}
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
/*
* Transmit characters, refill buffer descriptor, if possible
*/
static int cpm_uart_tx_pump(struct uart_port *port)
{
cbd_t __iomem *bdp;
u8 *p;
int count;
struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
struct circ_buf *xmit = &port->info->xmit;
/* Handle xon/xoff */
if (port->x_char) {
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
*p++ = port->x_char;
out_be16(&bdp->cbd_datlen, 1);
setbits16(&bdp->cbd_sc, BD_SC_READY);
/* Get next BD. */
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
pinfo->tx_cur = bdp;
port->icount.tx++;
port->x_char = 0;
return 1;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
cpm_uart_stop_tx(port);
return 0;
}
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
xmit->tail != xmit->head) {
count = 0;
p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
while (count < pinfo->tx_fifosize) {
*p++ = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
count++;
if (xmit->head == xmit->tail)
break;
}
out_be16(&bdp->cbd_datlen, count);
setbits16(&bdp->cbd_sc, BD_SC_READY);
/* Get next BD. */
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
}
pinfo->tx_cur = bdp;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
cpm_uart_stop_tx(port);
return 0;
}
return 1;
}
static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
{
unsigned long intr_status;
unsigned long cts_status;
unsigned long flag = TTY_NORMAL;
struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
struct uart_port *port = &sirfport->port;
struct uart_state *state = port->state;
struct circ_buf *xmit = &port->state->xmit;
spin_lock(&port->lock);
intr_status = rd_regl(port, SIRFUART_INT_STATUS);
wr_regl(port, SIRFUART_INT_STATUS, intr_status);
intr_status &= rd_regl(port, SIRFUART_INT_EN);
if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT))) {
if (intr_status & SIRFUART_RXD_BREAK) {
if (uart_handle_break(port))
goto recv_char;
uart_insert_char(port, intr_status,
SIRFUART_RX_OFLOW, 0, TTY_BREAK);
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
if (intr_status & SIRFUART_RX_OFLOW)
port->icount.overrun++;
if (intr_status & SIRFUART_FRM_ERR) {
port->icount.frame++;
flag = TTY_FRAME;
}
if (intr_status & SIRFUART_PARITY_ERR)
flag = TTY_PARITY;
wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
intr_status &= port->read_status_mask;
uart_insert_char(port, intr_status,
SIRFUART_RX_OFLOW_INT, 0, flag);
}
recv_char:
if (intr_status & SIRFUART_CTS_INT_EN) {
cts_status = !(rd_regl(port, SIRFUART_AFC_CTRL) &
SIRFUART_CTS_IN_STATUS);
if (cts_status != 0) {
uart_handle_cts_change(port, 1);
} else {
uart_handle_cts_change(port, 0);
wake_up_interruptible(&state->port.delta_msr_wait);
}
}
if (intr_status & SIRFUART_RX_IO_INT_EN)
sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
if (intr_status & SIRFUART_TX_INT_EN) {
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
spin_unlock(&port->lock);
return IRQ_HANDLED;
} else {
sirfsoc_uart_pio_tx_chars(sirfport,
SIRFSOC_UART_IO_TX_REASONABLE_CNT);
if ((uart_circ_empty(xmit)) &&
(rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
SIRFUART_FIFOEMPTY_MASK(port)))
sirfsoc_uart_stop_tx(port);
}
}
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
{
struct tty_struct *tty = NULL;
unsigned int status, ch, flg;
static struct timeval anomaly_start = { .tv_sec = 0 };
status = UART_GET_LSR(uart);
UART_CLEAR_LSR(uart);
ch = UART_GET_CHAR(uart);
uart->port.icount.rx++;
#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
if (kgdb_connected && kgdboc_port_line == uart->port.line)
if (ch == 0x3) {/* Ctrl + C */
kgdb_breakpoint();
return;
}
if (!uart->port.info || !uart->port.info->tty)
return;
#endif
tty = uart->port.info->tty;
if (ANOMALY_05000363) {
/* The BF533 (and BF561) family of processors have a nice anomaly
* where they continuously generate characters for a "single" break.
* We have to basically ignore this flood until the "next" valid
* character comes across. Due to the nature of the flood, it is
* not possible to reliably catch bytes that are sent too quickly
* after this break. So application code talking to the Blackfin
* which sends a break signal must allow at least 1.5 character
* times after the end of the break for things to stabilize. This
* timeout was picked as it must absolutely be larger than 1
* character time +/- some percent. So 1.5 sounds good. All other
* Blackfin families operate properly. Woo.
*/
if (anomaly_start.tv_sec) {
struct timeval curr;
suseconds_t usecs;
if ((~ch & (~ch + 1)) & 0xff)
goto known_good_char;
do_gettimeofday(&curr);
if (curr.tv_sec - anomaly_start.tv_sec > 1)
goto known_good_char;
usecs = 0;
if (curr.tv_sec != anomaly_start.tv_sec)
usecs += USEC_PER_SEC;
usecs += curr.tv_usec - anomaly_start.tv_usec;
if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
goto known_good_char;
if (ch)
anomaly_start.tv_sec = 0;
else
anomaly_start = curr;
return;
known_good_char:
status &= ~BI;
anomaly_start.tv_sec = 0;
}
}
if (status & BI) {
if (ANOMALY_05000363)
if (bfin_revid() < 5)
do_gettimeofday(&anomaly_start);
uart->port.icount.brk++;
if (uart_handle_break(&uart->port))
goto ignore_char;
status &= ~(PE | FE);
}
if (status & PE)
uart->port.icount.parity++;
if (status & OE)
uart->port.icount.overrun++;
if (status & FE)
uart->port.icount.frame++;
status &= uart->port.read_status_mask;
if (status & BI)
flg = TTY_BREAK;
else if (status & PE)
flg = TTY_PARITY;
else if (status & FE)
flg = TTY_FRAME;
else
flg = TTY_NORMAL;
if (uart_handle_sysrq_char(&uart->port, ch))
goto ignore_char;
uart_insert_char(&uart->port, status, OE, ch, flg);
ignore_char:
tty_flip_buffer_push(tty);
}
static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
{
struct circ_buf *xmit = &uart->port.info->xmit;
/*
* Check the modem control lines before
* transmitting anything.
*/
bfin_serial_mctrl_check(uart);
if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
#ifdef CONFIG_BF54x
/* Clear TFI bit */
UART_PUT_LSR(uart, TFI);
#endif
UART_CLEAR_IER(uart, ETBEI);
return;
}
if (uart->port.x_char) {
UART_PUT_CHAR(uart, uart->port.x_char);
uart->port.icount.tx++;
uart->port.x_char = 0;
}
while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
uart->port.icount.tx++;
SSYNC();
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uart->port);
}
static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
{
struct bfin_serial_port *uart = dev_id;
spin_lock(&uart->port.lock);
while (UART_GET_LSR(uart) & DR)
bfin_serial_rx_chars(uart);
spin_unlock(&uart->port.lock);
return IRQ_HANDLED;
}
static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
{
struct bfin_serial_port *uart = dev_id;
spin_lock(&uart->port.lock);
if (UART_GET_LSR(uart) & THRE)
bfin_serial_tx_chars(uart);
spin_unlock(&uart->port.lock);
return IRQ_HANDLED;
}
#endif
#ifdef CONFIG_SERIAL_BFIN_DMA
static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
{
struct circ_buf *xmit = &uart->port.info->xmit;
uart->tx_done = 0;
/*
* Check the modem control lines before
* transmitting anything.
*/
bfin_serial_mctrl_check(uart);
if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
uart->tx_count = 0;
uart->tx_done = 1;
return;
}
if (uart->port.x_char) {
UART_PUT_CHAR(uart, uart->port.x_char);
uart->port.icount.tx++;
uart->port.x_char = 0;
}
uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
uart->tx_count = UART_XMIT_SIZE - xmit->tail;
blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
(unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
set_dma_config(uart->tx_dma_channel,
set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
INTR_ON_BUF,
DIMENSION_LINEAR,
DATA_SIZE_8,
DMA_SYNC_RESTART));
set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
set_dma_x_modify(uart->tx_dma_channel, 1);
enable_dma(uart->tx_dma_channel);
UART_SET_IER(uart, ETBEI);
}
static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
{
struct tty_struct *tty = uart->port.info->port.tty;
int i, flg, status;
status = UART_GET_LSR(uart);
UART_CLEAR_LSR(uart);
uart->port.icount.rx +=
CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
UART_XMIT_SIZE);
if (status & BI) {
uart->port.icount.brk++;
if (uart_handle_break(&uart->port))
goto dma_ignore_char;
status &= ~(PE | FE);
}
if (status & PE)
uart->port.icount.parity++;
if (status & OE)
uart->port.icount.overrun++;
if (status & FE)
uart->port.icount.frame++;
status &= uart->port.read_status_mask;
if (status & BI)
flg = TTY_BREAK;
else if (status & PE)
flg = TTY_PARITY;
else if (status & FE)
flg = TTY_FRAME;
else
flg = TTY_NORMAL;
for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
if (i >= UART_XMIT_SIZE)
i = 0;
if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
uart_insert_char(&uart->port, status, OE,
uart->rx_dma_buf.buf[i], flg);
}
dma_ignore_char:
tty_flip_buffer_push(tty);
}
void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
{
int x_pos, pos, flags;
spin_lock_irqsave(&uart->port.lock, flags);
uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
uart->rx_dma_nrows = 0;
x_pos = DMA_RX_XCOUNT - x_pos;
if (x_pos == DMA_RX_XCOUNT)
x_pos = 0;
pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
if (pos != uart->rx_dma_buf.tail) {
uart->rx_dma_buf.head = pos;
bfin_serial_dma_rx_chars(uart);
uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
}
spin_unlock_irqrestore(&uart->port.lock, flags);
mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
}
static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
struct zilog_channel *channel)
{
struct circ_buf *xmit;
if (ZS_IS_CONS(up)) {
unsigned char status = readb(&channel->control);
ZSDELAY();
/* TX still busy? Just wait for the next TX done interrupt.
*
* It can occur because of how we do serial console writes. It would
* be nice to transmit console writes just like we normally would for
* a TTY line. (ie. buffered and TX interrupt driven). That is not
* easy because console writes cannot sleep. One solution might be
* to poll on enough port->xmit space becoming free. -DaveM
*/
if (!(status & Tx_BUF_EMP))
return;
}
up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
if (ZS_REGS_HELD(up)) {
__load_zsregs(channel, up->curregs);
up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
}
if (ZS_TX_STOPPED(up)) {
up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
goto ack_tx_int;
}
if (up->port.x_char) {
up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
writeb(up->port.x_char, &channel->data);
ZSDELAY();
ZS_WSYNC(channel);
up->port.icount.tx++;
up->port.x_char = 0;
return;
}
if (up->port.state == NULL)
goto ack_tx_int;
xmit = &up->port.state->xmit;
if (uart_circ_empty(xmit))
goto ack_tx_int;
if (uart_tx_stopped(&up->port))
goto ack_tx_int;
up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
writeb(xmit->buf[xmit->tail], &channel->data);
ZSDELAY();
ZS_WSYNC(channel);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
up->port.icount.tx++;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
return;
ack_tx_int:
writeb(RES_Tx_P, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
}
static int omap_8250_tx_dma(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
struct omap8250_priv *priv = p->port.private_data;
struct circ_buf *xmit = &p->port.state->xmit;
struct dma_async_tx_descriptor *desc;
unsigned int skip_byte = 0;
int ret;
if (dma->tx_running)
return 0;
if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
/*
* Even if no data, we need to return an error for the two cases
* below so serial8250_tx_chars() is invoked and properly clears
* THRI and/or runtime suspend.
*/
if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
ret = -EBUSY;
goto err;
}
if (p->ier & UART_IER_THRI) {
p->ier &= ~UART_IER_THRI;
serial_out(p, UART_IER, p->ier);
}
return 0;
}
dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
if (priv->habit & OMAP_DMA_TX_KICK) {
u8 tx_lvl;
/*
* We need to put the first byte into the FIFO in order to start
* the DMA transfer. For transfers smaller than four bytes we
* don't bother doing DMA at all. It seem not matter if there
* are still bytes in the FIFO from the last transfer (in case
* we got here directly from omap_8250_dma_tx_complete()). Bytes
* leaving the FIFO seem not to trigger the DMA transfer. It is
* really the byte that we put into the FIFO.
* If the FIFO is already full then we most likely got here from
* omap_8250_dma_tx_complete(). And this means the DMA engine
* just completed its work. We don't have to wait the complete
* 86us at 115200,8n1 but around 60us (not to mention lower
* baudrates). So in that case we take the interrupt and try
* again with an empty FIFO.
*/
tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
if (tx_lvl == p->tx_loadsz) {
ret = -EBUSY;
goto err;
}
if (dma->tx_size < 4) {
ret = -EINVAL;
goto err;
}
skip_byte = 1;
}
desc = dmaengine_prep_slave_single(dma->txchan,
dma->tx_addr + xmit->tail + skip_byte,
dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
ret = -EBUSY;
goto err;
}
dma->tx_running = 1;
desc->callback = omap_8250_dma_tx_complete;
desc->callback_param = p;
dma->tx_cookie = dmaengine_submit(desc);
dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
dma_async_issue_pending(dma->txchan);
if (dma->tx_err)
dma->tx_err = 0;
if (p->ier & UART_IER_THRI) {
p->ier &= ~UART_IER_THRI;
serial_out(p, UART_IER, p->ier);
}
if (skip_byte)
serial_out(p, UART_TX, xmit->buf[xmit->tail]);
return 0;
err:
dma->tx_err = 1;
return ret;
}
/*
* Transmit characters, refill buffer descriptor, if possible
*/
static int cpm_uart_tx_pump(struct uart_port *port)
{
volatile cbd_t *bdp;
unsigned char *p;
int count;
struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
struct circ_buf *xmit = &port->info->xmit;
/* Handle xon/xoff */
if (port->x_char) {
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
p = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
*p++ = port->x_char;
bdp->cbd_datlen = 1;
bdp->cbd_sc |= BD_SC_READY;
/* Get next BD. */
if (bdp->cbd_sc & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
pinfo->tx_cur = bdp;
port->icount.tx++;
port->x_char = 0;
return 1;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
cpm_uart_stop_tx(port);
return 0;
}
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
while (!(bdp->cbd_sc & BD_SC_READY) && (xmit->tail != xmit->head)) {
count = 0;
p = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
while (count < pinfo->tx_fifosize) {
*p++ = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
count++;
if (xmit->head == xmit->tail)
break;
}
bdp->cbd_datlen = count;
bdp->cbd_sc |= BD_SC_READY;
__asm__("eieio");
/* Get next BD. */
if (bdp->cbd_sc & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
}
pinfo->tx_cur = bdp;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
cpm_uart_stop_tx(port);
return 0;
}
return 1;
}
/**
* are_driver8250_uarts_active() - Check if any ports managed by this
* driver are currently busy. This should be called with interrupts
* disabled.
*/
int are_driveromap_uarts_active(int *driver8250_managed)
{
struct circ_buf *xmit;
unsigned int status;
int j;
*driver8250_managed = 0x7; /* OMAP has 3 UART instances */
for (j = 0; j < 3; j++) {
struct uart_omap_port *up = ui[j];
/* check ownership of port */
/* Check only ports managed by this driver and open */
if((up->port.dev == NULL) || (up->port.type == PORT_UNKNOWN)){
*driver8250_managed &= ~(1 << j);
continue;
}
/* driver owns this port but its closed */
if (up->port.info == NULL)
continue;
/* check for recent driver activity */
/* if from now to last activty < 5 second keep clocks on */
if ((jiffies_to_msecs(jiffies - isr8250_activity) < 5000))
return 1;
/* check for any current pending activity */
/* Any queued work in ring buffer which can be handled still? */
xmit = &up->port.info->xmit;
if (!(uart_circ_empty(xmit) || uart_tx_stopped(&up->port)))
return 1;
status = serial_in(up, UART_LSR);
/* TX hardware not empty/ */
if (!(status & (UART_LSR_TEMT | UART_LSR_THRE)))
return 1;
/* Any rx activity? */
if (status & UART_LSR_DR)
return 1;
/* Any modem activity */
status = serial_in(up, UART_MSR);
if (!((status & UART_MSR_ANY_DELTA) == 0))
return 1;
if (up->use_dma) {
/*
* Silicon Errata i291 workaround.
* UART Module has to be put in force idle if it is
* configured in DMA mode and when there is no activity
* expected.
*/
unsigned int tmp;
tmp = (serial_in(up, UART_OMAP_SYSC) & 0x7);
serial_out(up, UART_OMAP_SYSC, tmp); /* force-idle */
}
}
if(*driver8250_managed) {
return 0;
}
return 1;
}
static void
transmit_chars_no_dma(struct uart_cris_port *up)
{
int max_count;
struct circ_buf *xmit = &up->port.state->xmit;
void __iomem *regi_ser = up->regi_ser;
reg_ser_r_stat_din rstat;
reg_ser_rw_ack_intr ack_intr = { .tr_rdy = regk_ser_yes };
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
/* No more to send, so disable the interrupt. */
reg_ser_rw_intr_mask intr_mask;
intr_mask = REG_RD(ser, regi_ser, rw_intr_mask);
intr_mask.tr_rdy = 0;
intr_mask.tr_empty = 0;
REG_WR(ser, regi_ser, rw_intr_mask, intr_mask);
up->write_ongoing = 0;
return;
}
/* If the serport is fast, we send up to max_count bytes before
exiting the loop. */
max_count = 64;
do {
reg_ser_rw_dout dout = { .data = xmit->buf[xmit->tail] };
REG_WR(ser, regi_ser, rw_dout, dout);
REG_WR(ser, regi_ser, rw_ack_intr, ack_intr);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
up->port.icount.tx++;
if (xmit->head == xmit->tail)
break;
rstat = REG_RD(ser, regi_ser, r_stat_din);
} while ((--max_count > 0) && rstat.tr_rdy);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
}
static void receive_chars_no_dma(struct uart_cris_port *up)
{
reg_ser_rs_stat_din stat_din;
reg_ser_r_stat_din rstat;
struct tty_port *port;
struct uart_icount *icount;
int max_count = 16;
char flag;
reg_ser_rw_ack_intr ack_intr = { 0 };
rstat = REG_RD(ser, up->regi_ser, r_stat_din);
icount = &up->port.icount;
port = &up->port.state->port;
do {
stat_din = REG_RD(ser, up->regi_ser, rs_stat_din);
flag = TTY_NORMAL;
ack_intr.dav = 1;
REG_WR(ser, up->regi_ser, rw_ack_intr, ack_intr);
icount->rx++;
if (stat_din.framing_err | stat_din.par_err | stat_din.orun) {
if (stat_din.data == 0x00 &&
stat_din.framing_err) {
/* Most likely a break. */
flag = TTY_BREAK;
icount->brk++;
} else if (stat_din.par_err) {
flag = TTY_PARITY;
icount->parity++;
} else if (stat_din.orun) {
flag = TTY_OVERRUN;
icount->overrun++;
} else if (stat_din.framing_err) {
flag = TTY_FRAME;
icount->frame++;
}
}
/*
* If this becomes important, we probably *could* handle this
* gracefully by keeping track of the unhandled character.
*/
if (!tty_insert_flip_char(port, stat_din.data, flag))
panic("%s: No tty buffer space", __func__);
rstat = REG_RD(ser, up->regi_ser, r_stat_din);
} while (rstat.dav && (max_count-- > 0));
spin_unlock(&up->port.lock);
tty_flip_buffer_push(port);
spin_lock(&up->port.lock);
}
static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
{
struct tty_struct *tty = NULL;
unsigned int status, ch, flg;
static struct timeval anomaly_start = { .tv_sec = 0 };
status = UART_GET_LSR(uart);
UART_CLEAR_LSR(uart);
ch = UART_GET_CHAR(uart);
uart->port.icount.rx++;
#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
if (kgdb_connected && kgdboc_port_line == uart->port.line
&& kgdboc_break_enabled)
if (ch == 0x3) {/* Ctrl + C */
kgdb_breakpoint();
return;
}
if (!uart->port.state || !uart->port.state->port.tty)
return;
#endif
tty = uart->port.state->port.tty;
if (ANOMALY_05000363) {
/* The BF533 (and BF561) family of processors have a nice anomaly
* where they continuously generate characters for a "single" break.
* We have to basically ignore this flood until the "next" valid
* character comes across. Due to the nature of the flood, it is
* not possible to reliably catch bytes that are sent too quickly
* after this break. So application code talking to the Blackfin
* which sends a break signal must allow at least 1.5 character
* times after the end of the break for things to stabilize. This
* timeout was picked as it must absolutely be larger than 1
* character time +/- some percent. So 1.5 sounds good. All other
* Blackfin families operate properly. Woo.
*/
if (anomaly_start.tv_sec) {
struct timeval curr;
suseconds_t usecs;
if ((~ch & (~ch + 1)) & 0xff)
goto known_good_char;
do_gettimeofday(&curr);
if (curr.tv_sec - anomaly_start.tv_sec > 1)
goto known_good_char;
usecs = 0;
if (curr.tv_sec != anomaly_start.tv_sec)
usecs += USEC_PER_SEC;
usecs += curr.tv_usec - anomaly_start.tv_usec;
if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
goto known_good_char;
if (ch)
anomaly_start.tv_sec = 0;
else
anomaly_start = curr;
return;
known_good_char:
status &= ~BI;
anomaly_start.tv_sec = 0;
}
}
if (status & BI) {
if (ANOMALY_05000363)
if (bfin_revid() < 5)
do_gettimeofday(&anomaly_start);
uart->port.icount.brk++;
if (uart_handle_break(&uart->port))
goto ignore_char;
status &= ~(PE | FE);
}
if (status & PE)
uart->port.icount.parity++;
if (status & OE)
uart->port.icount.overrun++;
if (status & FE)
uart->port.icount.frame++;
status &= uart->port.read_status_mask;
if (status & BI)
flg = TTY_BREAK;
else if (status & PE)
flg = TTY_PARITY;
else if (status & FE)
flg = TTY_FRAME;
else
flg = TTY_NORMAL;
if (uart_handle_sysrq_char(&uart->port, ch))
goto ignore_char;
uart_insert_char(&uart->port, status, OE, ch, flg);
ignore_char:
tty_flip_buffer_push(tty);
}
static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
{
struct circ_buf *xmit = &uart->port.state->xmit;
if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
#ifdef CONFIG_BF54x
/* Clear TFI bit */
UART_PUT_LSR(uart, TFI);
#endif
/* Anomaly notes:
* 05000215 - we always clear ETBEI within last UART TX
* interrupt to end a string. It is always set
* when start a new tx.
*/
UART_CLEAR_IER(uart, ETBEI);
return;
}
if (uart->port.x_char) {
UART_PUT_CHAR(uart, uart->port.x_char);
uart->port.icount.tx++;
uart->port.x_char = 0;
}
while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
uart->port.icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uart->port);
}
static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
{
struct bfin_serial_port *uart = dev_id;
while (UART_GET_LSR(uart) & DR)
bfin_serial_rx_chars(uart);
return IRQ_HANDLED;
}
static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
{
struct bfin_serial_port *uart = dev_id;
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
uart->scts = 0;
uart_handle_cts_change(&uart->port, uart->scts);
}
#endif
spin_lock(&uart->port.lock);
if (UART_GET_LSR(uart) & THRE)
bfin_serial_tx_chars(uart);
spin_unlock(&uart->port.lock);
return IRQ_HANDLED;
}
#endif
#ifdef CONFIG_SERIAL_BFIN_DMA
static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
{
struct circ_buf *xmit = &uart->port.state->xmit;
uart->tx_done = 0;
if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
uart->tx_count = 0;
uart->tx_done = 1;
return;
}
if (uart->port.x_char) {
UART_PUT_CHAR(uart, uart->port.x_char);
uart->port.icount.tx++;
uart->port.x_char = 0;
}
uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
uart->tx_count = UART_XMIT_SIZE - xmit->tail;
blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
(unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
set_dma_config(uart->tx_dma_channel,
set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
INTR_ON_BUF,
DIMENSION_LINEAR,
DATA_SIZE_8,
DMA_SYNC_RESTART));
set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
set_dma_x_modify(uart->tx_dma_channel, 1);
SSYNC();
enable_dma(uart->tx_dma_channel);
UART_SET_IER(uart, ETBEI);
}
static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
{
struct tty_struct *tty = uart->port.state->port.tty;
int i, flg, status;
status = UART_GET_LSR(uart);
UART_CLEAR_LSR(uart);
uart->port.icount.rx +=
CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
UART_XMIT_SIZE);
if (status & BI) {
uart->port.icount.brk++;
if (uart_handle_break(&uart->port))
goto dma_ignore_char;
status &= ~(PE | FE);
}
if (status & PE)
uart->port.icount.parity++;
if (status & OE)
uart->port.icount.overrun++;
if (status & FE)
uart->port.icount.frame++;
status &= uart->port.read_status_mask;
if (status & BI)
flg = TTY_BREAK;
else if (status & PE)
flg = TTY_PARITY;
else if (status & FE)
flg = TTY_FRAME;
else
flg = TTY_NORMAL;
for (i = uart->rx_dma_buf.tail; ; i++) {
if (i >= UART_XMIT_SIZE)
i = 0;
if (i == uart->rx_dma_buf.head)
break;
if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
uart_insert_char(&uart->port, status, OE,
uart->rx_dma_buf.buf[i], flg);
}
dma_ignore_char:
tty_flip_buffer_push(tty);
}
void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
{
int x_pos, pos;
dma_disable_irq_nosync(uart->rx_dma_channel);
spin_lock_bh(&uart->rx_lock);
/* 2D DMA RX buffer ring is used. Because curr_y_count and
* curr_x_count can't be read as an atomic operation,
* curr_y_count should be read before curr_x_count. When
* curr_x_count is read, curr_y_count may already indicate
* next buffer line. But, the position calculated here is
* still indicate the old line. The wrong position data may
* be smaller than current buffer tail, which cause garbages
* are received if it is not prohibit.
*/
uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
uart->rx_dma_nrows = 0;
x_pos = DMA_RX_XCOUNT - x_pos;
if (x_pos == DMA_RX_XCOUNT)
x_pos = 0;
pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
/* Ignore receiving data if new position is in the same line of
* current buffer tail and small.
*/
if (pos > uart->rx_dma_buf.tail ||
uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
uart->rx_dma_buf.head = pos;
bfin_serial_dma_rx_chars(uart);
uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
}
spin_unlock_bh(&uart->rx_lock);
dma_enable_irq(uart->rx_dma_channel);
mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
}
